742b535e40
Add PPC Freescale e500mc and e5500 subtargets.
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Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to
the PowerPC backend.
Patch by Tobias von Koch.
llvm-svn: 162764
2012-08-28 16:12:39 +00:00
460e94d842
Add support for the PPC isel instruction.
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The isel (integer select) instruction is supported on the 440 and A2
embedded cores and on the POWER7.
llvm-svn: 159045
2012-06-22 23:10:08 +00:00
f1cc96ab50
Fixes for PPC host detection and features.
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POWER4 is a 64-bit CPU (better matched to the 970).
The g3 is really the 750 (no altivec), the g4+ is the 74xx (not the 750).
Patch by Andreas Tobler.
llvm-svn: 158363
2012-06-12 16:39:23 +00:00
bddc916f2b
Enable MFOCRF generation on the PPC A2 core.
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llvm-svn: 158324
2012-06-11 19:57:04 +00:00
bfd3d08d18
Rename the PPC target feature gpul to mfocrf.
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The PPC target feature gpul (IsGigaProcessor) was only used for one thing:
To enable the generation of the MFOCRF instruction. Furthermore, this
instruction is available on other PPC cores outside of the G5 line. This
feature now corresponds to the HasMFOCRF flag.
No functionality change.
llvm-svn: 158323
2012-06-11 19:57:01 +00:00
f2b9c38d6f
Add POWER6 and POWER7 CPU types to the PPC backend.
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No functional change; these will be used by upcoming scheduler enhancements.
llvm-svn: 158313
2012-06-11 15:43:08 +00:00
3ecfa7b277
Fix some 80-col. violations I introduced with the A2 PPC64 core.
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llvm-svn: 153852
2012-04-01 21:20:14 +00:00
9f9f8929ee
Add instruction itinerary for the PPC64 A2 core.
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This adds a full itinerary for IBM's PPC64 A2 embedded core. These
cores form the basis for the CPUs in the new IBM BG/Q supercomputer.
llvm-svn: 153842
2012-04-01 19:22:40 +00:00
b22310fda6
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
...
llvm-svn: 150878
2012-02-18 12:03:15 +00:00
6fa5697af0
Add PPC 440 scheduler and some associated tests
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llvm-svn: 142170
2011-10-17 04:03:49 +00:00
4903379088
initial test commit (remove whitespace)
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llvm-svn: 141972
2011-10-14 18:54:13 +00:00
045e04dbfe
dissolve some more hacks.
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llvm-svn: 119115
2010-11-15 03:53:53 +00:00
b93331f3be
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
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When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
llvm-svn: 100384
2010-04-05 03:10:20 +00:00
977e7be9d4
Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.
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llvm-svn: 59953
2008-11-24 07:34:46 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
4f2e4e0f92
Switch PPC return lower to use an autogenerated CC description.
...
llvm-svn: 34940
2007-03-06 00:59:59 +00:00
59e7a777da
Honor cpu directive, take two.
...
llvm-svn: 32492
2006-12-12 20:57:08 +00:00
a35f306740
Rename some subtarget features. A CPU now can *have* 64-bit instructions,
...
can in 32-bit mode we can choose to optionally *use* 64-bit registers.
llvm-svn: 28824
2006-06-16 17:34:12 +00:00
305c49579c
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
...
llvm-svn: 28378
2006-05-18 00:12:58 +00:00
dcec882286
Remove PointerType from class Target
...
llvm-svn: 28368
2006-05-17 21:20:27 +00:00
6e90062416
add callee saved vector regs
...
llvm-svn: 26805
2006-03-16 22:07:06 +00:00
7579cfb1a0
Mark instructions that are cracked by the PPC970 decoder as such.
...
llvm-svn: 26720
2006-03-13 05:15:10 +00:00
51348c5f27
Several big changes:
...
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
type instead of a table in the .cpp file. Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
accurately.
llvm-svn: 26719
2006-03-12 09:13:49 +00:00
b9f35f06bc
Add a subtarget feature for the stfiwx instruction. I know the G5 has it,
...
but I don't know what other PPC impls do. If someone could update the proc
table, I would appreciate it :)
llvm-svn: 26421
2006-02-28 07:08:22 +00:00
d98701c639
Subtarget feature can now set any variable to any value
...
llvm-svn: 25678
2006-01-27 08:09:42 +00:00
53ad110490
Add attribute name and type to SubtargetFeatures.
...
llvm-svn: 24012
2005-10-26 17:28:23 +00:00
abcce5c4b3
mark this as beta
...
llvm-svn: 23906
2005-10-23 22:23:45 +00:00
a389f0d8fa
rearrange things a bit so that instructions can use subtarget features in the
...
future.
llvm-svn: 23902
2005-10-23 22:08:13 +00:00
0d4923b975
improve -help output
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llvm-svn: 23892
2005-10-23 05:28:51 +00:00
13a19453d2
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's
...
to group appropriately and provide cues to maintainers that the lists don't
need to be ordered.
llvm-svn: 23880
2005-10-22 08:04:24 +00:00
c5d511c4d9
64-bit reg support should not be enabled by default, as support isn't complete.
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llvm-svn: 23878
2005-10-21 22:15:43 +00:00
9ed9032e22
Plugin new subtarget backend into the build.
...
llvm-svn: 23870
2005-10-21 19:05:19 +00:00
74ab9960f2
Added InstrSchedClass to each of the PowerPC Instructions.
...
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.
llvm-svn: 23830
2005-10-19 19:51:16 +00:00
7503d46feb
Rename PowerPC*.td -> PPC*.td
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llvm-svn: 23740
2005-10-14 23:40:39 +00:00
0921e3bfc1
Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td
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llvm-svn: 23738
2005-10-14 23:37:35 +00:00
Hal Finkel