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4213 Commits

Author SHA1 Message Date
David Blaikie dcbd160804 Remove unused member & unnecessary semicolon. 
llvm-svn: 166694
 2012-10-25 17:04:55 +00:00
NAKAMURA Takumi 88e1b351d4 llvm/utils/TableGen/CMakeLists.txt: Update corresponding to r166685. 
llvm-svn: 166686
 2012-10-25 15:57:56 +00:00
Sebastian Pop 5c87daf2c8 add TableGen support to create relationship maps between instructions 
Relationship maps are represented as InstrMapping records which are parsed by
TableGen and the information is used to construct mapping tables to represent
appropriate relations between instructions. These tables are emitted into
XXXGenInstrInfo.inc file along with the functions to query them.

Patch by Jyotsna Verma <jverma@codeaurora.org>.

llvm-svn: 166685
 2012-10-25 15:54:06 +00:00
Joerg Sonnenberger 7090937330 Don't use stack unwinding to provide the location information for 
SetTheory, but pass down the location explicitly.

llvm-svn: 166629
 2012-10-24 22:03:59 +00:00
Lang Hames cdd40bdc05 Allow the commuted form of tied-operand constraints in tablegen ("$dst = $src", 
rather than "$src = $dst").

llvm-svn: 166382
 2012-10-20 22:44:13 +00:00
Daniel Dunbar a3d9cabf8f lit: Rename the valgrind leaks feature to match what is currently used 
(vg_leak).

llvm-svn: 166306
 2012-10-19 20:29:30 +00:00
Daniel Dunbar a3514551a1 lit: Remove support for XTARGET. 
- The XTARGET feature (inherited from old DG tests) was just confusing (and
   barely ever used). The same effect can now be achieved with a combination of
   the more useful REQUIRES and XFAIL.

llvm-svn: 166305
 2012-10-19 20:29:27 +00:00
Daniel Dunbar 519a349c8a lit: Add 'valgrind' and 'valgrind-leaks' features when valgrind is used. 
- These can be used with the XFAIL options.

llvm-svn: 166303
 2012-10-19 20:12:00 +00:00
Daniel Dunbar 315bcbd145 lit: Propagate TERM variable in environment, some tools can do really obscure 
odd things if this is missing.

llvm-svn: 166289
 2012-10-19 17:23:34 +00:00
Daniel Dunbar f1706edf5d lit: Allow XFAIL: lines to also refer to "features". 
llvm-svn: 166224
 2012-10-18 20:43:04 +00:00
Bill Wendling fbd38fe2e3 Add an enum for the return and function indexes into the AttrListPtr object. This gets rid of some magic numbers. 
llvm-svn: 165924
 2012-10-15 07:29:08 +00:00
Bill Wendling d079a446d7 Attributes Rewrite 
Convert the internal representation of the Attributes class into a pointer to an
opaque object that's uniqued by and stored in the LLVMContext object. The
Attributes class then becomes a thin wrapper around this opaque
object. Eventually, the internal representation will be expanded to include
attributes that represent code generation options, etc.

llvm-svn: 165917
 2012-10-15 04:46:55 +00:00
Chad Rosier 2f480a8a50 [ms-inline asm] Use the new API introduced in r165830 in lieu of the 
MapAndConstraints vector.  Also remove the unused Kind argument.

llvm-svn: 165833
 2012-10-12 22:53:36 +00:00
Richard Trieu 2448969d7f Change (!list.size() == 0) to (!list.empty()). No functional change. 
llvm-svn: 165812
 2012-10-12 17:57:35 +00:00
Sean Silva 506a1c5a58 Remove unnecessary classof()'s 
isa<> et al. automatically infer when the cast is an upcast (including a
self-cast), so these are no longer necessary.

llvm-svn: 165767
 2012-10-11 23:30:49 +00:00
Chad Rosier 2b189a5b40 Remove extra semicolons. 
llvm-svn: 165757
 2012-10-11 22:25:56 +00:00
Sean Silva bd7d243107 tblgen: Compile TableGen without RTTI. 
TableGen no longer needs RTTI!

llvm-svn: 165651
 2012-10-10 20:27:18 +00:00
Sean Silva c0a9e39d0a tblgen: Move mini Type hierarchy to LLVM-style RTTI. 
llvm-svn: 165648
 2012-10-10 20:24:49 +00:00
Sean Silva 88eb8dd4ed tblgen: Use semantically correct RTTI functions. 
Also, some minor cleanup.

llvm-svn: 165647
 2012-10-10 20:24:47 +00:00
Sean Silva fb509ed156 tblgen: Mechanically move dynamic_cast<> to dyn_cast<>. 
Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>.
That will happen in a future patch.

There are also two dyn_cast_or_null<>'s slipped in instead of
dyn_cast<>'s, since they were causing crashes with just dyn_cast<>.

llvm-svn: 165646
 2012-10-10 20:24:43 +00:00
Bill Wendling ed42e799dc Pass into the AttributeWithIndex::get method an ArrayRef of attribute 
enums. These are then created via the correct Attributes creation method.

llvm-svn: 165607
 2012-10-10 06:13:42 +00:00
Andrew Trick d0b9c44583 TableGen subtarget emitter cleanup. 
Consistently evaluate Aliases and Sequences recursively.

llvm-svn: 165604
 2012-10-10 05:43:13 +00:00
Andrew Trick 8e9c1d8998 misched: Generate IsBuffered flag for machine resources. 
llvm-svn: 165602
 2012-10-10 05:43:04 +00:00
Micah Villmow 9cfc13d46c Move TargetData to DataLayout. 
llvm-svn: 165403
 2012-10-08 16:39:34 +00:00
Chad Rosier 8f06e7dea4 [ms-inline asm] Add a few typedefs to simplify future changes. 
llvm-svn: 165324
 2012-10-05 18:41:14 +00:00
Sean Silva 98c61711c6 tblgen: Replace uses of dynamic_cast<XXXRecTy> with dyn_cast<>. 
This is a mechanical change of dynamic_cast<> to dyn_cast<>. A number of
these uses are actually more like isa<> or cast<>, and will be changed
to the semanticaly appropriate one in a future patch.

llvm-svn: 165291
 2012-10-05 03:31:58 +00:00
Andrew Trick 9e1deb69b9 Added instregex support to TableGen subtarget emitter. 
This allows the processor-specific machine model to override selected
base opcodes without any fanciness.
e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>.

llvm-svn: 165180
 2012-10-03 23:06:32 +00:00
Andrew Trick da984b1aa9 TableGen subtarget emitter, nearly first class support for SchedAlias. 
A processor can now arbitrarily alias one SchedWrite onto
another. Only the SchedAlias definition need be within the processor
model. The aliased SchedWrite may be a SchedVariant, WriteSequence, or
transitively refer to another alias.

llvm-svn: 165179
 2012-10-03 23:06:28 +00:00
Andrew Trick 7aba6beae5 Cleanup TableGen subtarget emitter. 
llvm-svn: 165178
 2012-10-03 23:06:25 +00:00
Chad Rosier bd5974e7ae [ms-inline asm] Default to the 'm' constraint. This matches the behavior of the 
MSVC compiler.

llvm-svn: 165174
 2012-10-03 22:18:38 +00:00
Sean Silva a3bf561384 tblgen: Migrate llvm-tblgen to new TableGenMain API. 
llvm-svn: 165166
 2012-10-03 21:29:19 +00:00
Chad Rosier 380a74a339 Fix 80-column violations. Cleanup whitespace in generated code. 
llvm-svn: 164983
 2012-10-02 00:25:57 +00:00
Chad Rosier f4e35dc672 [ms-inline asm] Add the convertToMapAndConstraints() function that is used to 
map constraints and MCInst operands to inline asm operands.  This replaces the
getMCInstOperandNum() function.

The logic to determine the constraints are not in place, so we still default to
a register constraint (i.e., "r"). Also, we no longer build the MCInst but
rather return just the opcode to get the MCInstrDesc.

llvm-svn: 164979
 2012-10-01 23:45:51 +00:00
Sylvestre Ledru 91ce36c986 Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 
llvm-svn: 164768
 2012-09-27 10:14:43 +00:00
Sylvestre Ledru 721cffd53a Fix a typo 'iff' => 'if' 
llvm-svn: 164767
 2012-09-27 09:59:43 +00:00
Chad Rosier c4734c8950 Rather then have a wrapper function, have tblgen instantiate the implementation. 
Also remove an unused argument.

llvm-svn: 164567
 2012-09-24 22:57:55 +00:00
Chad Rosier 3cb355d11f Rather then have a wrapper function, have tblgen instantiate the implementation. 
llvm-svn: 164548
 2012-09-24 19:32:29 +00:00
Andrew Trick 9257b8f8bb Machine Model (-schedmodel only). Added SchedAliases. 
Allow subtargets to tie SchedReadWrite types to processor specific
sequences or variants.

llvm-svn: 164451
 2012-09-22 02:24:21 +00:00
Chad Rosier 17ede627f0 [ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser. 
llvm-svn: 164420
 2012-09-21 22:21:26 +00:00
Chad Rosier 2ac9fd0a82 Whitespace. 
llvm-svn: 164406
 2012-09-21 19:25:59 +00:00
Dmitri Gribenko 6e9fcd6215 Clarify comment. 
llvm-svn: 164371
 2012-09-21 15:26:34 +00:00
Micah Villmow 75e29c4b78 Add in new data types that are used by AMDIL/ANL among others. 
llvm-svn: 164261
 2012-09-19 22:47:07 +00:00
Owen Anderson dee6583dfd Soften the pattern-can-never-match error in TableGen into a warning. This pattern can be very useful in cases where you want to define a multiclass that covers both commutative and non-commutative operators (say, add and sub). 
llvm-svn: 164256
 2012-09-19 22:15:06 +00:00
Craig Topper 3f23c1a8b9 Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. 
llvm-svn: 164204
 2012-09-19 06:37:45 +00:00
Andrew Trick cfe222c2a9 SchedMachineModel: compress the CPU's WriteLatencyTable. 
llvm-svn: 164199
 2012-09-19 04:43:19 +00:00
Sean Silva 835139bfe4 Iterate deterministicaly over ClassInfo*'s 
Fixes an observed instance of nondeterministic TableGen output.

Review by Jakob.

llvm-svn: 164191
 2012-09-19 01:47:03 +00:00
Sean Silva c8f5657f91 Iterate deterministically over register classes 
Fixes an observed instance of nondeterministic TableGen output.

Review by Jakob.

llvm-svn: 164190
 2012-09-19 01:47:01 +00:00
Sean Silva a4e2c5fc86 Refactor Record* by-ID comparator to Record.h 
This is a generally useful utility; there's no reason to have it hidden
in CodeGenDAGPatterns.cpp.

Also, rename it to fit the other comparators in Record.h

Review by Jakob.

llvm-svn: 164189
 2012-09-19 01:47:00 +00:00
Benjamin Kramer ef878a832b FileCheck: Fix off-by-one bug that made CHECK-NOT: ignore the next character after the colon. 
llvm-svn: 164165
 2012-09-18 20:51:39 +00:00
Craig Topper 7ecfa6d960 Make custom operand parsing mnemonic indices use the same mnemonic table as the match table. Reorder fields in OperandMatchEntry to provide the least amount of padding for in tree targets. 
llvm-svn: 164109
 2012-09-18 07:02:21 +00:00
Craig Topper e2cfeb30a1 Use variable type for index into mnemonic table. Shrinks size of index field on in tree targets. Saving static data space. 
llvm-svn: 164108
 2012-09-18 06:10:45 +00:00
Andrew Trick ba7b921fcb Replaced ReInitMCSubtargetInfo with InitMCProcessor. 
Now where we used to call ReInitMCSubtargetInfo, we actually recompute
the same information as InitMCSubtargetInfo instead of only setting
the feature bits.

llvm-svn: 164105
 2012-09-18 05:33:15 +00:00
Andrew Trick ea28dbdf93 comment typo 
llvm-svn: 164097
 2012-09-18 04:03:30 +00:00
Andrew Trick a88f1bddc6 TableGen subtarget emitter. Use getSchedClassIdx. 
llvm-svn: 164096
 2012-09-18 03:55:55 +00:00
Andrew Trick c6c88151bb TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants. 
llvm-svn: 164095
 2012-09-18 03:41:43 +00:00
Andrew Trick 1188e439b2 TableGen subtarget emitter. Remove unnecessary header dependence. 
llvm-svn: 164094
 2012-09-18 03:32:57 +00:00
Andrew Trick ab722bdd50 TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model. 
llvm-svn: 164092
 2012-09-18 03:18:56 +00:00
Craig Topper 9150610db7 Mark asm matcher conversion table as const. 
llvm-svn: 164088
 2012-09-18 01:41:49 +00:00
Craig Topper aae8fb801e Fix typo in comment. No functional change. 
llvm-svn: 164086
 2012-09-18 01:13:36 +00:00
Andrew Trick 8038ceb731 Backout the wrong subtarget emitter fix 
llvm-svn: 164078
 2012-09-17 23:14:15 +00:00
Andrew Trick 3e5546add7 Fix release build after reverting 
llvm-svn: 164075
 2012-09-17 23:05:04 +00:00
Andrew Trick 8e7f202e32 Revert r164061-r164067. Most of the new subtarget emitter. 
I have to work out the Target/CodeGen header dependencies
before putting this back.

llvm-svn: 164072
 2012-09-17 23:00:42 +00:00
Andrew Trick 692b87c18f InitMCProcessor 
llvm-svn: 164066
 2012-09-17 22:19:12 +00:00
Andrew Trick c00f4314ce comment typo 
llvm-svn: 164064
 2012-09-17 22:19:04 +00:00
Andrew Trick 36e07eb83e TableGen subtarget emitter. Use getSchedClassIdx. 
llvm-svn: 164063
 2012-09-17 22:19:01 +00:00
Andrew Trick 7a1faa2c8a TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants. 
llvm-svn: 164062
 2012-09-17 22:18:58 +00:00
Andrew Trick 0923f8183b TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model. 
llvm-svn: 164061
 2012-09-17 22:18:55 +00:00
Andrew Trick a72fca6bec TableGen subtarget emitter. Format and emit data tables for the new machine model. 
llvm-svn: 164060
 2012-09-17 22:18:50 +00:00
Andrew Trick 9ef0882b72 TableGen subtarget emitter. Generate data tables for the new machine model. 
Map the CodeGenSchedule object model onto data tables. The structure
of the data tables is defined in MC, so for convenience we include
MCSchedule.h. The alternative is maintaining a redundant copy of the
table structure definitions. Mapping the object model onto data tables
is sufficiently complicated that it should not be interleaved with
emitting source code. This avoids major problem with the backend for
itinerary generation.

llvm-svn: 164059
 2012-09-17 22:18:48 +00:00
Andrew Trick 23f3c65e4b TableGen subtarget emitter. Emit processor resources for the new machine model. 
llvm-svn: 164058
 2012-09-17 22:18:45 +00:00
Andrew Trick 8fa00f5069 TableGen subtarget parser: Add getProcResourcesIdx(). 
llvm-svn: 164057
 2012-09-17 22:18:43 +00:00
Jim Grosbach 4c36349de9 TableGen: Add initializer. 
Keep GCC's warnings happy. It can't reason out that the state machine won't
ever hit the potentially uninitialized use in OPC_FilterValue.

llvm-svn: 164041
 2012-09-17 18:00:53 +00:00
Axel Naumann 4a1270691e Fix a few vars that can end up being used without initialization. 
The cases where no initialization happens should still be checked for logic flaws.

llvm-svn: 164032
 2012-09-17 14:20:57 +00:00
Michael Liao ebeedd0ed6 Fix typo 
llvm-svn: 164012
 2012-09-17 04:43:39 +00:00
Craig Topper a583df034a Add 'virtual' keywoards to output file for overridden functions. 
llvm-svn: 164002
 2012-09-16 18:25:36 +00:00
Craig Topper 8dcaf4998c Add 'virtual' keywoards to output file for overridden functions. 
llvm-svn: 163999
 2012-09-16 16:35:22 +00:00
Dmitri Gribenko 8d30240939 Fix Doxygen issues: wrap code examples in \code and use \p to refer to 
parameters.

llvm-svn: 163984
 2012-09-15 20:22:05 +00:00
Craig Topper f8f0a23ce7 Revert r163878 as it breaks on targets with alternate register names. Such targets do not exist in the main tree so this was not noticed. 
llvm-svn: 163959
 2012-09-15 01:22:42 +00:00
Andrew Trick 1e46d48814 TableGen subtarget parser. Handle new machine model. 
Collect processor resources from the subtarget defs.

llvm-svn: 163953
 2012-09-15 00:20:02 +00:00
Andrew Trick 33401e8469 TableGen subtarget parser. Handle new machine model. 
Infer SchedClasses from variants defined by the target or subtarget.

llvm-svn: 163952
 2012-09-15 00:19:59 +00:00
Andrew Trick 766864963b TableGen subtarget parser. Handle new machine model. 
Collect SchedClasses and SchedRW types from the subtarget defs.

llvm-svn: 163951
 2012-09-15 00:19:57 +00:00
Craig Topper 06cec4ceac Allow the second opcode info table to be 8, 16, or 32-bits as needed to represent additional fragments. This recovers some space on ATT X86 syntax and PowerPC which only need 40-bits instead of 48-bits. This also increases ARM to 64-bits to fully encode all of its operands. 
llvm-svn: 163880
 2012-09-14 08:33:11 +00:00
Craig Topper 805e39beab Reduce size of register name index tables by using uint16_t for all in tree targets. If more than 16-bits are needed for any out of tree targets, code will detect and use uint32_t instead. 
llvm-svn: 163878
 2012-09-14 06:37:49 +00:00
Manman Ren 4d9ae56a45 AsmWriterEmitter: OpInfo2 should be unsigned 16-bit. 
Fix an issue in r163814.

llvm-svn: 163837
 2012-09-13 20:47:48 +00:00
Manman Ren 68cf9fc45d AsmWriterEmitter: increase the number of bits for OpcodeInfo from 32-bit to 
48-bit if necessary, in order to reduce the generated code size.

We have 900 cases not covered by OpcodeInfo in ATT AsmWriter and more in Intel
AsmWriter and ARM AsmWriter.

This patch reduced the clang Release build size by 50k, running on a Mac Pro.

llvm-svn: 163814
 2012-09-13 17:43:46 +00:00
Dmitri Gribenko 2bc1d483fe Fix Doxygen issues: 
* wrap code blocks in \code ... \endcode;
* refer to parameter names in paragraphs correctly (\arg is not what most
  people want -- it starts a new paragraph).

llvm-svn: 163790
 2012-09-13 12:34:29 +00:00
Craig Topper 963305b450 Add a new compression type to ModRM table that detects when the memory modRM byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. 
llvm-svn: 163774
 2012-09-13 05:45:42 +00:00
Jim Grosbach f6cb1ee75a TableGen: Convert an assert() to a proper diagnostic. 
llvm-svn: 163726
 2012-09-12 17:40:25 +00:00
Dmitri Gribenko 881929c1b6 Fix a couple of Doxygen comment issues pointed out by -Wdocumentation. 
llvm-svn: 163721
 2012-09-12 16:59:47 +00:00
Owen Anderson 16ba4b2d83 Improve tblgen code cleanliness: create an unknown_class, from which the unknown def inherits. Make tblgen check for that class, rather than checking for the def itself. 
llvm-svn: 163664
 2012-09-11 23:47:08 +00:00
Owen Anderson ccd682c695 Compute a map from register names to registers, rather than scanning the list of registers every time we want to look up a register by name. 
llvm-svn: 163659
 2012-09-11 23:32:17 +00:00
Jakob Stoklund Olesen d346d4871a Add TRI::getSubRegIndexLaneMask(). 
Sub-register lane masks are bitmasks that can be used to determine if
two sub-registers of a virtual register will overlap. For example, ARM's
ssub0 and ssub1 sub-register indices don't overlap each other, but both
overlap dsub0 and qsub0.

The lane masks will be accurate on most targets, but on targets that use
sub-register indexes in an irregular way, the masks may conservatively
report that two sub-register indices overlap when the eventually
allocated physregs don't.

Irregular register banks also mean that the bits in a lane mask can't be
mapped onto register units, but the concept is similar.

llvm-svn: 163630
 2012-09-11 16:34:08 +00:00
Jakob Stoklund Olesen dd40fda52d Clean the sub-reg index composition maps at emission. 
Preserve the Composites map in the CodeGenSubRegIndex class so it can be
used to determine which sub-register indices can actually be composed.

llvm-svn: 163629
 2012-09-11 16:34:05 +00:00
Jakob Stoklund Olesen 21e2f1c6e5 Add MCRI::getNumSubRegIndices() and start checking SubRegIndex ranges. 
Apparently, NumSubRegIndices was completely unused before. Adjust it by
one to include the null subreg index, just like getNumRegs() includes
the null register.

llvm-svn: 163628
 2012-09-11 16:34:02 +00:00
Craig Topper 8702c5b7c0 Change unsigned to a uint16_t in static disassembler tables to reduce the table size. 
llvm-svn: 163594
 2012-09-11 04:19:21 +00:00
Evgeniy Stepanov c9cdb96188 GTest on Android needs a custom tmpdir path. 
llvm-svn: 163501
 2012-09-10 10:32:29 +00:00
NAKAMURA Takumi 78ddd58743 lit: Util.which(): Use os.path.isfile() instead of os.path.exists(), or it hits to the directory. 
For example, which('loop-convert') returns 'loop-convert' when the directory 'loop-convert' exists.

llvm-svn: 163469
 2012-09-08 12:07:24 +00:00
Ted Kremenek d94669675b Revert "Add -exact-match option to FileCheck to allow clients to do exact matches without using regular expressions." 
Turns out I did not need it after all.  If we find a use for it in the future, we
can resurrect it.

llvm-svn: 163457
 2012-09-08 04:32:13 +00:00
Anshuman Dasgupta f16a443da3 Refactored DFA generator. Merged transition class into state class. 
Patch by Ivan Llopard!

llvm-svn: 163424
 2012-09-07 21:35:43 +00:00
Ted Kremenek 1cb637cc37 Add -exact-match option to FileCheck to allow clients to do exact matches without using regular expressions. 
llvm-svn: 163371
 2012-09-07 06:47:16 +00:00