Commit Graph

164816 Commits

Author SHA1 Message Date
Florian Hahn 8a17f1f43e Revert r333740: IPSCCP] Use PredicateInfo to propagate facts from cmp.
This is breaking the clang-with-thin-lto-ubuntu bot.

llvm-svn: 333745
2018-06-01 12:58:43 +00:00
Sander de Smalen f95ea047e5 [AArch64][SVE] Asm: Support for FDUP_ZI (copy fp immediate) instruction.
Unpredicated copy of floating-point immediate value into SVE vector,
along with MOV-aliases.

Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D47482

llvm-svn: 333744
2018-06-01 12:54:46 +00:00
Simon Dardis 351aa594f6 [mips] Guard more aliases correctly.
Also, duplicate an alias for microMIPS.

llvm-svn: 333741
2018-06-01 10:57:13 +00:00
Florian Hahn f4df554f32 Recommit r333268: [IPSCCP] Use PredicateInfo to propagate facts from cmp instructions.
This patch updates IPSCCP to use PredicateInfo to propagate
facts to true branches predicated by EQ and to false branches
predicated by NE.

As a follow up, we should be able to extend it to also propagate additional
facts about nonnull.

Reviewers: davide, mssimpso, dberlin, efriedma

Reviewed By: davide, dberlin

Differential Revision: https://reviews.llvm.org/D45330

llvm-svn: 333740
2018-06-01 10:48:54 +00:00
Simon Dardis 54217598b6 [mips] Guard 'nop' properly and add mips16's nop instruction
Reviewers: smaksimovic, atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D47583

llvm-svn: 333739
2018-06-01 10:46:00 +00:00
Pavel Labath d6ca063907 DWARFAcceleratorTable: Add an iterator-based api for accessing names in the index
Summary:
Back when we were introducing the DWARF v5 name index, there was a
short discussion whether we shouldn't have a nicer api for iterating
over the index. At that time, I did not find it necessary since the
iteration over names was done only from within the index itself (and I
figured the internal implementation can deal with a slightly rough
interface).

However, now I ran into a use for this kind of API in LLDB (for finding
all names matching a regular expression), so it looked like a nice
opportunity to introduce one. To make the API more useful, I've made the
NameTableEntry class a bit smarter: it now stores the string section
reference (so it can return its name) and its position in the name index
(mainly useful for dumping/logging).

I also convert the internal users to use the new API, which also gives
test coverage for the added code.

Reviewers: JDevlieghere, aprantl, dblaikie

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D47590

llvm-svn: 333738
2018-06-01 10:33:11 +00:00
Simon Dardis ee67dcb837 [mips] Select the correct instruction for computing frameindexes
Reviewers: smaksimovic, atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D47582

llvm-svn: 333736
2018-06-01 10:07:10 +00:00
Gabor Buella 27c96d3d20 NFC Avoid a warning in WasmEHPrepare.cpp
```
../lib/CodeGen/WasmEHPrepare.cpp:166:30: warning: extra ‘;’ [-Wpedantic]
                 false, false);
                              ^
```

llvm-svn: 333732
2018-06-01 07:47:46 +00:00
Sander de Smalen 97ca6b9e09 [AArch64][SVE] Asm: Support for DUPM (masked immediate) instruction.
Unpredicated copy of repeating immediate pattern to SVE vector, along
with MOV-aliases.

Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D47328

llvm-svn: 333731
2018-06-01 07:25:46 +00:00
Matt Arsenault 72a9f52c87 AMDGPU: Switch some half using-tests to use amdhsa
The default clover ABI weirdly promotes half to float,
which should probably be fixed.

llvm-svn: 333730
2018-06-01 07:06:03 +00:00
Craig Topper c3cf55b935 [X86][Disassembler] Make it an error to set EVEX.R' to 0 when modrm.reg encodes a GPR.
This is different than the behavior of EVEX.X extending modrm.rm to 5 bits.

llvm-svn: 333728
2018-06-01 06:11:29 +00:00
Craig Topper 0838c4d6bc [X86][Disassembler] Ignore EVEX.X extension of modrm.rm to 5-bits when modrm.rm encodes a k-register.
llvm-svn: 333727
2018-06-01 05:36:08 +00:00
Daniel Cederman d72b9fd141 Implemented sane default for llvm-objdump's relocation Value format
Summary:
"Unknown" for platforms that were not manually added into the switch
did not make sense at all. Now it prints Target + addend for all
elf-machines that were not explicitly mentioned.

Addresses PR21059 and PR25124.

Original author: fedor.sergeev

Reviewers: jyknight, espindola, fedor.sergeev

Reviewed By: jyknight

Subscribers: eraman, dcederman, jfb, dschuff, aheejin, llvm-commits

Differential Revision: https://reviews.llvm.org/D36464

llvm-svn: 333726
2018-06-01 05:31:58 +00:00
Craig Topper 74a61b02e0 [X86][Disassembler] Clamp index to 4-bits when decoding GPR registers.
A 5-bit value can occur when EVEX.X is 0 due to it being used to extend modrm.rm to encode XMM16-31. But if modrm.rm instead encodes a GPR, the Intel documentation says EVEX.X should be ignored so just mask it to 4 bits once we know its a GPR.

llvm-svn: 333725
2018-06-01 05:12:44 +00:00
Craig Topper 1a00b0ac27 [X86] Add a test case showing a bad disassembling of an EVEX instruction with EVEX.X=0 and a GPR encoded in modrm.rm.
EVEX.X is used to extended modrm.rm when the instruction encodes a XMM/YMM/ZMM register. But we aren't properly ignoring it when it encodes a GPR and we end up printing whatever registers exist in X86 register enum after the GPRs.

llvm-svn: 333724
2018-06-01 05:12:43 +00:00
Craig Topper 5b1dd01e57 [X86][Disassembler] Make sure EVEX.X is not used to extend base registers of memory operations.
This was an accidental side effect of EVEX.X being used to encode XMM16-XMM31 using modrm.rm with modrm.mod==0x3.

I think there are still more bugs related to this.

llvm-svn: 333722
2018-06-01 04:29:34 +00:00
Craig Topper c6b2c2bb70 [X86][Disassembler] Use a local variable instead of using a field in the instruction object. NFC
llvm-svn: 333721
2018-06-01 04:29:30 +00:00
Tom Stellard e43778895c AMDGPU/R600: Move intrinsics to IntrinsicsAMDGPU.td
Reviewers: arsenm, nhaehnle, jvesely

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D47487

llvm-svn: 333720
2018-06-01 02:19:46 +00:00
Craig Topper dc5ba1e495 [X86] Make sure the check for VEX.vvvv being all ones on instructions that don't use it doesn't ignore a bit in 32-bit mode.
llvm-svn: 333717
2018-06-01 01:23:52 +00:00
Craig Topper 0179c6d0e5 [X86][Disassembler] Suppress reading of EVEX.V' and EVEX.R' in 32-bit mode.
llvm-svn: 333714
2018-06-01 00:10:36 +00:00
Craig Topper b9c2e8cc01 [X86] Add test cases showing the disassembler producing an xmm16-xmm31 register in 32-bit mode.
We aren't properly suppressing the reading of VEX.R' and VEX.V' in 32-bit mode.

llvm-svn: 333713
2018-06-01 00:10:32 +00:00
Heejin Ahn d69acf3b4c Change ambiguous uses of term 'funclet' to 'EH scopes'. NFC.
Summary:
`getEHScopeMembership()` function is used not only for funclet-based
EHs; they apply to all EH schemes that use the scoped IR
(catchpad/cleanuppad/...). D47005 (rL333045) changed some of the uses of
the term 'funclet' to 'EH scopes' in case they apply to all scoped EH,
and this fixes more of them. For `FuncletLayout` pass, I left it as is
because the pass is only used for funclet-based EH.

Reviewers: majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D47611

llvm-svn: 333711
2018-06-01 00:03:21 +00:00
Dan Gohman 91ab25bbe3 [WebAssembly] Update to the new names for the memory intrinsics.
The WebAssembly committee has decided on the names `memory.size` and
`memory.grow` for the memory intrinsics, so update the LLVM intrinsics to
follow those names, keeping both sets of old names in place for
compatibility.

llvm-svn: 333708
2018-05-31 22:35:25 +00:00
Sanjay Patel affe450db7 [LoopVectorize, x86] add tests to show missing SVML transforms; NFC
llvm-svn: 333707
2018-05-31 22:31:02 +00:00
Dan Gohman b17de645ea [WebAssembly] Fix the signatures for the __mulo* libcalls.
The __mulo* libcalls have an extra i32* to return the overflow value.

Fixes PR37401.

llvm-svn: 333706
2018-05-31 22:27:24 +00:00
Heejin Ahn 5ef4d5f9c1 [WebAssembly] Support instruction selection for catching exceptions
Summary:
This lowers exception catching-related instructions:
1. Lowers `wasm.catch` intrinsic to `catch` instruction
2. Removes `catchpad` and `cleanuppad` instructions; they are not
necessary after isel phase. (`MachineBasicBlock::isEHFuncletEntry()` or
`MachineBasicBlock::isEHPad()` can be used instead.)
3. Lowers `catchret` and `cleanupret` instructions to pseudo `catchret`
and `cleanupret` instructions in isel, which will be replaced with other
instructions in `WebAssemblyExceptionPrepare` pass.
4. Adds 'WebAssemblyExceptionPrepare` pass, which is for running various
transformation for EH. Currently this pass only replaces `catchret` and
`cleanupret` instructions into appropriate wasm instructions to make
this patch successfully run until the end.

Currently this does not handle lowering of intrinsics related to LSDA
info generation (`wasm.landingpad.index` and `wasm.lsda`), because they
cannot be tested without implementing `EHStreamer`'s wasm-specific
handlers. They are marked as TODO, which is needed to make isel pass.
Also this does not generate `try` and `end_try` markers yet, which will
be handled in later patches.

This patch is based on the first wasm EH proposal.
(https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md)

Reviewers: dschuff, majnemer

Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D44090

llvm-svn: 333705
2018-05-31 22:25:54 +00:00
Craig Topper 9a6c0bdcbd [LoopIdiomRecognize] Only convert loops to ctlz if we can prove that the input is non-negative.
Summary:
Loop idiom recognize tries to convert loops like

```
int foo(int x) {
  int cnt = 0;
  while (x) {
    x >>= 1;
    ++cnt;
  }
  return cnt;
}
```

into calls to ctlz, but if x is initially negative this loop should be infinite.

It happens that the cases that motivated this change have an absolute value of x before the loop. So this patch restricts the transform to cases where we know x is positive. Note: We are relying on the absolute value of INT_MIN to be undefined so we can assume that the result is always positive.

Fixes PR37479

Reviewers: spatel, hfinkel, efriedma, javed.absar

Reviewed By: efriedma

Subscribers: dmgreen, llvm-commits

Differential Revision: https://reviews.llvm.org/D47348

llvm-svn: 333702
2018-05-31 22:16:55 +00:00
Heejin Ahn 99d60e0dab [WebAssembly] Add Wasm exception handling prepare pass
Summary:
This adds a pass that transforms a program to be prepared for Wasm
exception handling. This is using Windows EH instructions and based on
the previous Wasm EH proposal.
(https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md)

Reviewers: dschuff, majnemer

Subscribers: jfb, mgorny, sbc100, jgravelle-google, JDevlieghere, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D43746

llvm-svn: 333696
2018-05-31 22:02:34 +00:00
Sanjay Patel 2ae1ab30e3 [LoopVectorize, x86] regenerate checks; NFC
I removed the 'fast' flag from the calls because that's not required.

llvm-svn: 333695
2018-05-31 21:30:36 +00:00
Alexander Shaposhnikov ecc84834b7 [llvm-strip] Add -o option to llvm-strip
This diff implements the option -o 
for specifying a file to write the output to.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D47505

llvm-svn: 333693
2018-05-31 20:42:13 +00:00
Andrea Di Biagio 4037011404 [llvm-mca] Fixed a problem caused by an invalid use of a processor resource mask in the Scheduler.
The lambda functions used by method ResourceManager::mustIssueImmediately() was
incorrectly truncating masks of buffered processor resources to 32-bit quantities.
The invalid mask values were then used to access a map of processor
resource descriptors.

Fixes PR37643.

llvm-svn: 333692
2018-05-31 20:27:46 +00:00
Stanislav Mekhanoshin 739174c4be [AMDGPU] Construct memory clauses before RA
Memory clauses are formed into bundles in presence of xnack.
Their source operands are marked as early-clobber.

This allows to allocate distinct source and destination registers
within a clause and prevent breaking the clause with s_nop in the
hazard recognizer.

Clauses are undone before post-RA scheduler to allow some rescheduling,
which will not break the clause since artificial edges are created in
the dag to keep memory operations together. Yet this allows a better
ILP in some cases.

Differential Revision: https://reviews.llvm.org/D47511

llvm-svn: 333691
2018-05-31 20:13:51 +00:00
Sanjay Patel 26368cd5d9 [InstCombine] narrow select to match condition operands' size
This is the planned enhancement to D47163 / rL333611.
We want to match cmp/select sizes because that will be recognized
as min/max more easily and lead to better codegen (especially for
vector types).

As mentioned in D47163, this improves some of the tests that would
also be folded by D46380, so we may want to adjust that patch to
match the new patterns where the extend op occurs after the select.

llvm-svn: 333689
2018-05-31 19:55:27 +00:00
Stanislav Mekhanoshin 7137f609f4 [AMDGPU] Fixed incorrect -mcpu=gfx800 in xnor.ll test. NFC.
llvm-svn: 333687
2018-05-31 19:39:54 +00:00
Aditya Nandakumar 2980b01995 [GISel]: Pattern matchers for GFSUB, GFNEG
https://reviews.llvm.org/D47547

Add matching templates for G_FSUB, and G_FNEG.

Reviewed by: aemerson.

llvm-svn: 333685
2018-05-31 19:30:01 +00:00
Lang Hames 6fe6616c47 [ORC] Add a getRequestedSymbols method to MaterializationResponsibility.
This method returns the set of symbols in the target VSO that have queries
waiting on them. This can be used to make decisions about which symbols to
delegate to another MaterializationUnit (typically this will involve
delegating all symbols that have *not* been requested to another
MaterializationUnit so that materialization of those symbols can be
deferred until they are requested).

llvm-svn: 333684
2018-05-31 19:29:03 +00:00
Lang Hames d3a76f5bbc [ORC] Rename IRMaterializationUnit's Discardable member to SymbolToDefinition,
and make it protected rather than private.

The new name reflects the actual information in the map, and this information
can be useful to derived classes (for example, to quickly look up the IR
definition of a requested symbol).

llvm-svn: 333683
2018-05-31 19:29:01 +00:00
Sanjay Patel dfbe6b49f0 [InstCombine] regenerate checks; NFC
llvm-svn: 333682
2018-05-31 19:25:02 +00:00
Peter Collingbourne 3aa30e8062 IRGen: Write .dwo files when -split-dwarf-file is used together with -fthinlto-index.
Differential Revision: https://reviews.llvm.org/D47597

llvm-svn: 333677
2018-05-31 18:25:59 +00:00
Sriraman Tallam d10c4e07f5 Relax GOTPCREL relocations for tail jmp instructions.
Differential Revision: https://reviews.llvm.org/D47563

llvm-svn: 333676
2018-05-31 18:12:33 +00:00
Craig Topper c9a4c6208b [JumpThreading] Fix some strange formatting of code inside LLVM_DEBUG. NFC
I don't know if clang-format got confused here or what.

llvm-svn: 333675
2018-05-31 18:08:11 +00:00
Artem Dergachev 3260b00d48 [ADT] Annotate immutable list/set/map update methods with LLVM_NODISCARD.
Because immutable data structures are, well, immutable, methods like "append",
"add", "set" create a copy of the list (set, map) instead of mutating the
existing map. If the updated object is discarded, it clearly indicates a bug.
Such bugs are introduced frequently, hence the warn_unused_result annotation.

Differential Revision: https://reviews.llvm.org/D47496

llvm-svn: 333672
2018-05-31 17:32:29 +00:00
Jonas Devlieghere 745918ff87 [ADT] Make escaping fn conform to coding guidelines
As noted by Adrian on llvm-commits, PrintHTMLEscaped and PrintEscaped in
StringExtras did not conform to the LLVM coding guidelines. This commit
rectifies that.

llvm-svn: 333669
2018-05-31 17:01:42 +00:00
David Bolvansky 5430b73755 [SimplifyLibcalls] [NFC] Cleanup, improvements
Summary:
* Use "find('%')" instead of loop to find '%' char (we already uses find('%') in optimizePrintFString..)
* Convert getParent() chains to getModule()/getFunction()

Reviewers: lebedev.ri, spatel

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D47397

llvm-svn: 333668
2018-05-31 16:39:27 +00:00
Francis Visoiu Mistrih 90aba024c5 [MC] Fallback on DWARF when generating compact unwind on AArch64
Instead of asserting when using the def_cfa directive with a register
different from fp, fallback on DWARF.

Easily triggered with:

.cfi_def_cfa x1, 32;

rdar://40249694

Differential Revision: https://reviews.llvm.org/D47593

llvm-svn: 333667
2018-05-31 16:33:26 +00:00
Roman Tereshin f34d7ecc15 [GlobalISel][Mips] LegalizerInfo verifier: Adding LegalizerInfo::verify(...) call for Mips
Reviewers: aemerson, qcolombet

Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D46339

llvm-svn: 333665
2018-05-31 16:16:49 +00:00
Roman Tereshin 76c29c68dc [GlobalISel][AMDGPU] LegalizerInfo verifier: Adding LegalizerInfo::verify(...) call for AMDGPU
Reviewers: aemerson, qcolombet

Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D46339

llvm-svn: 333664
2018-05-31 16:16:48 +00:00
Roman Tereshin 667c7581ed [GlobalISel][ARM] LegalizerInfo verifier: Adding LegalizerInfo::verify(...) call and fixing bugs exposed
Reviewers: aemerson, qcolombet

Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D46339

llvm-svn: 333663
2018-05-31 16:16:48 +00:00
Roman Tereshin cc1a16fdf9 [GlobalISel][X86] LegalizerInfo verifier: Adding LegalizerInfo::verify(...) call and fixing bugs exposed
Reviewers: aemerson, qcolombet

Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D46339

llvm-svn: 333662
2018-05-31 16:16:47 +00:00
Simon Pilgrim ff0623cd29 [X86][SSE] Recognise splat rotations and expand back to shift ops.
Noticed while fixing PR37426, for splat rotations (rotation by an uniform value) its better to just expand back to shift ops than performing as a general non-uniform rotation.

llvm-svn: 333661
2018-05-31 15:47:17 +00:00