Commit Graph

3756 Commits

Author SHA1 Message Date
Hal Finkel 47646c0981 Add a 'Returned' intrinsic property corresponding to the 'returned' argument attribute
This will be used by the upcoming llvm.noalias intrinsic.

Differential Revision: http://reviews.llvm.org/D22201

llvm-svn: 275034
2016-07-11 01:28:42 +00:00
Justin Bogner acf564ca15 TableGen: Update style in CodeGenIntrinsics. NFC
Ran clang-format to remove the namespace indentation, and stopped
repeating names in doc comments since I was updating every line
anyway.

llvm-svn: 274919
2016-07-08 20:14:27 +00:00
Tim Northover be22e5ccbe TableGen: avoid string copy.
llvm-svn: 274584
2016-07-05 22:51:30 +00:00
Tim Northover e6ae6767d9 AArch64: TableGenerate system instruction operands.
The way the named arguments for various system instructions are handled at the
moment has a few problems:

  - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp
  - That weird Mapping class that I have no idea what I was on when I thought
    it was a good idea.
  - Searches are performed linearly through the entire list.
  - We print absolutely all registers in upper-case, even though some are
    canonically mixed case (SPSel for example).
  - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated
    to comments in our implementation, with a slightly opaque hex value
    indicating the canonical encoding LLVM will use.

This adds a new TableGen backend to produce efficiently searchable tables, and
switches AArch64 over to using that infrastructure.

llvm-svn: 274576
2016-07-05 21:23:04 +00:00
Tim Northover 88403d7a84 TableGen: promote "code" type from syntactic sugar.
It's being immediately converted to a "string", but being able to tell what
type the field was originally can be useful in backends.

llvm-svn: 274575
2016-07-05 21:22:55 +00:00
Davide Italiano 774e41cc47 [TableGen] Remove dead code. NFCI.
llvm-svn: 274515
2016-07-04 19:21:42 +00:00
Nicolai Haehnle 84c9f9919a Add writeonly IR attribute
Summary:
This complements the earlier addition of IntrWriteMem and IntrWriteArgMem
LLVM intrinsic properties, see D18291.

Also start using the attribute for memset, memcpy, and memmove intrinsics,
and remove their special-casing in BasicAliasAnalysis.

Reviewers: reames, joker.eph

Subscribers: joker.eph, llvm-commits

Differential Revision: http://reviews.llvm.org/D18714

llvm-svn: 274485
2016-07-04 08:01:29 +00:00
Simon Dardis 5f95c9af8d Revert "Revert "[misched] Extend scheduler to handle unsupported features""
This reverts commit r273565.

This was an over-eager revert.

llvm-svn: 273658
2016-06-24 08:43:27 +00:00
Ahmed Bougacha ef3358d579 [TableGen] Use StringRef::compare instead of != and <. NFC.
The previous code would always do 1 or 2 prefix compares;
explicitly only do one.

This speeds up debug -gen-asm-matcher by ~10% (e.g. X86: 40s -> 35s).

llvm-svn: 273583
2016-06-23 17:09:49 +00:00
Simon Dardis fcc7f6fad2 Revert "[misched] Extend scheduler to handle unsupported features"
This reverts commit r273551.

Patch contained a wrong check for isUnsupported.

llvm-svn: 273565
2016-06-23 14:54:47 +00:00
Simon Dardis 081e4bb14c [misched] Extend scheduler to handle unsupported features
Currently isComplete = 1 requires that every instruction must
be described, declared unsupported or marked as having no
scheduling information for a processor.

For some backends such as MIPS, this requirement entails
long regex lists of instructions that are unsupported.

This patch teaches Tablegen to skip over instructions that
are associated with unsupported feature when checking if the
scheduling model is complete.

Patch by: Daniel Sanders

Contributions by: Simon Dardis

Reviewers: MatzeB

Differential Reviewer: http://reviews.llvm.org/D20522

llvm-svn: 273551
2016-06-23 09:22:11 +00:00
Matthias Braun 6b1fd9aa63 TableGen/CodeGenSchedule: Move some getAllDerivedDefinitions() calls out of inner loops
This cuts the runtime of the two slowest tblgen invocations in aarch64
in half for me...

llvm-svn: 273235
2016-06-21 03:24:03 +00:00
Thomas Jablin 2263512a6c test commit: remove trailing whitespace
llvm-svn: 273197
2016-06-20 20:43:26 +00:00
Benjamin Kramer 4ca41fd09e Run clang-tidy's performance-unnecessary-copy-initialization over LLVM.
No functionality change intended.

llvm-svn: 272516
2016-06-12 17:30:47 +00:00
Richard Smith 2ad6d48b0c Search for llvm-symbolizer binary in the same directory as argv[0], before
looking for it along $PATH. This allows installs of LLVM tools outside of
$PATH to find the symbolizer and produce pretty backtraces if they crash.

llvm-svn: 272232
2016-06-09 00:53:21 +00:00
Benjamin Kramer c321e53402 Apply most suggestions of clang-tidy's performance-unnecessary-value-param
Avoids unnecessary copies. All changes audited & pass tests with asan.
No functional change intended.

llvm-svn: 272190
2016-06-08 19:09:22 +00:00
Sjoerd Meijer 3c2f785769 AsmWriterEmitter.cpp assumes that all operands of a printed alias
will appear after a blank. This assumption does not hold in the ARM
target.

Patch by: Roger Ferrer Ibanez

Differential Revision: http://reviews.llvm.org/D20234

llvm-svn: 271666
2016-06-03 13:17:37 +00:00
Sjoerd Meijer 84e2f69245 Currently AsmWriterEmiter.cpp (used by tblgen -gen-asm-writer) does not
consider the Predicates attached to InstAlias when generating printAliasInstr.
This forces users of printAliasInstr to check those predicates beforehand.

This commit adds them in the condition set of the IAPrinter object.

Patch by: Roger Ferrer Ibanez

Differential Revision: http://reviews.llvm.org/D20233

llvm-svn: 271665
2016-06-03 13:14:19 +00:00
Benjamin Kramer 82de7d323d Apply clang-tidy's misc-move-constructor-init throughout LLVM.
No functionality change intended, maybe a tiny performance improvement.

llvm-svn: 270997
2016-05-27 14:27:24 +00:00
Benjamin Kramer 4fed928f53 Avoid some copies by using const references.
clang-tidy's performance-unnecessary-copy-initialization with some manual
fixes. No functional changes intended.

llvm-svn: 270988
2016-05-27 12:30:51 +00:00
Matt Arsenault 4fb996e82d TableGen: Use StringRef instead of std::string
llvm-svn: 270741
2016-05-25 18:07:40 +00:00
Eugene Zelenko 75259bb3cb Fix Clang-tidy modernize-use-bool-literals in generated Target code; other minor fixes; other minor fixes.
Make generated code more readable.

Fix some Include What You Use warnings.

Differential revision: http://reviews.llvm.org/D20317

llvm-svn: 269783
2016-05-17 17:04:23 +00:00
Justin Bogner 1df01f0e31 SDAG: Make SelectCodeCommon return void
This means SelectCode unconditionally returns nullptr now. I'll follow
up with a change to make that return void as well, but it seems best
to keep that one very mechanical.

This is part of the work to have Select return void instead of an
SDNode *, which is in turn part of llvm.org/pr26808.

llvm-svn: 269136
2016-05-10 22:58:26 +00:00
Sam Kolton 5f10a137d0 [TableGen] AsmMatcher: support for default values for optional operands
Summary:
This change allows to specify "DefaultMethod" for optional operand (IsOptional = 1) in AsmOperandClass that return default value for operand. This is used in convertToMCInst to set default values in MCInst.
Previously if you wanted to set default value for operand you had to create custom converter method. With this change it is possible to use standard converters even when optional operands presented.

Reviewers: tstellarAMD, ab, craig.topper

Subscribers: jyknight, dsanders, arsenm, nhaustov, llvm-commits

Differential Revision: http://reviews.llvm.org/D18242

llvm-svn: 268726
2016-05-06 11:31:17 +00:00
Craig Topper c6b3669884 [TableGen] Fix a memory leak when creating SwitchOpcodeMatchers.
llvm-svn: 268712
2016-05-06 06:56:14 +00:00
Craig Topper 332dd6614a [TableGen] Remove isSafeToReorderWithPatternPredicate from DAGISelMatchers as its not used anymore.
llvm-svn: 268711
2016-05-06 06:21:27 +00:00
Craig Topper 05e772b36b [TableGen] Remove getHash support from DAGISelMatcher. It hasn't been used for some time.
llvm-svn: 268706
2016-05-06 02:37:59 +00:00
Craig Topper b3fb529cc6 [TableGen] Remove SinkPatternPredicates from the DAG isel matcher optimizer.
Pattern predicates already appear to be emitted as far down as they can be. The optimization was making no changes on any in-tree target.

llvm-svn: 268705
2016-05-06 02:37:56 +00:00
Justin Bogner 465886ece1 SDAG: Remove OPC_MarkGlueResults and associated logic. NFC
This opcode never happens in practice, and yet the logic we have in
place to handle it would be undefined behaviour if we ever executed
it. Remove it rather than trying to refactor code that's never
reached.

llvm-svn: 268692
2016-05-05 22:37:45 +00:00
Craig Topper 94753520c6 [TableGen] Make sure to recursively factor any ScopeMatchers created while forming a SwitchType node. Remove a couple hundred bytes from the X86 matcher table.
llvm-svn: 268611
2016-05-05 06:19:27 +00:00
Craig Topper d34bf350b2 [TableGen] Remove stale comment.
llvm-svn: 268610
2016-05-05 06:19:25 +00:00
Craig Topper 3fc0e668ff [CodeGen] Add some space optimized forms of EmitNode and MorphNodeTo that implicitly indicate the number of result VTs. This shaves about 16K off the X86 matching table taking it down to about 470K.
Overall this reduces the llc binary size with all in-tree targets by about 40K.

llvm-svn: 268365
2016-05-03 05:54:13 +00:00
Craig Topper e3c1e225d7 [CodeGen] Add OPC_MoveChild0-OPC_MoveChild7 opcodes to isel matching tables to optimize table size. Shaves about 12K off the X86 matcher table.
llvm-svn: 268209
2016-05-02 01:53:30 +00:00
Matthias Braun 39d1fad554 TableGen: Produce CoveredBySubRegs summary for register classes
This will be used in the upcoming "DetectDeadLanes" pass.

llvm-svn: 267850
2016-04-28 03:07:11 +00:00
Matthias Braun cd69bcf6d5 TargetRegisterInfo: Introduce reverseComposeSubRegIndexLaneMask()
This function performs the reverse computation of
composeSubRegIndexLaneMask().

It will be used in the upcoming "DetectDeadLanes" pass.

llvm-svn: 267849
2016-04-28 03:07:07 +00:00
Matthias Braun ff04541f4a TableGen: Support lanemasks for classes without subregisters
Previously using lanemasks on registers without any subregisters was not
well defined. This commit extends TargetRegisterInfo/tablegen to:
- Report a lanemask of 1 for regclasses without subregisters
- Do the right thing when mapping a 0/1 lanemask from a class without
  subregisters into a class with subregisters in
  TargetRegisterInfo::composeSubRegIndexLaneMasks().

This will be used in the upcoming "DetectDeadLanes" patch.

llvm-svn: 267848
2016-04-28 03:07:04 +00:00
Nicolai Haehnle 97788020c5 Split IntrReadArgMem into IntrReadMem and IntrArgMemOnly
Summary:
IntrReadWriteArgMem simply becomes IntrArgMemOnly.

So there are fewer intrinsic properties that express their orthogonality
better, and correspond more closely to the corresponding IR attributes.

Suggested by: Philip Reames

Reviewers: joker.eph, reames, tstellarAMD

Subscribers: jholewinski, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D19291

llvm-svn: 267021
2016-04-21 17:48:02 +00:00
Amaury Sechet 60b31453ac Add LLVMGetAttrKindID in the C API in order to facilitate migration away from LLVMAttribute
Summary:
LLVMAttribute has outlived its utility and is becoming a problem for C API users that what to use all the LLVM attributes. In order to help moving away from LLVMAttribute in a smooth manner, this diff introduce LLVMGetAttrKindIDInContext, which can be used instead of the enum values.

See D18749 for reference.

Reviewers: Wallbraker, whitequark, joker.eph, echristo, rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D19081

llvm-svn: 266842
2016-04-20 01:02:12 +00:00
Nicolai Haehnle b48275f134 Add IntrWrite[Arg]Mem intrinsic property
Summary:
This property is used to mark an intrinsic that only writes to memory, but
neither reads from memory nor has other side effects.

An example where this is useful is the llvm.amdgcn.buffer.store.format.*
intrinsic, which corresponds to a store instruction that goes through a special
buffer descriptor rather than through a plain pointer.

With this property, the intrinsic should still be handled as having side
effects at the LLVM IR level, but machine scheduling can make smarter
decisions.

Reviewers: tstellarAMD, arsenm, joker.eph, reames

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D18291

llvm-svn: 266826
2016-04-19 21:58:33 +00:00
Nicolai Haehnle 152c18e9ac [TableGen] Make an error message slightly more informative
Reviewers: ab, spop, stoklund

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D19192

llvm-svn: 266823
2016-04-19 21:58:10 +00:00
Mehdi Amini b550cb1750 [NFC] Header cleanup
Removed some unused headers, replaced some headers with forward class declarations.

Found using simple scripts like this one:
clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap'

Patch by Eugene Kosov <claprix@yandex.ru>

Differential Revision: http://reviews.llvm.org/D19219

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 266595
2016-04-18 09:17:29 +00:00
Craig Topper 6ff46266d1 Declare MVT::SimpleValueType as an int8_t sized enum. This removes 400 bytes from TargetLoweringBase and probably other places.
This required changing several places to print VT enums as strings instead of raw ints since the proper method to use to print became ambiguous. This is probably an improvement anyway.

This also appears to save ~8K from an x86 self host build of llc.

llvm-svn: 266562
2016-04-17 17:37:33 +00:00
Richard Smith 2db6f2e508 Update and fix LLVM_ENABLE_MODULES:
1) We need to add this flag prior to adding any other, in case the user has
specified a -fmodule-cache-path= flag in their custom CXXFLAGS. Such a flag
causes -Werror builds to fail, and thus all config checks fail, until we add
the corresponding -fmodules flag. The modules selfhost bot does this, for
instance.

2) Delete module maps that were putting .cpp files into modules.

3) Enable -fmodules-local-submodule-visibility, to get proper module
visibility rules applied across submodules of the same module. Disable
-fmodules for C builds, since that flag is not available there.

llvm-svn: 266502
2016-04-16 00:48:58 +00:00
Amaury Sechet 2a734db7d3 Revert "Add LLVMGetAttrKindIDInContext in the C API in order to facilitate migration away from LLVMAttribute"
This reverts commit 0bcfd95c268bcb180a525e1837e84475df8acdc7.

llvm-svn: 266259
2016-04-13 23:01:39 +00:00
Amaury Sechet 3ef4e4a98c Add LLVMGetAttrKindIDInContext in the C API in order to facilitate migration away from LLVMAttribute
Summary: LLVMAttribute has outlived its utility and is becoming a problem for C API users that what to use all the LLVM attributes. In order to help moving away from LLVMAttribute in a smooth manner, this diff introduce LLVMGetAttrKindIDInContext, which can be used instead of the enum values.

Reviewers: Wallbraker, whitequark, joker.eph, echristo

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D18749

llvm-svn: 266257
2016-04-13 22:51:40 +00:00
Junmo Park 9154b88cfe Minor code cleanup. NFC.
llvm-svn: 266045
2016-04-12 06:02:11 +00:00
Valery Pykhtin 020c29e2b7 [TableGen] AsmMatcherEmitter.cpp: replace a sequence of "if" to "switch" in emitValidateOperandClass.
Differential Revision: http://reviews.llvm.org/D18394

llvm-svn: 265412
2016-04-05 16:18:16 +00:00
Nicolai Haehnle 411fbbf5f3 [TableGen] more helpful error message in MapTableEmitter
Differential Revision: http://reviews.llvm.org/D17275

llvm-svn: 263148
2016-03-10 18:51:58 +00:00
Craig Topper 267bdb2094 [CodeGen] Add space-optimized EmitMergeInputChains1_2 to the DAG isel matching tables. Shaves about 5100 bytes from the X86 matcher table. NFC
llvm-svn: 262815
2016-03-07 07:29:12 +00:00
Matthias Braun 42d9ad9c5b TableGen: Accept itinerary data when checking for schedmodel completeness
llvm-svn: 262548
2016-03-03 00:04:59 +00:00