ece825dc4f
Data type suffix must come after predicate.
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llvm-svn: 89723
2009-11-24 01:05:23 +00:00
2522908653
Materialize global addresses via movt/movw pair, this is always better
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than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
llvm-svn: 89720
2009-11-24 00:44:37 +00:00
f890f51666
80 column violations
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llvm-svn: 89718
2009-11-24 00:20:27 +00:00
f2ad571443
* Move stub allocation inside the JITEmitter, instead of exposing a
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way for each TargetJITInfo subclass to allocate its own stubs. This
means stubs aren't as exactly-sized anymore, but it lets us get rid of
TargetJITInfo::emitFunctionStubAtAddr(), which lets ARM and PPC
support the eager JIT, fixing http://llvm.org/PR4816 .
* Rename the JITEmitter's stub creation functions to describe the kind
of stub they create. So far, all of them create lazy-compilation
stubs, but they sometimes get used when far-call stubs are needed.
Fixing http://llvm.org/PR5201 will involve fixing this.
llvm-svn: 89715
2009-11-23 23:35:19 +00:00
de5dea869f
Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
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Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
llvm-svn: 89711
2009-11-23 23:20:51 +00:00
19b48370fb
Allow more than one stub to be being generated at the same time.
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It's probably better in the long run to replace the
indirect-GlobalVariable system. That'll be done after a subsequent
patch.
llvm-svn: 89708
2009-11-23 22:49:00 +00:00
738a97a1db
Massive refactoring of NEON instructions. Separate opcode from data size specifier suffix, move \t up stream to instruction format, and fix more 80 column violations.
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This fixes the NEON asm printing so the "predicate" field is printed between the opcode and the data type suffix.
llvm-svn: 89706
2009-11-23 21:57:23 +00:00
dbb4140f37
move fconst[sd] to UAL. <rdar://7414913>
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llvm-svn: 89700
2009-11-23 21:08:25 +00:00
b6528d3244
Partially revert r84730 by removing N2VDup from ARMInstrFormats.td and modifying
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VDUPLND and VDUPLNQ to derive from N2V instead of N2VDup. VDUPLND and VDUPLNQ
now expect op19_18 and op17_16 as the first two args.
llvm-svn: 89699
2009-11-23 21:00:43 +00:00
04c0e76772
fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate.
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llvm-svn: 89694
2009-11-23 20:35:53 +00:00
5ad7416260
Revert r84572 by removing N3VImm from ARMInstrFormats.td now that we can specify
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{?,?,?,?} as op11_8 for VEXTd and VEXTq.
llvm-svn: 89693
2009-11-23 20:09:13 +00:00
e97457afbc
Partially revert r89377 by removing NLdStLN class definition from
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ARMInstrFormats.td and fixing VLD[234]LN* and VST[234]LN* to derive from NLdSt
instead of NLdStLN.
llvm-svn: 89684
2009-11-23 18:16:16 +00:00
ebc60ef80c
Make it clear that the index bit(s) of Vector Get Lane and Vector Set Lane
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should be left unspecified now that Bob Wilson has fixed pr5470.
llvm-svn: 89676
2009-11-23 17:48:17 +00:00
1f2457f8aa
Minor itinerary fixes for FP instructions.
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llvm-svn: 89672
2009-11-23 17:34:12 +00:00
fd963e11f5
Move default FrameReg val to getFrameIndexReference(). Otherwise, debug info can get bogus values.
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llvm-svn: 89618
2009-11-22 20:05:32 +00:00
90e9062e96
Generate more correct debug info for frame indices.
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llvm-svn: 89576
2009-11-22 02:32:29 +00:00
abdf86d2be
Minor optimization: when doing eq/ne comparions and RHS is a constant - swap operands, this will allow us to fold imm into comparison.
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llvm-svn: 89574
2009-11-22 01:14:08 +00:00
3a31644c7a
Drop unsupported imm operands
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llvm-svn: 89573
2009-11-22 01:13:54 +00:00
a9c7bb724a
Use 2-byte alignment for functions. 4 bytes are clear overkill here.
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llvm-svn: 89572
2009-11-22 01:13:39 +00:00
d099b578e4
Use semicolon as assembler comment string
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llvm-svn: 89571
2009-11-22 01:12:49 +00:00
e09e95b35c
Revert 89562. We're being sneakier than I was giving us credit for, and this
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isn't necessary.
llvm-svn: 89568
2009-11-21 23:34:09 +00:00
43fd822249
Darwin requires a frame pointer for all non-leaf functions to support correct
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backtraces.
llvm-svn: 89562
2009-11-21 21:40:08 +00:00
a33fc86be3
Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.
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llvm-svn: 89542
2009-11-21 06:21:52 +00:00
ed85e12da6
We are not using DBG_STOPPOINT anymore.
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llvm-svn: 89536
2009-11-21 02:46:55 +00:00
7dcca8f7fc
Added two SubtargetFeatures::AddFeatures methods, which accept a comma-separated string or already parsed command line parameters as input, and some code re-factoring to use these new methods.
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llvm-svn: 89516
2009-11-21 00:00:02 +00:00
312971513f
Fix a thinko that caused spurious @GOTOFFs.
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llvm-svn: 89509
2009-11-20 23:30:32 +00:00
e14b347176
Update for new getBlockAddress signature.
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llvm-svn: 89507
2009-11-20 23:21:00 +00:00
7a6611793f
Target-independent support for TargetFlags on BlockAddress operands,
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and support for blockaddresses in x86-32 PIC mode.
llvm-svn: 89506
2009-11-20 23:18:13 +00:00
c1f532e930
Recommitting PALIGNR shift width fixes.
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Thanks to Daniel Dunbar for fixing clang intrinsics:
http://llvm.org/viewvc/llvm-project?view=rev&revision=89499
llvm-svn: 89500
2009-11-20 22:28:42 +00:00
8495a506eb
Remove an incorrect overaggressive optimization
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(PPC specific).
llvm-svn: 89496
2009-11-20 22:16:40 +00:00
19d92728d0
Reverting PALIGNR fix until I figure out how this
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broke the Clang testsuite.
llvm-svn: 89495
2009-11-20 22:09:28 +00:00
fbed130173
Fixed PALIGNR to take 8-bit rotations in all cases.
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Also fixed the corresponding testcase, and the PALIGNR
intrinsic (tested for correctness with llvm-gcc).
llvm-svn: 89491
2009-11-20 21:40:28 +00:00
bdb43a9d99
Remat VLDRD from constpool. Clean up some instruction property specifications.
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llvm-svn: 89478
2009-11-20 19:57:15 +00:00
6c3b71195a
The verify() call of CPEIsInRange() isn't right for the assertion check of
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constant pool ranges, as CPEIsInRange() makes conservative assumptions about
the potential alignment changes from branch adjustments. The verification,
on the other hand, runs after those branch adjustments are made, so the
effects on alignment are known and already taken into account. The sanity
check in verify should check the range directly instead.
llvm-svn: 89473
2009-11-20 19:37:38 +00:00
fc81352e3f
Remove verifySizes() since it's not adding much value.
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llvm-svn: 89443
2009-11-20 02:32:06 +00:00
bbd50b0f78
Also CSE non-pic load from constant pools.
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llvm-svn: 89440
2009-11-20 02:10:27 +00:00
81a2851bcb
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all.
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llvm-svn: 89423
2009-11-20 00:54:03 +00:00
a6380af658
Update comment to reflect instruction.
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llvm-svn: 89414
2009-11-20 00:21:55 +00:00
b73918c42d
When placing constant islands and adjusting for alignment padding, inline
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assembly can confuse things utterly, as it's assumed that instructions in
inline assembly are 4 bytes wide. For Thumb mode, that's often not true,
so the calculations for when alignment padding will be present get thrown off,
ultimately leading to out of range constant pool entry references. Making
more conservative assumptions that padding may be necessary when inline asm
is present avoids this situation.
llvm-svn: 89403
2009-11-19 23:10:28 +00:00
b6c7704a8d
Refactor cmov selection code out to a separate function. No functionality change.
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llvm-svn: 89396
2009-11-19 21:45:22 +00:00
31c74dbb10
Reverting the EH table patches.
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$ svn merge -c -89279 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r89279 into '.':
U lib/CodeGen/AsmPrinter/DwarfException.cpp
U lib/Target/TargetLoweringObjectFile.cpp
$ svn merge -c -89270 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r89270 into '.':
G lib/CodeGen/AsmPrinter/DwarfException.cpp
G lib/Target/TargetLoweringObjectFile.cpp
llvm-svn: 89379
2009-11-19 19:21:09 +00:00
b3b8209d77
Added NLdStLN which is similar to NLdSt with the exception that op7_4 is not
...
fully specified at this level. Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.
llvm-svn: 89377
2009-11-19 19:20:17 +00:00
36a5bf82bf
fix typo
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llvm-svn: 89369
2009-11-19 18:23:19 +00:00
91431b008b
Fix a typo in a comment.
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llvm-svn: 89360
2009-11-19 16:35:11 +00:00
82adca8373
80 col violation.
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llvm-svn: 89337
2009-11-19 08:16:50 +00:00
b18525937c
More consistent thumb1 asm printing.
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llvm-svn: 89328
2009-11-19 06:57:41 +00:00
2a6c92fcb6
Shrink ldr / str [sp, imm0-1024] to 16-bit instructions.
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llvm-svn: 89326
2009-11-19 06:32:27 +00:00
547abae38d
Eliminate more * 4 in Thumb1 asm printing for consistency sake.
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llvm-svn: 89325
2009-11-19 06:31:26 +00:00
4713b282ce
- Add sugregister logic to handle f64=(f32,f32).
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- Support mips1 like load/store of doubles:
Instead of:
sdc $f0, X($3)
Generate:
swc $f0, X($3)
swc $f1, X+4($3)
llvm-svn: 89322
2009-11-19 06:06:13 +00:00
8bd87239d7
Only use small sections for non linux targets!
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llvm-svn: 89316
2009-11-19 05:28:18 +00:00
Evan Cheng