fdb25de17e
Switch SubRegSet to using symbolic SubRegIndices
...
llvm-svn: 104571
2010-05-24 23:03:18 +00:00
91b2b8540c
Allow Thumb2 MVN instructions to set condition codes. The immediate operand
...
version of t2MVN already allowed that, but not the register versions.
llvm-svn: 104570
2010-05-24 22:41:19 +00:00
76b3de92f2
diaggroup categories should take precedence over diag-specific groups.
...
llvm-svn: 104567
2010-05-24 21:55:47 +00:00
1181a19318
Lose the dummies
...
llvm-svn: 104564
2010-05-24 21:47:01 +00:00
edab242488
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
...
structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
llvm-svn: 104563
2010-05-24 21:46:58 +00:00
1b79babdec
Avoid adding duplicate function live-in's.
...
llvm-svn: 104560
2010-05-24 21:33:37 +00:00
79b6a0f140
Fix an mmx movd encoding.
...
llvm-svn: 104552
2010-05-24 20:51:08 +00:00
dc71cc794b
MC/X86: Add aliases for CMOVcc variants.
...
llvm-svn: 104549
2010-05-24 20:32:23 +00:00
722bff2c7d
Clean up some extra whitespace.
...
llvm-svn: 104544
2010-05-24 20:08:34 +00:00
3eb7691858
Thumb2 RSBS instructions were being printed without the 'S' suffix.
...
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.
llvm-svn: 104531
2010-05-24 18:44:06 +00:00
51b37e0bd8
Do not emit line number entries for unknown debug values.
...
This fixes recent regression in store.exp from gdb testsuite.
llvm-svn: 104524
2010-05-24 18:26:49 +00:00
755d45be43
LR is in GPR, not tGPR even in Thumb1 mode.
...
llvm-svn: 104518
2010-05-24 18:00:18 +00:00
ff2d118733
Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices are
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never used.
llvm-svn: 104517
2010-05-24 17:55:38 +00:00
8a57aeca2a
Use SubRegIndex in SystemZ.
...
Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug.
llvm-svn: 104515
2010-05-24 17:43:01 +00:00
5d56769fb6
SubRegIndex'ize Mips
...
llvm-svn: 104514
2010-05-24 17:42:58 +00:00
fd6f16fab9
SubRegIndex'ize MSP430
...
llvm-svn: 104513
2010-05-24 17:42:55 +00:00
8d042c0269
Fix a few places that depended on the numeric value of subreg indices.
...
Add assertions in places that depend on consecutive indices.
llvm-svn: 104510
2010-05-24 17:13:28 +00:00
6c47d6423c
Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
...
from ARMRegisterInfo.h
llvm-svn: 104508
2010-05-24 16:54:32 +00:00
9340ea59e1
Rename X86 subregister indices to something shorter.
...
Use the tablegen-produced enums.
llvm-svn: 104493
2010-05-24 14:48:17 +00:00
1c69646e99
Add the SubRegIndex TableGen class.
...
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.
llvm-svn: 104492
2010-05-24 14:48:12 +00:00
c5327226e4
Encode the Caml frametable by following what the comment says: the number of descriptors
...
is first emitted, and StackOffsets are emitted in 16 bits.
llvm-svn: 104488
2010-05-24 12:24:11 +00:00
e9cd6d069d
Apply timeouts and memory limits in more places. In particular, when
...
bugpoint does "Running the code generator to test for a crash" this
gets you a crash if llc goes into an infinite loop or uses up vast
amounts of memory.
llvm-svn: 104485
2010-05-24 07:49:55 +00:00
6738a2e39e
llvm-mc: Use EmitIntValue where possible, which makes the API calls from the AsmParser and CodeGen line up better.
...
llvm-svn: 104467
2010-05-23 18:36:38 +00:00
8271d1bb4a
llvm-mc: Use AddBlankLine in asm parser. This makes transliteration match the input much more closely, and also makes the API calls from the AsmParser and CodeGen line up better.
...
llvm-svn: 104466
2010-05-23 18:36:34 +00:00
3ff1a06de6
MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches.
...
llvm-svn: 104463
2010-05-23 17:44:06 +00:00
49f40e8c32
VDUP doesn't support vectors with 64-bit elements.
...
llvm-svn: 104455
2010-05-23 05:42:31 +00:00
b52fcd6304
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
...
addw $0xFFFF, %ax
should match the same as
addw $-1, %ax
but we used to match it to the longer encoding.
llvm-svn: 104453
2010-05-22 21:02:33 +00:00
346782c12c
tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one.
...
llvm-svn: 104452
2010-05-22 21:02:29 +00:00
d459e29a0a
MC/X86: Add alias for setz, setnz, jz, jnz.
...
llvm-svn: 104435
2010-05-22 06:37:33 +00:00
987a1576d2
Trivial change to dump() function for SparseBitVector
...
llvm-svn: 104433
2010-05-22 05:13:17 +00:00
168ced94d8
Implement @llvm.returnaddress. rdar://8015977.
...
llvm-svn: 104421
2010-05-22 01:47:14 +00:00
bd9485db63
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
...
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
llvm-svn: 104419
2010-05-22 01:06:18 +00:00
64087cd346
This test is darwin only. Make it so(tm).
...
llvm-svn: 104418
2010-05-22 00:55:55 +00:00
91fdf68516
Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
...
copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.
llvm-svn: 104415
2010-05-22 00:23:12 +00:00
6fdea1bda8
Add full bss data support for darwin tls variables.
...
llvm-svn: 104414
2010-05-22 00:10:22 +00:00
4a8e6e83dc
Collect variable information during endFunction() instead of beginFunction().
...
llvm-svn: 104412
2010-05-22 00:04:14 +00:00
75ed30b593
Add a new section and accessor for TLS data.
...
llvm-svn: 104411
2010-05-22 00:00:58 +00:00
61438fe064
Clean up extra whitespace.
...
llvm-svn: 104410
2010-05-21 23:53:55 +00:00
53ff992dde
Make this LookAheadLimit, not the uninitialized LookAheadLeft.
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Evan please verify!
llvm-svn: 104408
2010-05-21 23:40:03 +00:00
4dc833c607
add a note
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llvm-svn: 104404
2010-05-21 23:16:21 +00:00
09d47031b1
Expand on comment.
...
llvm-svn: 104396
2010-05-21 23:03:53 +00:00
7e7482c80f
Added retl for 32-bit x86 and added retq for 64-bit x86.
...
llvm-svn: 104394
2010-05-21 23:01:38 +00:00
0624d5226c
Fix comment and whitespace.
...
llvm-svn: 104392
2010-05-21 22:39:11 +00:00
37c529ae68
expand on the llvm ir bitcode dox. Patch by Peter Housel!
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llvm-svn: 104391
2010-05-21 22:20:54 +00:00
2c8bdead9e
Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs.
...
llvm-svn: 104385
2010-05-21 21:22:19 +00:00
3dca28d0e2
Fix section attribute name.
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llvm-svn: 104381
2010-05-21 21:08:52 +00:00
51d9ee3ff6
Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements
...
so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.
llvm-svn: 104380
2010-05-21 21:05:32 +00:00
3858451e09
- Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs
...
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.
llvm-svn: 104377
2010-05-21 20:53:24 +00:00
7d7f604321
Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction
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reads or writes a register.
This takes partial redefines and undef uses into account.
Don't actually use it yet. That caused miscompiles.
llvm-svn: 104372
2010-05-21 20:02:01 +00:00
1782aae355
Simplify
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llvm-svn: 104338
2010-05-21 18:49:09 +00:00
2b78565842
Previous commit message should refer to 104308.
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llvm-svn: 104337
2010-05-21 18:44:47 +00:00
6361e3e8a2
Fix two bugs in 104348:
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Case where MMX is disabled wasn't handled right.
MMX->MMX bitconverts are Legal.
llvm-svn: 104336
2010-05-21 18:40:15 +00:00
ea91abddfe
added an assertion to MCObjectWriter::WriteBytes to catch misuse of the ZeroFillSize parameter
...
If the size of the string is greater than the zero fill size, the function will attempt to write a very large string of zeros to the object file (~4GB on 32 bit platforms). This assertion will catch the scenario and crash the program before the write occurs.
llvm-svn: 104334
2010-05-21 18:23:56 +00:00
0735ecfe17
now that fp reg kill insertion stuff happens as a separate
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pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.
The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes. Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross. It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).
Just do the scan on machine phis which is simpler, faster
and more correct. This fixes PR6828.
llvm-svn: 104333
2010-05-21 18:17:54 +00:00
058a207436
Use less evil form of switch stmt.
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llvm-svn: 104331
2010-05-21 18:02:42 +00:00
39a8a43bd8
use continue to reduce nesting.
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llvm-svn: 104330
2010-05-21 18:01:24 +00:00
b7d68a2256
pull a nested loop of this pass out to its own function,
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eliminating the gymnastics around the ContainsFPCode var.
llvm-svn: 104328
2010-05-21 17:57:03 +00:00
fb41aaefeb
modernize this pass a bit, fit in 80 columns.
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llvm-svn: 104326
2010-05-21 17:49:07 +00:00
a81e1cab04
constify accessor.
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llvm-svn: 104325
2010-05-21 17:47:50 +00:00
b4e1687270
Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read."
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This reverts r104322. I think it was causing miscompilations.
llvm-svn: 104323
2010-05-21 17:36:32 +00:00
8e8e090301
Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.
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This correctly handles partial redefines and undef uses.
llvm-svn: 104322
2010-05-21 16:42:30 +00:00
a648c6a757
Teach VirtRegRewriter to handle spilling in instructions that have multiple
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definitions of the virtual register.
This happens when spilling the registers produced by REG_SEQUENCE:
%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0
The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.
llvm-svn: 104321
2010-05-21 16:36:13 +00:00
1f3801062d
If the first definition of a virtual register is a partial redef, add an
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<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.
llvm-svn: 104320
2010-05-21 16:32:16 +00:00
638cdb2db1
Currently, createMachOStreamer() is invoked directly in llvm-mc which
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isn't ideal if we want to be able to use another object file format.
Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.
llvm-svn: 104318
2010-05-21 12:54:43 +00:00
5abb6dd61e
Split out the x86_32 an x86_64 ELF backends as they handle ELF
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differently. This will make adding ELF support easier in the long run.
llvm-svn: 104317
2010-05-21 11:39:07 +00:00
ec9d6faef0
Add support for parsing the ELF .type assembler directive.
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llvm-svn: 104316
2010-05-21 11:36:59 +00:00
d5f0998c6e
Removed scaleNumbering method declaration from LiveInterval (not defined, not used).
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llvm-svn: 104311
2010-05-21 03:04:04 +00:00
b3b9c8ac48
Fix i64->f64 conversion, x86-64, -no-sse. A bit
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tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.
llvm-svn: 104308
2010-05-21 00:52:33 +00:00
34c260458a
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
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llvm-svn: 104307
2010-05-21 00:43:17 +00:00
725211e948
Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.
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llvm-svn: 104306
2010-05-21 00:42:32 +00:00
e85262d651
Remove dead option.
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llvm-svn: 104303
2010-05-21 00:27:55 +00:00
fbd6c45e06
Simplify.
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llvm-svn: 104302
2010-05-21 00:10:20 +00:00
c120ffe3f6
Fix __crashreport_info__ declaration.
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llvm-svn: 104300
2010-05-20 23:50:19 +00:00
4401f8873c
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
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llvm-svn: 104293
2010-05-20 23:26:43 +00:00
9b48b856ea
DominatorTree.getNode can return null for unreachable blocks.
...
llvm-svn: 104290
2010-05-20 22:46:54 +00:00
86110fa2bb
Minor code cleanups.
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llvm-svn: 104287
2010-05-20 22:25:20 +00:00
3a48292204
Print a space after the colon.
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llvm-svn: 104279
2010-05-20 21:11:37 +00:00
6295f2ebb8
Make Solve check its own post-condition, to reduce clutter in the
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top-level LSRInstance logic.
llvm-svn: 104278
2010-05-20 20:59:23 +00:00
a4ca28a3ae
Add comments.
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llvm-svn: 104276
2010-05-20 20:52:00 +00:00
baf2eea6f4
MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq.
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llvm-svn: 104275
2010-05-20 20:36:29 +00:00
0adee9b362
Rename variable. add comment.
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llvm-svn: 104274
2010-05-20 20:35:24 +00:00
927bcaadda
More code cleanups. Use iterators instead of indices when indices
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aren't needed.
llvm-svn: 104273
2010-05-20 20:33:18 +00:00
61655aa2bb
X86: Model i64i32imm properly, as a subclass of all immediates.
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llvm-svn: 104272
2010-05-20 20:20:39 +00:00
6d4c66dc1d
X86: Fix immediate type of FOO64i32 operations.
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llvm-svn: 104271
2010-05-20 20:20:35 +00:00
5661c0c755
tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor
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it.
llvm-svn: 104270
2010-05-20 20:20:32 +00:00
4c4043cf34
Fix OptimizeShadowIV to set Changed. Change OptimizeLoopTermCond to set
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Changed directly instead of using a return value.
Rename FilterOutUndesirableDedicatedRegisters's Changed variable to
distinguish it from LSRInstance's Changed member.
llvm-svn: 104269
2010-05-20 20:05:31 +00:00
8ec018cedf
Add some comments.
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llvm-svn: 104268
2010-05-20 20:00:41 +00:00
8ce95cc3c5
Simplify this code. Don't do a DomTreeNode lookup for each visited block.
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llvm-svn: 104267
2010-05-20 20:00:25 +00:00
490c8ab76d
Refactor.
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llvm-svn: 104265
2010-05-20 19:57:06 +00:00
141791c6d1
Grammar fix. This is a test commit.
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llvm-svn: 104264
2010-05-20 19:45:09 +00:00
ab5fb7f559
Minor code cleanups.
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llvm-svn: 104263
2010-05-20 19:44:23 +00:00
ee2fea3cd7
When canonicalizing icmp operand order to put the loop invariant
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operand on the left, the interesting operand is on the right. This
fixes a bug where LSR was failing to recognize ICmpZero uses,
which led it to be unable to reverse the induction variable in the
attached testcase.
Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test
is extremely fragile and hard to meaningfully update.
llvm-svn: 104262
2010-05-20 19:26:52 +00:00
3e69aa0399
llvmc: Make segfault detection work on Win32.
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llvm-svn: 104261
2010-05-20 19:23:47 +00:00
fdf9874ba7
Set Changed to true when canonicalizing ICmp operand order; even though
...
it isn't a very interesting change, it's a change nonetheless.
llvm-svn: 104260
2010-05-20 19:16:03 +00:00
5954994bba
Handle Neon v2f64 and v2i64 vector shuffles as register copies.
...
This fixes the remaining issue with pr7167.
llvm-svn: 104257
2010-05-20 18:39:53 +00:00
63d4f68df4
Remove dbg_value workaround and associated command line option
...
llvm-svn: 104254
2010-05-20 18:34:01 +00:00
098a47931c
Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn't
...
have a pattern and it had an invalid encoding.
llvm-svn: 104244
2010-05-20 18:05:01 +00:00
d7d6638e3e
The PPC MFCR instruction implicitly uses all 8 of the CR
...
registers. Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
vreg = MCRF CR0
MFCR <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment). That avoids all problems. 7739628.
llvm-svn: 104238
2010-05-20 17:48:26 +00:00
e2ff7f3a7d
Strip llvm.dbg.lv also.
...
llvm-svn: 104236
2010-05-20 16:49:22 +00:00
981563d0ba
Rename a variable to avoid shadowing.
...
llvm-svn: 104234
2010-05-20 16:41:11 +00:00
e1c53f29d3
Split DbgVariable. Eventually, variable info will be communicated through frame index, or DBG_VALUE instruction, or collection of DBG_VALUE instructions. Plus each DbgVariable may not need a label.
...
llvm-svn: 104233
2010-05-20 16:36:41 +00:00
6b733fc189
Minor code simplification.
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llvm-svn: 104232
2010-05-20 16:23:28 +00:00
29790edb93
Fix assembly parsing and encoding of the pushf and popf family of
...
instructions.
llvm-svn: 104231
2010-05-20 16:16:00 +00:00
5238275478
Set neverHasSideEffects on 64-bit pushf and popf, for consistency with
...
16-bit and 32-bit pushf and popf.
llvm-svn: 104228
2010-05-20 15:42:55 +00:00
80a9608442
Move the code for deleting BaseRegs and LSRUses into helper functions,
...
and fix a bug that valgrind noticed where the code would std::swap an
element with itself.
llvm-svn: 104225
2010-05-20 15:17:54 +00:00
7c3e230cd1
Reduce string trashing.
...
llvm-svn: 104223
2010-05-20 14:14:22 +00:00
bdd062dae0
Add a hybrid bottom up scheduler that reduce register usage while avoiding
...
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.
llvm-svn: 104216
2010-05-20 06:13:19 +00:00
c53cc4f8bf
Fix typo in comment.
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llvm-svn: 104209
2010-05-20 03:30:09 +00:00
1e19eab963
Define the x86 pause instruction.
...
llvm-svn: 104204
2010-05-20 01:35:50 +00:00
a3b7570a3a
Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it
...
doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.
llvm-svn: 104203
2010-05-20 01:23:41 +00:00
1d88151079
Fix build by actually declaring the variable.
...
llvm-svn: 104201
2010-05-20 00:59:30 +00:00
27e7ffc7d4
Partial code for emitting thread local bss data.
...
llvm-svn: 104197
2010-05-20 00:49:07 +00:00
de852faef9
Match "4" or "8" depending upon if it's 32- or 64-bit.
...
llvm-svn: 104196
2010-05-20 00:27:10 +00:00
4b4446be7c
Once more, with feeling.
...
llvm-svn: 104190
2010-05-20 00:07:13 +00:00
04c4a399aa
lit: Add another place to look for bash.
...
llvm-svn: 104189
2010-05-19 23:56:09 +00:00
20fab456da
Teach LSR how to cope better with unrolled loops on targets where
...
the addressing modes don't make this trivially easy. This allows
it to avoid falling into the less precise heuristics in more
cases.
llvm-svn: 104186
2010-05-19 23:43:12 +00:00
42603958fb
Optimize away insertelement of an undef value. This shows up in
...
test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up. Radar 7998853.
llvm-svn: 104185
2010-05-19 23:42:58 +00:00
7cbfa4462f
fix rdar://7986634 - match instruction opcodes case insensitively.
...
llvm-svn: 104183
2010-05-19 23:34:33 +00:00
1c4687e350
Testcase for r104181.
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llvm-svn: 104182
2010-05-19 23:33:26 +00:00
f98511473e
Enable preserving debug information through post-RA scheduling
...
llvm-svn: 104175
2010-05-19 22:57:47 +00:00
604560c5fe
Fix the post-RA instruction scheduler to handle instructions referenced by
...
more than one dbg_value instruction. rdar://7759363
llvm-svn: 104174
2010-05-19 22:57:06 +00:00
70e506e18a
Code clean up.
...
llvm-svn: 104173
2010-05-19 22:42:23 +00:00
a08130864e
Revert r104165.
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llvm-svn: 104172
2010-05-19 21:58:28 +00:00
e0eddb21f5
Add support for partial redefs to the fast register allocator.
...
A partial redef now triggers a reload if required. Also don't add
<imp-def,dead> operands for physical superregisters.
Kill flags are still treated as full register kills, and <imp-use,kill> operands
are added for physical superregisters as before.
llvm-svn: 104167
2010-05-19 21:36:05 +00:00
0fe341e2e2
There is no need to maintain InsnsBeginScopeSet separately.
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llvm-svn: 104165
2010-05-19 21:26:53 +00:00
63476ddae6
A more combo tls testcase.
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llvm-svn: 104163
2010-05-19 21:19:42 +00:00
5d4c134a94
Add MachineInstr::readsVirtualRegister() in preparation for proper handling of
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partial redefines.
We are going to treat a partial redefine of a virtual register as a
read-modify-write:
%reg1024:6 = OP
Unless the register is fully clobbered:
%reg1024:6 = OP, %reg1024<imp-def>
MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.
llvm-svn: 104149
2010-05-19 20:36:22 +00:00
b95493c495
Few more simple tls testcases.
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llvm-svn: 104148
2010-05-19 20:35:15 +00:00
738e920edf
Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
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llvm-svn: 104147
2010-05-19 20:19:50 +00:00
e11cdf8cc8
TwoAddressInstructionPass doesn't really know how to merge live intervals when
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lowering REG_SEQUENCE instructions.
Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes.
llvm-svn: 104146
2010-05-19 20:08:00 +00:00
59a61fd7cc
llvmc: report an error if a child process segfaults.
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llvm-svn: 104145
2010-05-19 19:24:32 +00:00
6304da132f
Attempt to run this test on x86 only.
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llvm-svn: 104143
2010-05-19 18:59:37 +00:00
f070b1b571
Testcase to go with 104141.
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llvm-svn: 104142
2010-05-19 18:58:37 +00:00
6a1bfd282b
When expanding a vector_shuffle, the element type may not be legal and may
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need to be promoted. The BUILD_VECTOR and EXTRACT_VECTOR_ELT nodes generated
here already allow the promoted type to be used without further changes, so
just do the promotion. This fixes part of pr7167.
llvm-svn: 104141
2010-05-19 18:48:32 +00:00
52e37becf6
MC/X86: Add missing entry for TAILJMP_1 to getRelaxedOpcode().
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llvm-svn: 104122
2010-05-19 17:20:58 +00:00
d2f78e755f
MC/X86: Lower TAILCALLd[64] to JMP_1, to allow relaxation and to avoid same
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prefix byte problem as in r104062.
- As a total hack to keep the TAILCALL markers in the output, which some tests depend on, this invents a new TAILJMP_1 instruction.
llvm-svn: 104120
2010-05-19 15:26:43 +00:00
b243dfb085
MC/X86: Strip spurious operands from TAILJMPr64 as we do for CALL64r and
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CALL64pcrel32, for the same reason.
llvm-svn: 104116
2010-05-19 08:07:12 +00:00
daeca2d156
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
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llvm-svn: 104115
2010-05-19 07:28:01 +00:00
b7704fee4c
Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable.
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llvm-svn: 104114
2010-05-19 07:26:50 +00:00
4518c866b4
Update autoconf/automake versions in the documentation to match the versions used in Autogen.sh
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llvm-svn: 104113
2010-05-19 07:00:17 +00:00
4f6c7c6d94
MC/X86: Lower MOV{8,16,32,64}{rm,mr} to fixed-register forms, as appropriate.
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llvm-svn: 104112
2010-05-19 06:20:44 +00:00
dd7f566597
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
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llvm-svn: 104111
2010-05-19 06:07:03 +00:00
e89f5ae9d4
Target instruction selection should copy memoperands.
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llvm-svn: 104110
2010-05-19 06:06:09 +00:00
45ace40959
MC/X86: Strip spurious operands from CALL64r as we do for CALL64pcrel32, to
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avoid same prefix byte problem as in r104062.
llvm-svn: 104108
2010-05-19 04:31:36 +00:00
2c452fcd14
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
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llvm-svn: 104102
2010-05-19 01:52:25 +00:00
744c96dd48
Add a comment explaining why this code uses Append mode.
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llvm-svn: 104095
2010-05-19 01:21:34 +00:00
abd0ad54a4
Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.
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The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.
Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.
llvm-svn: 104094
2010-05-19 01:08:17 +00:00
58c6f21453
Factor out the code for picking integer arithmetic with immediate
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opcodes into a helper function. This fixes a few places in the code
which were not properly selecting the 8-bit-immediate opcodes.
llvm-svn: 104091
2010-05-19 00:53:19 +00:00
c09d5a29d8
Add a test to make sure that we're lowering the shift amount correctly.
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llvm-svn: 104090
2010-05-19 00:22:04 +00:00
beebef4137
Add a comment.
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llvm-svn: 104089
2010-05-18 23:55:57 +00:00
Jakob Stoklund Olesen