Commit Graph

353628 Commits

Author SHA1 Message Date
Simon Pilgrim ecd28d2401 [X86] Add AVX512VL concat-cast tests. 2020-05-07 15:08:17 +01:00
Lei Zhang 16027bbc3b [mlir][spirv] Serialize all operands together if possible
SPIR-V ops can mix operands and attributes in the definition. These
operands and attributes are serialized in the exact order of the definition
to match SPIR-V binary format requirements. It can cause excessive
generated code bloat because we are emitting code to handle each
operand/attribute separately. So here we probe first to check whether all
the operands are ahead of attributes. Then we can serialize all operands
together.

This removes ~1000 lines of code from the generated inc file.

Differential Revision: https://reviews.llvm.org/D79446
2020-05-07 09:32:03 -04:00
Lei Zhang a2634748cd [mlir][spirv] Remove template functions for getting op's opcode
These template functions are used in the serializer, where we can
actually directly query the opcode from the op's definition and
use that in the auto-generated serialization logic.

This removes a set of templates accounting for 319 lines from
the auto-generated inc file.

Differential Revision: https://reviews.llvm.org/D79444
2020-05-07 09:32:03 -04:00
Sjoerd Meijer 3bbc71d6c9 [LV] Fix typo in variable name. NFC. 2020-05-07 13:53:44 +01:00
Sander de Smalen 0d22076531 [SveEmitter] Add builtins for SVE2 uniform DSP operations
This patch adds builtins for:
- svqdmulh, svqdmulh_lane
- svqrdmlah, svqrdmlah_lane
- svqrdmlsh, svqrdmlsh_lane
- svqrdmulh, svqrdmulh_lane
2020-05-07 13:31:46 +01:00
Sander de Smalen 5fa0eeec6e [SveEmitter] Add more SVE2 builtins for shift operations
This patch adds builtins for:
- svqshlu
- svrshr
- svrsra
- svsli
- svsra
- svsri
2020-05-07 13:31:46 +01:00
Sander de Smalen dc2986f9dc [SveEmitter] Add builtins for SVE2 saturating shift left and addition
This patch adds builtins for:
- svqrshl
- svqshl
- svsqadd
- svuqadd
2020-05-07 13:31:46 +01:00
Sander de Smalen b32d14c30e [SveEmitter] Add builtins for SVE2 uniform DSP operations
This patch adds builtins for:
- svqadd, svhadd, svrhadd
- svqsub, svhsub, svqusbr, svhsubr
- svqabs
- svqneg
- svrecpe
- svrsqrte
2020-05-07 13:31:46 +01:00
Sander de Smalen 35de496550 [SveEmitter] Add builtins for svqdecp and svqincp
This patch adds builtins for saturating increment/decrement by svcntp,
in scalar and vector forms.
2020-05-07 13:31:46 +01:00
Sander de Smalen cac06263a4 [SveEmitter] Add builtins for svinsr 2020-05-07 13:31:46 +01:00
Simon Pilgrim b8a725274c [X86][AVX] combineSignExtendInReg - promote mask arithmetic before v4i64 canonicalization
We rely on the combine

(sext_in_reg (v4i64 a/sext (v4i32 x)), v4i1) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x, ExtraVT)))

to avoid complex v4i64 ashr codegen, but doing so prevents v4i64 comparison mask promotion, so ensure we attempt to promote before canonicalizing the (hopefully now redundant sext_in_reg).

Helps with the poor codegen in PR45808.
2020-05-07 13:16:36 +01:00
Sam Parker 751da4d596 [NFC][AArch64] Add test
Add cost model test for cast operations.
2020-05-07 13:16:03 +01:00
Calixte Denizet bec223a9bc [profile] Don't crash when forking in several threads
Summary:
When forking in several threads, the counters were written out in using the same global static variables (see GCDAProfiling.c): that leads to crashes.
So when there is a fork, the counters are resetted in the child process and they will be dumped at exit using the interprocess file locking.
When there is an exec, the counters are written out and in case of failures they're resetted.

Reviewers: jfb, vsk, marco-c, serge-sans-paille

Reviewed By: marco-c, serge-sans-paille

Subscribers: llvm-commits, serge-sans-paille, dmajor, cfe-commits, hiraditya, dexonsmith, #sanitizers, marco-c, sylvestre.ledru

Tags: #sanitizers, #clang, #llvm

Differential Revision: https://reviews.llvm.org/D78477
2020-05-07 14:13:11 +02:00
Sergej Jaskiewicz ddfe58822e Revert "[cmake] Allow std::filesystem tests in CrossWinToARMLinux.cmake"
This reverts commit 67175d8dc5.

https://reviews.llvm.org/D78200 has been reverted, so our bot is red.
Make it green by turning off std::filesystem.
2020-05-07 15:01:39 +03:00
Alexander Belyaev a6b2877f4c [MLIR] Make ParallelLoopFusion pass scan through all nested regions.
Differential Revision: https://reviews.llvm.org/D79558
2020-05-07 13:47:30 +02:00
Anna Welker 1e413a8c36 [ARM][MVE] Add support for incrementing gathers
Enables the MVEGatherScatterLowering pass to build
pre-incrementing gathers. Incrementing writeback gathers
are built when it is possible to replace the loop increment
instruction.

Differential Revision: https://reviews.llvm.org/D76786
2020-05-07 12:33:50 +01:00
Sander de Smalen 4f94e1a9f7 [SveEmitter] Add builtins for svasrd (zeroing/undef predication)
This patch adds builtins for arithmetic shift right (round towards zero)
instructions for zeroing (_z) and undef (_x) predication.
2020-05-07 12:28:18 +01:00
Sander de Smalen dbc6a07bcc [SveEmitter] Add builtins for address calculations.
This patch adds builtins for:
- svadrb, svadrh, svadrw, svadrd
2020-05-07 12:28:18 +01:00
Sander de Smalen 827c8b06d3 [SveEmitter] Add builtins for svcntp 2020-05-07 12:28:18 +01:00
Sander de Smalen ac894a5181 [SveEmitter] Add builtins for FFR manipulation
This patch adds builtins for:
- svrdffr, svrdffr_z
- svsetffr
- svwrffr
2020-05-07 12:28:18 +01:00
Sander de Smalen 91cb13f90d [SveEmitter] Add builtins for svqadd, svqsub and svdot
This patch adds builtins for saturating add/sub instructions:
- svqadd, svqadd_n
- svqsub, svqsub_n

and builtins for dot product instructions:
- svdot, svdot_lane
2020-05-07 12:28:18 +01:00
Kazushi (Jam) Marukawa 447efdb52b [VE] Minimum MC layer for VE (2/4)
Remove unnecessary EncoderMethod and DecoderMethod which cause errors in
supporting MC layer.

Differential Revision: https://reviews.llvm.org/D79544
2020-05-07 13:21:37 +02:00
Kazushi (Jam) Marukawa 6999ffcc39 [VE] Implements minimum MC layer for VE (1/4)
Summary:
Correct instruction bitfield addresses to generate machine code correctly.  Also
add some variables to represent all instructions correctly and change default
values to use registers by default.

Differential Revision: https://reviews.llvm.org/D79539
2020-05-07 13:10:36 +02:00
Lucas Prates 9d39df03a9 [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes
Summary:
Conflicting types for the same section name defined in clang section
pragmas and GNU-style section attributes were not properly captured by
Clang's Sema. The lack of diagnostics was caused by the fact the section
specification coming from attributes was handled by Sema as implicit,
even though explicitly defined by the user.

This patch enables the diagnostics for section type conflicts between
those specifications by making sure sections defined in section
attributes are correctly handled as explicit.

Reviewers: hans, rnk, javed.absar

Reviewed By: rnk

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D78573
2020-05-07 11:54:46 +01:00
Lucas Prates 0dac639f28 [Clang][Sema] Capturing section type conflicts on #pragma clang section
Summary:
Section names used in clang section pragmas were not validated against
previously defined sections, causing section type conflicts to be
ignored by Sema.

This patch enables Clang to capture these section type conflicts by
using the existing Sema's UnifySection method to validate section names
from clang section pragmas.

Reviewers: hans, rnk, javed.absar

Reviewed By: rnk

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D78572
2020-05-07 11:53:30 +01:00
Sander de Smalen 3cb8b4c193 [SveEmitter] Add builtins for SVE2 Polynomial arithmetic
This patch adds builtins for:
- sveorbt
- sveortb
- svpmul
- svpmullb, svpmullb_pair
- svpmullt, svpmullt_pair

The svpmullb and svpmullt builtins are expressed using the svpmullb_pair
and svpmullt_pair LLVM IR intrinsics, respectively.

Reviewers: SjoerdMeijer, efriedma, rengolin

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D79480
2020-05-07 11:53:04 +01:00
Sjoerd Meijer ae45b4dbe7 Recommit "[LV] Induction Variable does not remain scalar under tail-folding."
With 3 llvm regr tests fixed/updated that I had missed.
2020-05-07 11:52:20 +01:00
Adam Czachorowski 9108715321 [clangd] Fix AddUsing tweak for out-of-line functions.
Summary:
We used getEnclosingNamespaceContext(), which calls getParent() rather
than getLexicalParent(), so we would end up adding the "using" line in
places that do not affect the cursor location, or just return an error
when declaration was in another file.

Patch by Adam Czachorowski!

Reviewers: hokein

Reviewed By: hokein

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D79496
2020-05-07 12:50:04 +02:00
Kerry McLaughlin 3bcd3dd473 [CodeGen][SVE] Lowering of shift operations with scalable types
Summary:
Adds AArch64ISD nodes for:
 - SHL_PRED (logical shift left)
 - SHR_PRED (logical shift right)
 - SRA_PRED (arithmetic shift right)

Existing patterns for unpredicated left shift by immediate
have also been moved into the appropriate multiclasses
in SVEInstrFormats.td.

Reviewers: sdesmalen, efriedma, ctetreau, huihuiz, rengolin

Reviewed By: efriedma

Subscribers: huihuiz, tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D79478
2020-05-07 11:43:49 +01:00
Alex Zinenko 54c927b988 [mlir] Add a test exercising partial constant folding of affine min/max
This functionality was introduced in a87db48e6f
but only only tested indirectly though Linalg tests. Add direct tests.
2020-05-07 12:42:03 +02:00
Alex Zinenko 4809580463 [mlir] Add a test for OperationFolder
Adds a test exercising the rewriting pattern in the test dialect that calls
OperationFolder.create.
2020-05-07 12:39:24 +02:00
Alex Zinenko a87db48e6f [mlir] Support partial folding of affine.min/max
Originally, these operations were folded only if all expressions in their
affine maps could be folded to a constant expression that can be then subject
to numeric min/max computation. This introduces a more advanced version that
partially folds the affine map by lifting individual constant expression in it
even if some of the expressions remain variable. The folding can update the
operation in place to use a simpler map. Note that this is not as powerful as
canonicalization, in particular this does not remove dimensions or symbols that
became useless. This allows for better composition of Linalg tiling and
promotion transformation, where the latter can handle some canonical forms of
affine.min that the folding can now produce.

Differential Revision: https://reviews.llvm.org/D79502
2020-05-07 12:30:04 +02:00
Kadir Cetinkaya 717bef6623
[clangd] Preserve line information while build PreamblePatch
Summary: Depends on D78740.

Reviewers: sammccall

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D78743
2020-05-07 12:24:28 +02:00
LLVM GN Syncbot 92c657920e [gn build] Port e3ffe7269b 2020-05-07 10:11:03 +00:00
Jay Foad 17e13da29d [AMDGPU] Re-auto-generate test checks 2020-05-07 11:08:11 +01:00
Carl Ritson e3ffe7269b [AMDGPU] Cluster shader exports
Summary:
Add DAG scheduling mutation to cluster export instructions.
This avoids unnecessary waitcnts being added when computation
ends up interspersed with exports.

Reviewers: foad, arsenm, rampitec, nhaehnle

Reviewed By: foad

Subscribers: kzhuravl, jvesely, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D79481
2020-05-07 19:05:38 +09:00
Carl Ritson 0d4d86cbd1 [AMDGPU] Precommit test for D79481. NFC
Test shows unnecessary s_waitcnt between shader exports.
2020-05-07 19:01:51 +09:00
Wen-Heng (Jack) Chung f649aca9f3 [mlir][rocdl] Fix typo. NFC.
ROCLD -> ROCDL.

Differential Revision: https://reviews.llvm.org/D79441
2020-05-07 11:55:47 +02:00
Alex Zinenko a99f62c40a [mlir] VectorToLLVM: propagate up from replaceTransferOp
In the Vector to LLVM conversion, the `replaceTransferOp` function calls
into a type converter that may fail and suppresses the status. Change
the function to return the failure status instead, Since it is called
from a pattern, the failure can be readily propagated to the rest of
infrastructure.
2020-05-07 11:53:48 +02:00
Wen-Heng (Jack) Chung a23f190213 [mlir][vector] set alignment when lowering transfer_read and transfer_write.
When emitting masked load / store, set alignment from data layout.

Differential Revision: https://reviews.llvm.org/D79246
2020-05-07 11:44:25 +02:00
Kerry McLaughlin a31f4c52bf [SVE][CodeGen] Fix legalisation for scalable types
Summary:
This patch handles illegal scalable types when lowering IR operations,
addressing several places where the value of isScalableVector() is
ignored.

For types such as <vscale x 8 x i32>, this means splitting the
operations. In this example, we would split it into two
operations of type <vscale x 4 x i32> for the low and high halves.

In cases such as <vscale x 2 x i32>, the elements in the vector
will be promoted. In this case they will be promoted to
i64 (with a vector of type <vscale x 2 x i64>)

Reviewers: sdesmalen, efriedma, huntergr

Reviewed By: efriedma

Subscribers: david-arm, tschuett, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78812
2020-05-07 10:01:31 +01:00
Yevgeny Rouban b921543c49 SplitIndirectBrCriticalEdges: Fix Branch Probability update
Splitting critical edges for indirect branches
the SplitIndirectBrCriticalEdges() function may break branch
probabilities if target basic block happens to have unset
a probability for any of its successors. That is because in
such cases the getEdgeProbability(Target) function returns
probability 1/NumOfSuccessors and it is called after Target
was split (thus Target has a single successor). As the result
the correspondent successor of the split block gets
probability 100% but 1/NumOfSuccessors is expected (or better
be left unset).

Reviewers: yamauchi
Differential Revision: https://reviews.llvm.org/D78806
2020-05-07 15:31:44 +07:00
Sjoerd Meijer 20d67ffeae Revert "[LV] Induction Variable does not remain scalar under tail-folding."
This reverts commit 617aa64c84.

while I investigate buildbot failures.
2020-05-07 09:29:56 +01:00
Sjoerd Meijer 617aa64c84 [LV] Induction Variable does not remain scalar under tail-folding.
If tail-folding of the scalar remainder loop is applied, the primary induction
variable is splat to a vector and used by the masked load/store vector
instructions, thus the IV does not remain scalar. Because we now mark
that the IV does not remain scalar for these cases, we don't emit the vector IV
if it is not used. Thus, the vectoriser produces less dead code.

Thanks to Ayal Zaks for the direction how to fix this.

Differential Revision: https://reviews.llvm.org/D78911
2020-05-07 09:15:23 +01:00
Sam Parker 3c9b6dfa54 [NFC][ARM] Add tail predication test 2020-05-07 08:19:32 +01:00
Haojian Wu 2a3498e24f [clang-tidy] Exclude function calls in std namespace for bugprone-argument-comment.
Reviewers: gribozavr2

Subscribers: xazax.hun, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D79494
2020-05-07 09:00:49 +02:00
David Sherwood a400aa5faf [SVE] Fix getAlignmentInfo for scalable vectors
When calculating the natural alignment for scalable vectors it
is acceptable to calculate an allocation size based on the minimum
number of elements in the vector.

This code path is exercised by an existing test:

  CodeGen/AArch64/sve-intrinsics-int-arith.ll

Differential Revision: https://reviews.llvm.org/D79475
2020-05-07 07:52:37 +01:00
Craig Topper 350645594e [X86] Enable combinePMULH to match multiplies with elements larger than i32.
We're truncating so the extra bits will be discarded.
2020-05-06 23:13:59 -07:00
Craig Topper 1796cfd837 [X86] Add test cases for missed opportunity to match pmulh from multiplies with elements larger than i32.
We currently look for vXi32 sext/zext to match PMULH, but it
doesn't matter how many extra bits above i32 there are.
2020-05-06 23:13:58 -07:00
Uday Bondhugula 2affcd664e [MLIR] Fix affine fusion bug/efficiency issue / enable more fusion
The list of destination load ops while evaluating producer-consumer
fusion wasn't being maintained as a set, and as such, duplicate load ops
were being added to it. Although this is harmless correctness-wise, it's
a killer efficiency-wise and it prevents interesting/useful fusions
(including for eg. reshapes into a matmul). The reason the latter
fusions would be missed is that a slice union would be unnecessarily
needed due to the duplicate load ops on a memref added to the 'dst
loads' list. Since slice union is unimplemented for the local var case,
a single destination load op that leads to local vars (like a floordiv /
mod producing fusion), a common case, would not get fused due to an
unnecessary union being tried with itself.  (The union would actually be
the same thing but we would bail out.)

Besides the above, this would also significantly speed up fusion as all
the unnecessary slice computations / unions, checks, etc. due to the
duplicates go away.

Differential Revision: https://reviews.llvm.org/D79547
2020-05-07 10:51:34 +05:30