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Author SHA1 Message Date
Nemanja Ivanovic ec527dacca [PowerPC][NFC] Add a test case for extract and store patterns 
An upcoming patch will change the codegen for these patterns. This test case is
added now so that the patch can show the differences in codegen.

llvm-svn: 344112
 2018-10-10 04:18:35 +00:00
Dylan McKay 30ef1d60f9 [AVR] Fix the 'call.ll' CodeGen test 
Commit r343851 changed the format of the generated instructions.

An unnecessary load has been removed. Previously, a value would be moved
from r24 into a temporary register just to be copied into r30 before the
indirect call. Now, codegen immediately loads r24 into r30, saving a
MOVW instruction.

llvm-svn: 344111
 2018-10-10 03:21:42 +00:00
James Y Knight 892b09ba11 ExprConstant: Make __builtin_object_size use EM_IgnoreSideEffects. 
And, since EM_OffsetFold is now unused, remove it.

While builtin_object_size intends to ignore the presence of
side-effects in its argument, the EM_OffsetFold mode was NOT
configured to ignore side-effects. Rather it was effectively identical
to EM_ConstantFold -- its explanatory comment
notwithstanding.

However, currently, keepEvaluatingAfterSideEffect() is not always
honored -- sometimes evaluation continues despite it returning
false. Therefore, since the b_o_s code was only checking the return
value from evaluation, and not additionally checking the
HasSideEffects flag, side-effects _were_ in many cases actually being
ignored.

This change is a prerequisite cleanup towards fixing that issue.

Differential Revision: https://reviews.llvm.org/D52924

llvm-svn: 344110
 2018-10-10 02:53:43 +00:00
QingShan Zhang bc1586352e [PowerPC] Fix the assert of ISD::SIGN_EXTEND_INREG when type is v2i16 and v2i8 
For ISD::SIGN_EXTEND_INREG operation of v2i16 and v2i8 types will cause assert because they are registered as custom operation. 
So that the type legalization phase will enter the custom hook, which do not handle ISD::SIGN_EXTEND_INREG operation and fall throw into unreachable assert.

Patch By: wuzish (Zixuan Wu)
Differential Revision: https://reviews.llvm.org/D52449

llvm-svn: 344109
 2018-10-10 02:33:48 +00:00
George Burgess IV d98d505c0d [Analysis] Make LocationSize pretty-printing more descriptive 
This is the third patch in a series intended to make
https://reviews.llvm.org/D44748 more easily reviewable. Please see that
patch for more context. The second being r344013.

The intent is to make the output of printing a LocationSize more
precise. The main motivation for this is that we plan to add a bit to
distinguish whether a given LocationSize is an upper-bound or is
precise; making that information available in pretty-printing is nice.

llvm-svn: 344108
 2018-10-10 01:35:22 +00:00
Thomas Lively 108e98ec32 [WebAssembly] Fix fneg lowering 
Summary:
Subtraction from zero and floating point negation do not have the same
semantics, so fix lowering.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D52948

llvm-svn: 344107
 2018-10-10 01:09:09 +00:00
Heejin Ahn 5d900954bd [WebAssembly] Improve comments for SIMD instruction definitions 
llvm-svn: 344106
 2018-10-10 01:04:02 +00:00
George Karpenkov d2f6590285 [libFuzzer] Disable value profiling tests on ARM 
Some seem fragile, some fail, and some just take a really long time to run.
It does not seem to make sense to support some subset of value profiling tests.

Differential Revision: https://reviews.llvm.org/D53047

llvm-svn: 344105
 2018-10-10 00:58:03 +00:00
George Karpenkov f28523bb3f [libFuzzer] Generalize the code for getting the previous offset for different architectures 
Without this change, tests in coverage.test and dump_coverage.test are
failing on non-x86_64 platforms.
The diff is copied from sanitizer_common library, an alternative would
be to link it together with libFuzzer.

Differential Revision: https://reviews.llvm.org/D53040

llvm-svn: 344104
 2018-10-10 00:57:44 +00:00
George Karpenkov ea13613572 [sancov] Generalize the code to get the previous instruction to multiple architectures 
sancov subtracts one from the address to get the previous instruction,
which makes sense on x86_64, but not on other platforms.
This change ensures that the offset is correct for different platforms.
The logic for computing the offset is copied from sanitizer_common.

Differential Revision: https://reviews.llvm.org/D53039

llvm-svn: 344103
 2018-10-10 00:57:24 +00:00
Jim Ingham 285ae0c07b Add "var" and "vo" aliases for "frame variable" and "frame variable -O". 
Differential Revision: https://reviews.llvm.org/D53010

llvm-svn: 344102
 2018-10-10 00:51:30 +00:00
Erik Pilkington abbc51e5c3 [Basic] Split out -Wimplicit-int-conversion and -Wimplicit-float-conversion from -Wconversion 
These two diagnostics are noisy, so its reasonable for users to opt-out of them
when -Wconversion is enabled.

rdar://45058981

Differential revision: https://reviews.llvm.org/D53048

llvm-svn: 344101
 2018-10-10 00:40:50 +00:00
Ed Maste 8bddfdd59c clang: Allow ifunc resolvers to accept arguments 
When ifunc support was added to Clang (r265917) it did not allow
resolvers to take function arguments.  This was based on GCC's
documentation, which states resolvers return a pointer and take no
arguments.

However, GCC actually allows resolvers to take arguments, and glibc (on
non-x86 platforms) and FreeBSD (on x86 and arm64) pass some CPU
identification information as arguments to ifunc resolvers.  I believe
GCC's documentation is simply incorrect / out-of-date.

FreeBSD already removed the prohibition in their in-tree Clang copy.

Differential Revision:	https://reviews.llvm.org/D52703

llvm-svn: 344100
 2018-10-10 00:34:17 +00:00
Fangrui Song 2043a58abe Adapt OptTable::PrintHelp change in D51009 
Summary: Before, OptTable::PrintHelp append "[options] <inputs>" to its parameter `Help`. It is more flexible to change its semantic to `Usage` and let user customize the usage line.

Reviewers: rupprecht, ruiu, espindola

Reviewed By: rupprecht

Subscribers: emaste, sbc100, arichardson, aheejin, llvm-commits

Differential Revision: https://reviews.llvm.org/D53054

llvm-svn: 344099
 2018-10-10 00:15:36 +00:00
Fangrui Song d002823830 [Driver][cc1][cc1as] Call OptTable::PrintHelp with explicit " [options] file..." 
Summary: This is to accommodate a change in llvm/lib/Option/OptTable.cpp D51009

Reviewers: rupprecht, alexshap, jhenderson

Reviewed By: rupprecht

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D51109

llvm-svn: 344098
 2018-10-10 00:15:33 +00:00
Fangrui Song 88478bbc60 [opt] Change the parameter of OptTable::PrintHelp from Name to Usage and don't append "[options] <inputs>" 
Summary:
Before, "[options] <inputs>" is unconditionally appended to the `Name` parameter. It is more flexible to change its semantic to `Usage` and let user customize the usage line.

% llvm-objcopy
...
USAGE: llvm-objcopy <input> [ <output> ] [options] <inputs>

With this patch:

% llvm-objcopy
...
USAGE: llvm-objcopy input [output]

Reviewers: rupprecht, alexshap, jhenderson

Reviewed By: rupprecht

Subscribers: jakehehrlich, mehdi_amini, steven_wu, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D51009

llvm-svn: 344097
 2018-10-10 00:15:31 +00:00
Aaron Puchert 7f208f02db Annotate scoped_lock as with scoped_lockable attribute 
Summary:
Scoped capabilities need to be annotated as such, otherwise the thread
safety analysis won't work as intended.

Fixes PR39234.

Reviewers: ldionne

Reviewed By: ldionne

Subscribers: christof, libcxx-commits

Differential Revision: https://reviews.llvm.org/D53049

llvm-svn: 344096
 2018-10-09 23:42:29 +00:00
Zachary Turner e5f47bbeac [git-llvm] Fix some issues surrouding EOL conversion on Windows. 
This patch fixes three issues.

The first is that we didn't consider files which are explicitly
set to eolstyle CRLF in the repo, and there are a handful of
these.

Second is that dos2unix doesn't have a -q option in GnuWin32,
so this codepath wasn't working properly.

Finally with newer versions of Python (or newer versions of Git,
or some combination of the two) patches can't be applied when
we treat stdin as text, because Python silently undoes all the
work we did to convert the newlines to LF using dos2unix by
using universal_newlines=True and then converting them *back*
to CRLF.  So we need to add a way to force stdin to be treated
as binary, and use it when LF-newlines are required.

Differential Revision: https://reviews.llvm.org/D51444

llvm-svn: 344095
 2018-10-09 23:42:28 +00:00
Thomas Lively 409f5840a7 [WebAssembly] Handle V128 register class in explicit locals pass 
Summary:
Also add tests to catch crashes in passes that are not normally run in
tests.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D52959

llvm-svn: 344094
 2018-10-09 23:33:16 +00:00
Nemanja Ivanovic 72d4866e57 [DAGCombiner] Expand combining of FP logical ops to sign-setting FP ops 
We already do the following combines:
(bitcast int (and (bitcast fp X to int), 0x7fff...) to fp) -> fabs X
(bitcast int (xor (bitcast fp X to int), 0x8000...) to fp) -> fneg X

When the target has "bit preserving fp logic". This patch just extends it
to also combine:
(bitcast int (or (bitcast fp X to int), 0x8000...) to fp) -> fneg (fabs X)

As some targets have fnabs and even those that don't can efficiently lower
both the fabs and the fneg.

Differential revision: https://reviews.llvm.org/D44548

llvm-svn: 344093
 2018-10-09 23:20:11 +00:00
Rong Xu 5c7bf1a756 [X86] Fix sanitizer bot failure from 344085 
Fix the memory issue exposed by sanitizer.

llvm-svn: 344092
 2018-10-09 23:10:56 +00:00
Nemanja Ivanovic c62dfe512e [PowerPC][NFC] Commit nabs test case in preparation for committing D44548 
This just adds the test case so that the different code gen is clearly visible
when the DAG Combine lands.

llvm-svn: 344091
 2018-10-09 23:02:53 +00:00
Rui Ueyama 71cdbb7fe6 Merge two overloaded functions into one function. NFC. 
llvm-svn: 344089
 2018-10-09 22:44:53 +00:00
Rui Ueyama e65cb4889e Return early. NFC. 
llvm-svn: 344088
 2018-10-09 22:44:42 +00:00
Justin Bogner 90fde0e06f [LV] Move test for r343954 into x86 subdirectory 
This test uses an x86 triple, so it needs to be in the x86 specific
test directory.

llvm-svn: 344087
 2018-10-09 22:40:04 +00:00
Heejin Ahn d9a6de3c38 [WebAssembly] Improve readability of SIMD instructions (NFC) 
Summary:
- Categorize instructions into the categories as in the SIMD spec
- Move SIMD-related definition to WebAssemblyInstrSIMD.td
- Put definition and use of patterns together
- Add newlines here and there

Reviewers: tlively

Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D53045

llvm-svn: 344086
 2018-10-09 22:23:39 +00:00
Rong Xu 3d2efdfdea Recommit r343993: [X86] condition branches folding for three-way conditional codes 
Fix the memory issue exposed by sanitizer.

llvm-svn: 344085
 2018-10-09 22:03:40 +00:00
Cameron McInally bea5967e8c [FPEnv] PatternMatcher support for checking FNEG ignoring signed zeros 
https://reviews.llvm.org/D52934

llvm-svn: 344084
 2018-10-09 21:48:00 +00:00
Rui Ueyama 2b53b4bea6 Attempt to fix ubsan. 
Previously, we cast a pointer to Elf{32,64}_Chdr like this

  auto *Hdr = reinterpret_cast<const ELF64_Chdr>(Ptr);

and read from its members like this

  read32(&Hdr->ch_size);

I was thinking that this does not violate alignment requirement,
since &Hdr->ch_size doesn't really access memory, but seems like
it is a violation in terms of C++ spec (?)

In this patch, I use a different struct that allows unaligned access.

llvm-svn: 344083
 2018-10-09 21:41:53 +00:00
Sanjay Patel e9ca7ea3e5 [InstCombine] reverse 'trunc X to <N x i1>' canonicalization 
icmp ne (and X, 1), 0 --> trunc X to N x i1

Ideally, we'd do the same for scalars, but there will likely be 
regressions unless we add more trunc folds as we're doing here 
for vectors.

The motivating vector case is from PR37549:
https://bugs.llvm.org/show_bug.cgi?id=37549

define <4 x float> @bitwise_select(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %w) {
  %c = fcmp ole <4 x float> %x, %y
  %s = sext <4 x i1> %c to <4 x i32>
  %s1 = shufflevector <4 x i32> %s, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
  %s2 = shufflevector <4 x i32> %s, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
  %cond = or <4 x i32> %s1, %s2
  %condtr = trunc <4 x i32> %cond to <4 x i1>
  %r = select <4 x i1> %condtr, <4 x float> %z, <4 x float> %w
  ret <4 x float> %r
}

Here's a sampling of the vector codegen for that case using 
mask+icmp (current behavior) vs. trunc (with this patch):

AVX before:

vcmpleps	%xmm1, %xmm0, %xmm0
vpermilps	$80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
vpermilps	$250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
vorps	%xmm0, %xmm1, %xmm0
vandps	LCPI0_0(%rip), %xmm0, %xmm0
vxorps	%xmm1, %xmm1, %xmm1
vpcmpeqd	%xmm1, %xmm0, %xmm0
vblendvps	%xmm0, %xmm3, %xmm2, %xmm0

AVX after:

vcmpleps	%xmm1, %xmm0, %xmm0
vpermilps	$80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
vpermilps	$250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
vorps	%xmm0, %xmm1, %xmm0
vblendvps	%xmm0, %xmm2, %xmm3, %xmm0

AVX512f before:

vcmpleps	%xmm1, %xmm0, %xmm0
vpermilps	$80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
vpermilps	$250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
vorps	%xmm0, %xmm1, %xmm0
vpbroadcastd	LCPI0_0(%rip), %xmm1 ## xmm1 = [1,1,1,1]
vptestnmd	%zmm1, %zmm0, %k1
vblendmps	%zmm3, %zmm2, %zmm0 {%k1}

AVX512f after:

vcmpleps	%xmm1, %xmm0, %xmm0
vpermilps	$80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
vpermilps	$250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
vorps	%xmm0, %xmm1, %xmm0
vpslld	$31, %xmm0, %xmm0
vptestmd	%zmm0, %zmm0, %k1
vblendmps	%zmm2, %zmm3, %zmm0 {%k1}

AArch64 before:

fcmge	v0.4s, v1.4s, v0.4s
zip1	v1.4s, v0.4s, v0.4s
zip2	v0.4s, v0.4s, v0.4s
orr	v0.16b, v1.16b, v0.16b
movi	v1.4s, #1
and	v0.16b, v0.16b, v1.16b
cmeq	v0.4s, v0.4s, #0
bsl	v0.16b, v3.16b, v2.16b

AArch64 after:

fcmge	v0.4s, v1.4s, v0.4s
zip1	v1.4s, v0.4s, v0.4s
zip2	v0.4s, v0.4s, v0.4s
orr	v0.16b, v1.16b, v0.16b
bsl	v0.16b, v2.16b, v3.16b

PowerPC-le before:

xvcmpgesp 34, 35, 34
vspltisw 0, 1
vmrglw 3, 2, 2
vmrghw 2, 2, 2
xxlor 0, 35, 34
xxlxor 35, 35, 35
xxland 34, 0, 32
vcmpequw 2, 2, 3
xxsel 34, 36, 37, 34

PowerPC-le after:

xvcmpgesp 34, 35, 34
vmrglw 3, 2, 2
vmrghw 2, 2, 2
xxlor 0, 35, 34
xxsel 34, 37, 36, 0

Differential Revision: https://reviews.llvm.org/D52747

llvm-svn: 344082
 2018-10-09 21:26:01 +00:00
Zachary Turner 5989281cf3 [PDB] Fix another bug in globals stream name lookup. 
When we're on the last bucket the computation is tricky.
We were failing when the last bucket contained multiple
matches.  Added a new test for this.

llvm-svn: 344081
 2018-10-09 21:19:03 +00:00
Jake Ehrlich 5e49846ca6 [llvm-objcopy] Make -S an alias for --strip-all 
-S should be an alias for --strip-all not --strip-all-gnu

llvm-svn: 344080
 2018-10-09 21:14:09 +00:00
Adrian Prantl 8aa69e9927 llvm-dwarfdump: Extend --name to also search DW_AT_linkage_name. 
rdar://problem/45132695

llvm-svn: 344079
 2018-10-09 20:51:33 +00:00
Lang Hames bf6603e918 [ORC] Promote and rename private symbols inside the CompileOnDemand layer, 
rather than require them to have been promoted before being passed in.

Dropping this precondition is better for layer composition (CompileOnDemandLayer
was the only one that placed pre-conditions on the modules that could be added).
It also means that the promoted private symbols do not show up in the target
JITDylib's symbol table. Instead, they are confined to the hidden implementation
dylib that contains the actual definitions.

For the 403.gcc testcase this cut down the public symbol table size from ~15,000
symbols to ~4000, substantially reducing symbol dependence tracking costs.

llvm-svn: 344078
 2018-10-09 20:44:32 +00:00
Nemanja Ivanovic 87873d04c3 [PowerPC] Implement hasBitPreservingFPLogic for types that can be supported 
This is the PPC-specific non-controversial part of
https://reviews.llvm.org/D44548 that simply enables this combine for PPC
since PPC has these instructions.
This commit will allow the target-independent portion to be truly target
independent.

llvm-svn: 344077
 2018-10-09 20:35:15 +00:00
Rui Ueyama e3ccd28660 Calculate an offset only once. NFC. 
llvm-svn: 344076
 2018-10-09 20:29:24 +00:00
Rui Ueyama fbc629702d Remove redundant `Symtab->`. 
`SymbolTable` is a singleton class and is a global variable for the
unique instance, so we can always refer the symtab by `Symtab->`.
However, we don't need to use the global varaible from member functions
of SymbolTable class.

llvm-svn: 344075
 2018-10-09 20:22:18 +00:00
Rui Ueyama 714abece2b Simplify. NFC. 
llvm-svn: 344074
 2018-10-09 20:16:16 +00:00
Matt Davis 839ec9d9a4 [compiler-rt] Remove unused formal parameters from allocateOneNode. NFC. 
Summary: This is just a minor cleanup to the allocateOneNode interface.  The formals are no-longer used, so I just removed them.

Reviewers: davidxl, void

Reviewed By: davidxl

Subscribers: dberris, llvm-commits

Differential Revision: https://reviews.llvm.org/D52509

llvm-svn: 344073
 2018-10-09 20:10:28 +00:00
Rui Ueyama 659cff37d6 Remove a use of template to make code less abstracted. 
Sometimes, code that is a bit longer but doesn't use template is
easier to understand than code that uses template.

llvm-svn: 344072
 2018-10-09 19:54:32 +00:00
Craig Topper f6d8400869 [X86] When lowering unsigned v2i64 setcc without SSE42, flip the sign bits in the v2i64 type then bitcast to v4i32. 
This may give slightly better opportunities for DAG combine to simplify with the operations before the setcc. It also matches the type the xors will eventually be promoted to anyway so it saves a legalization step.

Almost all of the test changes are because our constant pool entry is now v2i64 instead of v4i32 on 64-bit targets. On 32-bit targets getConstant should be emitting a v4i32 build_vector and a v4i32->v2i64 bitcast.

There are a couple test cases where it appears we now combine a bitwise not with one of these xors which caused a new constant vector to be generated. This prevented a constant pool entry from being shared. But if that's an issue we're concerned about, it seems we need to address it another way that just relying a bitcast to hide it.

This came about from experiments I've been trying with pushing the promotion of and/or/xor to vXi64 later than LegalizeVectorOps where it is today. We run LegalizeVectorOps in a bottom up order. So the and/or/xor are promoted before their users are legalized. The bitcasts added for the promotion act as a barrier to computeKnownBits if we try to use it during vector legalization of a later operation. So by moving the promotion out we can hopefully get better results from computeKnownBits/computeNumSignBits like in LowerTruncate on AVX512. I've also looked at running LegalizeVectorOps in a top down order like LegalizeDAG, but thats showing some other issues.

llvm-svn: 344071
 2018-10-09 19:05:50 +00:00
Richard Smith e54d9525ad PR39231: fix null dereference when diagnosing deduction failure due to 
conflicting values for a non-type pack.

llvm-svn: 344070
 2018-10-09 18:49:22 +00:00
Sam Clegg 81abca32fb [SLPVectorizer] Check that lowered type is floating point before calling isFabsFree 
In the case of soft-fp (e.g. fp128 under wasm) the result of
getTypeLegalizationCost() can be an integer type even if the input is
floating point (See LegalizeTypeAction::TypeSoftenFloat).

Before calling isFabsFree() (which asserts if given a non-fp
type) we need to check that that result is fp.  This is safe since in
fabs is certainly not free in the soft-fp case.

Fixes PR39168

Differential Revision: https://reviews.llvm.org/D52899

llvm-svn: 344069
 2018-10-09 18:41:17 +00:00
Wolfgang Pieb a9ea9c5034 [DWARF] Make llvm-dwarfdump display the .debug_loc.dwo section. Fixes PR38991. 
Reviewer: dblaikie

Differential Revision: https://reviews.llvm.org/D52444

llvm-svn: 344068
 2018-10-09 18:38:55 +00:00
Sanjay Patel 1238e6c207 [InstCombine] add tests for extract subvector shuffles; NFC 
llvm-svn: 344067
 2018-10-09 18:37:20 +00:00
Zachary Turner 2be11c0260 Fix lld test. 
I removed this output from the dumper because it was non-portable,
but I didn't update the test which checked the output.

llvm-svn: 344066
 2018-10-09 18:35:06 +00:00
Nico Weber e1b9331d29 lld-link: attempt to fix tests on Windows after r344061. 
llvm-svn: 344065
 2018-10-09 18:19:09 +00:00
Adrian Prantl d969abde1b Add missing space 
llvm-svn: 344064
 2018-10-09 18:12:04 +00:00
Zachary Turner b7dd12b7a8 [PDB] Fix failure on big endian machines. 
We changed an ArrayRef<uint8_t> to an ArrayRef<uint32_t>, but
it needs to be an ArrayRef<support::ulittle32_t>.

We also change ArrayRef<> to FixedStreamArray<>.  Technically
an ArrayRef<> will work, but it can cause a copy in the underlying
implementation if the memory is not contiguous, and there's no
reason not to use a FixedStreamArray<>.

Thanks to nemanjai@ and thakis@ for helping me track this down
and confirm the fix.

llvm-svn: 344063
 2018-10-09 17:58:51 +00:00
Rui Ueyama c2921f002e Add an entry to the release notes. 
llvm-svn: 344062
 2018-10-09 17:53:33 +00:00