Commit Graph

50799 Commits

Author SHA1 Message Date
Sebastian Pop ec2fb226d8 rename LLVM_HOSTTRIPLE into LLVM_DEFAULT_TARGET_TRIPLE
llvm-svn: 143501
2011-11-01 21:31:44 +00:00
Eli Friedman 3f5eccbe7a Teach the x86 backend a couple tricks for dealing with v16i8 sra by a constant splat value. Fixes PR11289.
llvm-svn: 143498
2011-11-01 21:18:39 +00:00
Jim Grosbach 107c14391f Ignore MachO symbol flags in the upper nibble of n_desc.
They don't impact the MCJIT rtdyld, so just mask them off for now.

llvm-svn: 143472
2011-11-01 18:10:23 +00:00
Richard Osborne 56ce0932db Don't fold negative offsets into cp / dp accesses to avoid relocation errors.
This can happen if the address + addend is less than the start of the cp / dp.

llvm-svn: 143459
2011-11-01 11:31:53 +00:00
Eli Friedman 39df70c33a Remove a couple unused methods. PR11201.
llvm-svn: 143452
2011-11-01 05:11:01 +00:00
Eli Friedman a49b828f8f Make sure we use the right insertion point when instcombine replaces a PHI with another instruction. (Specifically, don't insert an arbitrary instruction before a PHI.) Fixes PR11275.
llvm-svn: 143437
2011-11-01 04:49:29 +00:00
Jim Grosbach fb2f1d61f4 ARM VLD/VST assembly parsing for symbolic address operands.
llvm-svn: 143413
2011-11-01 01:24:45 +00:00
Jakob Stoklund Olesen 559d4dcc16 Update split candidate correctly when interference cache is full.
No test case, spotted by inspection.

llvm-svn: 143407
2011-11-01 00:02:31 +00:00
Eli Friedman d28ddbff8d Add support for new atomics to cpp backend. Misc other fixes while I'm here. PR11268.
llvm-svn: 143406
2011-10-31 23:59:22 +00:00
Devang Patel f4af8c65aa Add utility to append a function to the list of global constructors.
Patch by Kostya Serebryany.

llvm-svn: 143405
2011-10-31 23:58:51 +00:00
Jim Grosbach 05df460269 ARM VST1 w/ writeback assembly parsing and encoding.
llvm-svn: 143369
2011-10-31 21:50:31 +00:00
Nadav Rotem f310361a7d Cleanup. Document. Make sure that this build_vector optimization only runs before the op legalizer and that the used type is legal.
llvm-svn: 143358
2011-10-31 20:08:25 +00:00
Jim Grosbach e4c8e692f2 ARM writeback vs. stride operands for VST/VLD.
The _fixed variants have a writeback operand, but not a stride operand.
Split the conditional flag to distinguish the cases.

llvm-svn: 143356
2011-10-31 19:11:23 +00:00
Owen Anderson 40703f4252 More not-crashing NEON disassembly updates for the vld refactoring.
llvm-svn: 143351
2011-10-31 17:17:32 +00:00
Craig Topper cfcfdf2aab Begin adding AVX2 instructions. No selection support yet other than intrinsics.
llvm-svn: 143331
2011-10-31 02:15:10 +00:00
Nick Lewycky aab6169ef6 Switch new .file directive emission off by default, change llc's flag for it to
-enable-dwarf-directory.

llvm-svn: 143326
2011-10-31 01:06:02 +00:00
Craig Topper 228d9131aa Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag.
llvm-svn: 143319
2011-10-30 19:57:21 +00:00
Duncan Sands 3d5692a475 Reapply commit 143214 with a fix: m_ICmp doesn't match conditions
with the given predicate, it matches any condition and returns the
predicate - d'oh!  Original commit message:
The expression icmp eq (select (icmp eq x, 0), 1, x), 0 folds to false.
Spotted by my super-optimizer in 186.crafty and 450.soplex.  We really
need a proper infrastructure for handling generalizations of this kind
of thing (which occur a lot), however this case is so simple that I decided
to go ahead and implement it directly.

llvm-svn: 143318
2011-10-30 19:56:36 +00:00
Peter Collingbourne 8bb15d8276 Teach ModuleLinker::getLinkageResult about materialisable functions
llvm-svn: 143316
2011-10-30 17:46:34 +00:00
Benjamin Kramer 7402ee6ec2 X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift and zero out the bits where zeros should've been shifted in.
llvm-svn: 143315
2011-10-30 17:31:21 +00:00
Nadav Rotem c602b2c4de Fix pr11266.
On x86: (shl V, 1) -> add V,V

Hardware support for vector-shift is sparse and in many cases we scalarize the
result. Additionally, on sandybridge padd is faster than shl.

llvm-svn: 143311
2011-10-30 13:24:22 +00:00
Benjamin Kramer a4eba41b7a Silence compiler warning.
llvm-svn: 143308
2011-10-30 08:39:55 +00:00
Nadav Rotem bf6568b5d6 Add a new DAGCombine optimization for BUILD_VECTOR.
If all of the inputs are zero/any_extended, create a new simple BV
which can be further optimized by other BV optimizations.

llvm-svn: 143297
2011-10-29 21:23:04 +00:00
Benjamin Kramer ff91dd9f07 PPC: Disable moves for all CR subregisters.
Should fix assertion failures on ppc buildbots.

llvm-svn: 143290
2011-10-29 19:43:38 +00:00
Benjamin Kramer 594ee77964 SimplifyLibCalls: Use IRBuilder.CreateGlobalString when creating a string for printf->puts, which correctly sets the unnamed_addr bit on the resulting GlobalVariable.
Fixes PR11264.

llvm-svn: 143289
2011-10-29 19:43:31 +00:00
Eli Friedman 3af3c046a9 Revert r143214; it's breaking a bunch of stuff.
llvm-svn: 143265
2011-10-29 00:56:07 +00:00
Dan Gohman 9b9c970148 Revert r143206, as there are still some failing tests.
llvm-svn: 143262
2011-10-29 00:41:52 +00:00
Jim Grosbach 3d785edee2 ARM mode 'mov' to 'mvn' assembler alias.
llvm-svn: 143237
2011-10-28 22:50:54 +00:00
Jim Grosbach b009a872d7 Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
  mov r2, #-3
becomes
  mvn r2, #2

rdar://10349224

llvm-svn: 143235
2011-10-28 22:36:30 +00:00
Owen Anderson 409b694c6c Specify that the high bit of the alignment field is fixed to 0 on these instructions.
llvm-svn: 143220
2011-10-28 20:43:24 +00:00
Akira Hatanaka 104b7e3f2c Make changes necessary in LowerFormalArguments to support Mips64.
llvm-svn: 143218
2011-10-28 19:55:48 +00:00
Akira Hatanaka b20a325baf Make changes necessary in LowerCall to support Mips64.
llvm-svn: 143217
2011-10-28 19:49:00 +00:00
Duncan Sands 280bc553b3 The expression icmp eq (select (icmp eq x, 0), 1, x), 0 folds to false.
Spotted by my super-optimizer in 186.crafty and 450.soplex.  We really
need a proper infrastructure for handling generalizations of this kind
of thing (which occur a lot), however this case is so simple that I decided
to go ahead and implement it directly.

llvm-svn: 143214
2011-10-28 19:01:20 +00:00
Akira Hatanaka 7989f15d37 Add variable IsO32 to MipsTargetLowering.
llvm-svn: 143213
2011-10-28 18:47:24 +00:00
Duncan Sands 985ba6386d A shift of a power of two is a power of two or zero.
For completeness - not spotted in the wild.

llvm-svn: 143211
2011-10-28 18:30:05 +00:00
Duncan Sands 92af0a8a7f Fold icmp ugt (udiv X, Y), X to false. Spotted by my super-optimizer
in 186.crafty.

llvm-svn: 143209
2011-10-28 18:17:44 +00:00
Owen Anderson dde461c8b1 Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
llvm-svn: 143208
2011-10-28 18:02:13 +00:00
Dan Gohman 73057ad24f Reapply r143177 and r143179 (reverting r143188), with scheduler
fixes: Use a separate register, instead of SP, as the
calling-convention resource, to avoid spurious conflicts with
actual uses of SP. Also, fix unscheduling of calling sequences,
which can be triggered by pseudo-two-address dependencies.

llvm-svn: 143206
2011-10-28 17:55:38 +00:00
Owen Anderson effd094438 Revert r143202.
llvm-svn: 143203
2011-10-28 17:38:30 +00:00
Owen Anderson df53d4fd61 Specify fixed bits on CPS instructions to enable roundtripping.
llvm-svn: 143202
2011-10-28 17:29:39 +00:00
Jim Grosbach 7a49575d7f Thumb2 ADD/SUB instructions encoding selection outside IT block.
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).

rdar://10348481

llvm-svn: 143201
2011-10-28 16:57:07 +00:00
NAKAMURA Takumi 29ccdd8207 Dwarf: [PR11022] Fix emitting DW_AT_const_value(>i64), to be host-endian-neutral.
Don't assume APInt::getRawData() would hold target-aware endianness nor host-compliant endianness. rawdata[0] holds most lower i64, even on big endian host.

FIXME: Add a testcase for big endian target.

FIXME: Ditto on CompileUnit::addConstantFPValue() ?
llvm-svn: 143194
2011-10-28 14:12:22 +00:00
Benjamin Kramer 47c3f2d625 Use BranchProbability compare operators.
llvm-svn: 143190
2011-10-28 11:14:31 +00:00
Duncan Sands 225a7037d6 Speculatively disable Dan's commits 143177 and 143179 to see if
it fixes the dragonegg self-host (it looks like gcc is miscompiled).
Original commit messages:
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.

Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.

Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.

Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.

This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.

Delete #if 0 code accidentally left in.

llvm-svn: 143188
2011-10-28 09:55:57 +00:00
Nick Lewycky cc64ae140d Always use the string pool, even when it makes the .o larger. This may help
tools that read the debug info in the .o files by making the DIE sizes more
consistent.

llvm-svn: 143186
2011-10-28 05:29:47 +00:00
Andrew Trick effdca9441 LFTR should avoid a type mismatch with null pointer IVs.
Fixes rdar://10359193 Indvar LinearFunctionTestReplace assertion

llvm-svn: 143183
2011-10-28 03:45:11 +00:00
Dan Gohman 0e8d1454b1 Delete #if 0 code accidentally left in.
llvm-svn: 143179
2011-10-28 01:41:21 +00:00
Dan Gohman 4db3f7dd83 Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.

Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.

Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.

Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.

This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.

llvm-svn: 143177
2011-10-28 01:29:32 +00:00
Jim Grosbach 080a499ee0 ARM Allow 'q' registers in VLD/VST vector lists.
Just treat it as if the constituent D registers where specified.

rdar://10348896

llvm-svn: 143167
2011-10-28 00:06:50 +00:00
Dan Gohman 4c9fca99c9 Remove the Alpha backend.
llvm-svn: 143164
2011-10-27 22:56:32 +00:00