7 Commits

Author	SHA1	Message	Date
Simon Pilgrim	84cbd8e750	[X86][SSE] Add extra (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) test case ... We should be able to handle the case where some c1+c2 elements exceed max shift and some don't by performing a clamp after the sum llvm-svn: 308724	2017-07-21 10:22:49 +00:00
Simon Pilgrim	7ff0e49d8c	[DAGCombiner] Match ISD::SRA non-uniform constant vectors patterns using predicates. ... Use predicate matchers introduced in D35492 to match more ISD::SRA constant folds llvm-svn: 308600	2017-07-20 10:43:05 +00:00
Sanjay Patel	a0d8a278a7	[x86] use a single shufps when it can save instructions ... This is a tiny patch with a big pile of test changes. This partially fixes PR27885: https://llvm.org/bugs/show_bug.cgi?id=27885 My motivating case looks like this: - vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,2] - vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] - vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] + vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] And this happens several times in the diffs. For chips with domain-crossing penalties, the instruction count and size reduction should usually overcome any potential domain-crossing penalty due to using an FP op in a sequence of int ops. For chips such as recent Intel big cores and Atom, there is no domain-crossing penalty for shufps, so using shufps is a pure win. So the test case diffs all appear to be improvements except one test in vector-shuffle-combining.ll where we miss an opportunity to use a shift to generate zero elements and one test in combine-sra.ll where multiple uses prevent the expected shuffle combining. Differential Revision: https://reviews.llvm.org/D27692 llvm-svn: 289837	2016-12-15 18:03:38 +00:00
Sanjay Patel	9ca028c2d6	[DAG] enhance computeKnownBits to handle SRL/SRA with vector splat constant ... llvm-svn: 284953	2016-10-23 23:13:31 +00:00
Sanjay Patel	5b7767f646	[x86] add test for missing vector SRA combine via computeKnownBits ... llvm-svn: 284896	2016-10-21 23:02:31 +00:00
Simon Pilgrim	b2ca2505cc	[DAGCombine] Generalize distributeTruncateThroughAnd to work with any non-opaque constant or constant vector ... llvm-svn: 284574	2016-10-19 08:57:37 +00:00
Simon Pilgrim	a2778b2591	[X86][SSE] Added vector ashr combine tests ... This doesn't cover all combines in DAGCombiner::visitSRA yet, but identifies several cases where we fail to combine vectors (or non-splatted) vectors llvm-svn: 284498	2016-10-18 17:31:07 +00:00