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27797 Commits

Author SHA1 Message Date
Bradley Smith eb4ca04db2 [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0. 
llvm-svn: 205882
 2014-04-09 14:43:35 +00:00
Bradley Smith db7b9b17eb [ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have the top bit of their immediate clear. 
llvm-svn: 205881
 2014-04-09 14:43:31 +00:00
Bradley Smith 60e7667886 [ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero. 
llvm-svn: 205880
 2014-04-09 14:43:27 +00:00
Bradley Smith 7525b47208 [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1. 
llvm-svn: 205879
 2014-04-09 14:43:24 +00:00
Bradley Smith 0243aa33fa [ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu. 
llvm-svn: 205878
 2014-04-09 14:43:20 +00:00
Bradley Smith 8f906a3c5f [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64. 
llvm-svn: 205877
 2014-04-09 14:43:15 +00:00
Bradley Smith 9f29b726d5 [ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases. 
llvm-svn: 205876
 2014-04-09 14:43:11 +00:00
Bradley Smith e8b4166acc [ARM64] Rework system register parsing to overcome SPSel clash in MSR variants. 
llvm-svn: 205875
 2014-04-09 14:43:06 +00:00
Bradley Smith bc35b1f138 [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value. 
llvm-svn: 205874
 2014-04-09 14:43:01 +00:00
Bradley Smith 4925be9b56 [ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during disassembly. 
llvm-svn: 205873
 2014-04-09 14:42:56 +00:00
Bradley Smith 3339427e2a [ARM64] Remove PrefetchOp and use ARM64PRFM instead. 
llvm-svn: 205872
 2014-04-09 14:42:53 +00:00
Bradley Smith 16478c4ccf [ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway. 
llvm-svn: 205871
 2014-04-09 14:42:49 +00:00
Bradley Smith 3db2a85853 [ARM64] Remove ARM64SYS. 
llvm-svn: 205870
 2014-04-09 14:42:45 +00:00
Bradley Smith fb90df563f [ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS. 
llvm-svn: 205869
 2014-04-09 14:42:42 +00:00
Bradley Smith 08c391c156 [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process. 
llvm-svn: 205868
 2014-04-09 14:42:36 +00:00
Bradley Smith 2ba17a4a17 [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent. 
llvm-svn: 205867
 2014-04-09 14:42:27 +00:00
Bradley Smith ceeb04df60 [ARM64] Copy the named immediate operand mapping logic and enums from AArch64. AArch64's named immediate mapping and parsing is much more advanced than ARM64's. No functionality change - they're currently living side by side while I switch uses over. 
llvm-svn: 205866
 2014-04-09 14:42:16 +00:00
Bradley Smith 8c0b88c987 [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11. 
llvm-svn: 205865
 2014-04-09 14:42:11 +00:00
Bradley Smith 527bf86e56 [ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL) 
llvm-svn: 205864
 2014-04-09 14:42:07 +00:00
Bradley Smith 6d7af17a3f [ARM64] Add missing 1Q -> 1q vector kind alias 
llvm-svn: 205863
 2014-04-09 14:42:01 +00:00
Bradley Smith 7d253f29a4 [ARM64] Add parsing for vector lists such as {v0.8b-v3.8b} 
llvm-svn: 205862
 2014-04-09 14:41:58 +00:00
Bradley Smith 664aa67153 [ARM64] Correctly alias LSL to UXTW for 32bit instruction variants, rather than UXTX 
llvm-svn: 205861
 2014-04-09 14:41:53 +00:00
Bradley Smith 35cadc58c9 [ARM64] STRHro and STRBro were not being decoded at all. 
llvm-svn: 205860
 2014-04-09 14:41:49 +00:00
Bradley Smith 87c60e00d5 [ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4. 
llvm-svn: 205859
 2014-04-09 14:41:45 +00:00
Bradley Smith cd91e5cd0c [ARM64] Register-offset loads and stores with the 'option' field equal to 00x or 10x are undefined. 
llvm-svn: 205858
 2014-04-09 14:41:38 +00:00
Elena Demikhovsky cf0b9bafc3 AVX-512: insert element to mask vector; store i1 data 
Implemented INSERT_VECTOR_ELT operation for v16i1 and v8i1 vectors;
Implemented "store" for i1 type

llvm-svn: 205850
 2014-04-09 12:37:50 +00:00
Daniel Sanders b282f1fec5 Re-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of -enable-no-nans-fp-math 
Summary:
They behave in accordance with the Has2008 and ABS2008 configuration bits of the processor which are used to select between the 1985 and 2008 versions of IEEE 754. In 1985 mode, these instructions are arithmetic (i.e. they raise invalid operation exceptions when given NaN), in 2008 mode they are non-arithmetic (i.e. they are copies).

nmadd.[ds], and nmsub.[ds] are still subject to -enable-no-nans-fp-math because the ISA spec does not explicitly state that they obey Has2008 and ABS2008.

Fixed the issue with the previous version of this patch (r205628). A pre-existing 'let Predicate =' statement was removing some predicates that were necessary for FP64 to behave correctly.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3274

llvm-svn: 205844
 2014-04-09 09:56:43 +00:00
Matt Arsenault 2c33562cd6 R600/SI: Match not instruction. 
llvm-svn: 205837
 2014-04-09 07:16:16 +00:00
Tim Northover b36d428d27 ARM64: scalarize v1i64 mul operation 
This is the second part of fixing PR19367.

llvm-svn: 205836
 2014-04-09 07:07:02 +00:00
Tim Northover b430cf6681 ARM64: add pattern for <1 x i64> custom not node. 
This should fix PR19367.

llvm-svn: 205835
 2014-04-09 06:55:39 +00:00
Saleem Abdulrasool fedfc2a63f ARM MC: 80 column 
llvm-svn: 205833
 2014-04-09 06:18:26 +00:00
Saleem Abdulrasool 5019a978ae ARM MC: sort source files in CMakeLists 
llvm-svn: 205832
 2014-04-09 06:18:23 +00:00
Craig Topper 8d399f87af [C++11] Replace some comparisons with 'nullptr' with simple boolean checks to reduce verbosity. 
llvm-svn: 205829
 2014-04-09 04:20:00 +00:00
Juergen Ributzka c11e8b67bb [Constant Hoisting][ARM64] Enable constant hoisting for ARM64. 
This implements the target-hooks for ARM64 to enable constant hoisting.

This fixes <rdar://problem/14774662> and <rdar://problem/16381500>.

llvm-svn: 205791
 2014-04-08 20:39:59 +00:00
Hal Finkel a775e51274 [PowerPC] Don't return false from PPC::isVSLDOIShuffleMask 
PPC::isVSLDOIShuffleMask should return -1, not false, when the shuffle
predicate should be false.

Noticed by inspection; no test case (yet).

llvm-svn: 205787
 2014-04-08 19:00:27 +00:00
Kevin Enderby d88fec3d3a Fix the ARM VLD3 (single 3-element structure to all lanes) 
size 16 double-spaced registers instruction printing.

This:
	vld3.16 {d0[], d2[], d4[]}, [r4]!

was being printed as:

	vld3.16	{d0[], d1[], d2[]}, [r4]!

rdar://16531387

llvm-svn: 205779
 2014-04-08 18:00:52 +00:00
NAKAMURA Takumi 35289340de X86MCAsmInfoGNUCOFF: Set PointerSize as 8 for targeting x64. It caused DW_LNE_set_address was misemitted on x64. 
FIXME: I haven't investigate whether CalleeSaveStackSlotSize should be 8.
llvm-svn: 205772
 2014-04-08 15:28:50 +00:00
Tim Northover 33d07468bc ARM64: fix fmsub patterns which assumed accum operand was first 
Confusingly, the NEON fmla instructions put the accumulator first but the
scalar versions put it at the end (like the fma lib function & LLVM's
intrinsic).

This should fix PR19345, assuming there's only one issue.

llvm-svn: 205758
 2014-04-08 12:23:51 +00:00
Elena Demikhovsky 3dcfbdfa54 AVX-512: Added fp_to_uint and uint_to_fp patterns. 
llvm-svn: 205754
 2014-04-08 07:24:02 +00:00
David Majnemer c9d2625586 X86: Split the relocation selection up 
Before, we would have conditional operators where one side of the
operator would be of type RelocationTypeAMD64 and the other is of type
RelocationTypeI386.  GCC would noisly warn with -Wenum-compare
diagnostic.

Instead, refactor the code so it is more like the X86 ELF object writer.

llvm-svn: 205752
 2014-04-08 02:15:13 +00:00
Jim Grosbach e75c048ab9 Tidy up comments a bit. 
Punctuation, grammar, formatting, etc..

llvm-svn: 205749
 2014-04-07 23:47:23 +00:00
Jim Grosbach 75010e7712 ARM64: Range based for loop in ARM64PromoteConstant pass 
llvm-svn: 205748
 2014-04-07 23:47:21 +00:00
Jim Grosbach 64a28e70c8 ARM64: Clean up file header comment a bit. 
llvm-svn: 205747
 2014-04-07 23:14:38 +00:00
Reed Kotler 735da8e015 Reverting commit r205628 due to mips64 issues. 
llvm-svn: 205741
 2014-04-07 22:11:40 +00:00
Tom Stellard 204e61bbdf R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies 
llvm-svn: 205732
 2014-04-07 19:45:45 +00:00
Tom Stellard 50122a5890 R600: Match 24-bit arithmetic patterns in a Target DAGCombine 
Moving these patterns from TableGen files to PerformDAGCombine()
should allow us to generate better code by eliminating unnecessary
shifts and extensions earlier.

This also fixes a bug where the MAD pattern was calling
SimplifyDemandedBits with a 24-bit mask on the first operand
even when the full pattern wasn't being matched.  This occasionally
resulted in some instructions being incorrectly deleted from the
program.

v2:
  - Fix bug with 64-bit mul

llvm-svn: 205731
 2014-04-07 19:45:41 +00:00
Tom Stellard 3cbe014027 R600: Replace dyn_cast + assert with cast 
llvm-svn: 205730
 2014-04-07 19:31:13 +00:00
Matt Arsenault 4be76e99fe Use std::swap 
llvm-svn: 205723
 2014-04-07 16:44:26 +00:00
Matt Arsenault 7939acd7fa Use .data() instead of &x[0] 
llvm-svn: 205722
 2014-04-07 16:44:24 +00:00
David Blaikie 2f7711242a MachineInstr: introduce explicit_operands and implicit_operands ranges 
Makes iteration over implicit and explicit machine operands more
explicit (har har). Insipired by code review discussion for r205565.

llvm-svn: 205680
 2014-04-05 22:42:04 +00:00