eb4ca04db2
[ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.
...
llvm-svn: 205882
2014-04-09 14:43:35 +00:00
db7b9b17eb
[ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have the top bit of their immediate clear.
...
llvm-svn: 205881
2014-04-09 14:43:31 +00:00
60e7667886
[ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero.
...
llvm-svn: 205880
2014-04-09 14:43:27 +00:00
7525b47208
[ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.
...
llvm-svn: 205879
2014-04-09 14:43:24 +00:00
0243aa33fa
[ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu.
...
llvm-svn: 205878
2014-04-09 14:43:20 +00:00
8f906a3c5f
[ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.
...
llvm-svn: 205877
2014-04-09 14:43:15 +00:00
9f29b726d5
[ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases.
...
llvm-svn: 205876
2014-04-09 14:43:11 +00:00
e8b4166acc
[ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.
...
llvm-svn: 205875
2014-04-09 14:43:06 +00:00
bc35b1f138
[ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value.
...
llvm-svn: 205874
2014-04-09 14:43:01 +00:00
4925be9b56
[ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during disassembly.
...
llvm-svn: 205873
2014-04-09 14:42:56 +00:00
3339427e2a
[ARM64] Remove PrefetchOp and use ARM64PRFM instead.
...
llvm-svn: 205872
2014-04-09 14:42:53 +00:00
16478c4ccf
[ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway.
...
llvm-svn: 205871
2014-04-09 14:42:49 +00:00
3db2a85853
[ARM64] Remove ARM64SYS.
...
llvm-svn: 205870
2014-04-09 14:42:45 +00:00
fb90df563f
[ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS.
...
llvm-svn: 205869
2014-04-09 14:42:42 +00:00
08c391c156
[ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process.
...
llvm-svn: 205868
2014-04-09 14:42:36 +00:00
2ba17a4a17
[ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent.
...
llvm-svn: 205867
2014-04-09 14:42:27 +00:00
ceeb04df60
[ARM64] Copy the named immediate operand mapping logic and enums from AArch64. AArch64's named immediate mapping and parsing is much more advanced than ARM64's. No functionality change - they're currently living side by side while I switch uses over.
...
llvm-svn: 205866
2014-04-09 14:42:16 +00:00
8c0b88c987
[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11.
...
llvm-svn: 205865
2014-04-09 14:42:11 +00:00
527bf86e56
[ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL)
...
llvm-svn: 205864
2014-04-09 14:42:07 +00:00
6d7af17a3f
[ARM64] Add missing 1Q -> 1q vector kind alias
...
llvm-svn: 205863
2014-04-09 14:42:01 +00:00
7d253f29a4
[ARM64] Add parsing for vector lists such as {v0.8b-v3.8b}
...
llvm-svn: 205862
2014-04-09 14:41:58 +00:00
664aa67153
[ARM64] Correctly alias LSL to UXTW for 32bit instruction variants, rather than UXTX
...
llvm-svn: 205861
2014-04-09 14:41:53 +00:00
35cadc58c9
[ARM64] STRHro and STRBro were not being decoded at all.
...
llvm-svn: 205860
2014-04-09 14:41:49 +00:00
87c60e00d5
[ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4.
...
llvm-svn: 205859
2014-04-09 14:41:45 +00:00
cd91e5cd0c
[ARM64] Register-offset loads and stores with the 'option' field equal to 00x or 10x are undefined.
...
llvm-svn: 205858
2014-04-09 14:41:38 +00:00
2c4e8ae0fd
Revert "YAMLIO: Encode ambiguous hex strings explicitly"
...
This reverts commit r205839.
It broke several tests in lld.
llvm-svn: 205857
2014-04-09 14:35:17 +00:00
fd0bf5d6e5
SLPVectorizer: Only vectorize intrinsics whose operands are widened equally
...
The vectorizer only knows how to vectorize intrinics by widening all operands by
the same factor.
Patch by Tyler Nowicki!
llvm-svn: 205855
2014-04-09 14:20:47 +00:00
cf0b9bafc3
AVX-512: insert element to mask vector; store i1 data
...
Implemented INSERT_VECTOR_ELT operation for v16i1 and v8i1 vectors;
Implemented "store" for i1 type
llvm-svn: 205850
2014-04-09 12:37:50 +00:00
b282f1fec5
Re-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of -enable-no-nans-fp-math
...
Summary:
They behave in accordance with the Has2008 and ABS2008 configuration bits of the processor which are used to select between the 1985 and 2008 versions of IEEE 754. In 1985 mode, these instructions are arithmetic (i.e. they raise invalid operation exceptions when given NaN), in 2008 mode they are non-arithmetic (i.e. they are copies).
nmadd.[ds], and nmsub.[ds] are still subject to -enable-no-nans-fp-math because the ISA spec does not explicitly state that they obey Has2008 and ABS2008.
Fixed the issue with the previous version of this patch (r205628). A pre-existing 'let Predicate =' statement was removing some predicates that were necessary for FP64 to behave correctly.
Reviewers: matheusalmeida
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3274
llvm-svn: 205844
2014-04-09 09:56:43 +00:00
815433587c
YAMLIO: Encode ambiguous hex strings explicitly
...
YAMLIO would turn a BinaryRef into the string 0000000004000000.
However, the leading zero causes parsers to interpret it as being an
octal number instead of a hexadecimal one.
Instead, escape such strings as needed.
llvm-svn: 205839
2014-04-09 07:56:27 +00:00
c3d9db2336
Delinearize: Extend informationin -analyze output
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llvm-svn: 205838
2014-04-09 07:53:49 +00:00
2c33562cd6
R600/SI: Match not instruction.
...
llvm-svn: 205837
2014-04-09 07:16:16 +00:00
b36d428d27
ARM64: scalarize v1i64 mul operation
...
This is the second part of fixing PR19367.
llvm-svn: 205836
2014-04-09 07:07:02 +00:00
b430cf6681
ARM64: add pattern for <1 x i64> custom not node.
...
This should fix PR19367.
llvm-svn: 205835
2014-04-09 06:55:39 +00:00
5c503bf4c4
Object: add type names for ARM/COFF relocations
...
Add type name mappings for the ARM COFF relocations. This allows for objdump to
provide a more useful description of relocations in disassembly inline form.
llvm-svn: 205834
2014-04-09 06:18:28 +00:00
fedfc2a63f
ARM MC: 80 column
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llvm-svn: 205833
2014-04-09 06:18:26 +00:00
5019a978ae
ARM MC: sort source files in CMakeLists
...
llvm-svn: 205832
2014-04-09 06:18:23 +00:00
c620761ca5
[C++11] More 'nullptr' conversion or in some cases just using a boolean check instead of comparing to nullptr.
...
llvm-svn: 205831
2014-04-09 06:08:46 +00:00
011817a0bf
[C++11] Make use of 'nullptr' in TableGen library.
...
llvm-svn: 205830
2014-04-09 04:50:04 +00:00
8d399f87af
[C++11] Replace some comparisons with 'nullptr' with simple boolean checks to reduce verbosity.
...
llvm-svn: 205829
2014-04-09 04:20:00 +00:00
a9bdb32f04
WinCOFF: Emit common symbols as specified in the COFF spec
...
Summary:
Local common symbols were properly inserted into the .bss section.
However, putting external common symbols in the .bss section would give
them a strong definition.
Instead, encode them as undefined, external symbols who's symbol value
is equivalent to their size.
Reviewers: Bigcheese, rafael, rnk
CC: llvm-commits
Differential Revision: http://reviews.llvm.org/D3324
llvm-svn: 205811
2014-04-08 22:33:40 +00:00
aaf9623d55
Bug 19348: Check for legal ExtLoad operation before folding
...
(aext (zextload x)) -> (aext (truncate (*extload x)))
Patch by Stanislav Mekhanoshin!
llvm-svn: 205805
2014-04-08 21:40:37 +00:00
b2fdacf3f2
divide by the result of the gcd
...
used to fail with 'Step should divide Start with no remainder.'
llvm-svn: 205802
2014-04-08 21:21:13 +00:00
9738e83a7d
handle special cases when findGCD returns 1
...
used to fail with 'Step should divide Start with no remainder.'
llvm-svn: 205801
2014-04-08 21:21:10 +00:00
b5b84e0963
in findGCD of multiply expr return the gcd
...
we used to return 1 instead of the gcd
llvm-svn: 205800
2014-04-08 21:21:05 +00:00
c11e8b67bb
[Constant Hoisting][ARM64] Enable constant hoisting for ARM64.
...
This implements the target-hooks for ARM64 to enable constant hoisting.
This fixes <rdar://problem/14774662> and <rdar://problem/16381500>.
llvm-svn: 205791
2014-04-08 20:39:59 +00:00
a5df813e51
RegAlloc: Account for a variable entry block frequency
...
Until r197284, the entry frequency was constant -- i.e., set to 2^14.
Although current ToT still has a constant entry frequency, since r197284
that has been an implementation detail (which is soon going to change).
- r204690 made the wrong assumption for the CSRCost metric. Adjust
callee-saved register cost based on entry frequency.
- r185393 made the wrong assumption (although it was valid at the
time). Update SpillPlacement.cpp::Threshold to be relative to the
entry frequency.
Since ToT still has 2^14 entry frequency, this should have no observable
functionality change.
<rdar://problem/14292693>
llvm-svn: 205789
2014-04-08 19:18:56 +00:00
a775e51274
[PowerPC] Don't return false from PPC::isVSLDOIShuffleMask
...
PPC::isVSLDOIShuffleMask should return -1, not false, when the shuffle
predicate should be false.
Noticed by inspection; no test case (yet).
llvm-svn: 205787
2014-04-08 19:00:27 +00:00
d88fec3d3a
Fix the ARM VLD3 (single 3-element structure to all lanes)
...
size 16 double-spaced registers instruction printing.
This:
vld3.16 {d0[], d2[], d4[]}, [r4]!
was being printed as:
vld3.16 {d0[], d1[], d2[]}, [r4]!
rdar://16531387
llvm-svn: 205779
2014-04-08 18:00:52 +00:00
2541d4e525
Verifier: Give the right message for bad atomic loads
...
Talk about load (not store) on an invalid atomic load.
<rdar://problem/16287567>
llvm-svn: 205777
2014-04-08 17:07:44 +00:00
Bradley Smith