Commit Graph

229 Commits

Author SHA1 Message Date
Bill Wendling 351b6659ad Temporarily revert r60382. It caused CodeGen/X86/i2k.ll and others to fail.
llvm-svn: 60383
2008-12-01 23:44:08 +00:00
Bill Wendling a435b1aebc - Have "ADD" instructions return an implicit EFLAGS.
- Add support for seto, setno, setc, and setnc instructions.

llvm-svn: 60382
2008-12-01 23:30:42 +00:00
Bill Wendling 751a694ad3 Generate something sensible for an [SU]ADDO op when the overflow/carry flag is
the conditional for the BRCOND statement. For instance, it will generate:

    addl %eax, %ecx
    jo LOF

instead of

    addl %eax, %ecx
    ; About 10 instructions to compare the signs of LHS, RHS, and sum.
    jl LOF

llvm-svn: 60123
2008-11-26 22:37:40 +00:00
Dan Gohman 002a2cb207 Fish kill flag annotations in PUSH instructions.
llvm-svn: 60095
2008-11-26 06:39:12 +00:00
Dan Gohman 0b2732598c Add more const qualifiers. This fixes build breakage from r59540.
llvm-svn: 59542
2008-11-18 19:49:32 +00:00
Evan Cheng f713722975 For now, don't split live intervals around x87 stack register barriers. FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them.
llvm-svn: 58230
2008-10-27 07:14:50 +00:00
Nicolas Geoffray db30612fc4 Generate code for TLS instructions.
llvm-svn: 58141
2008-10-25 15:22:06 +00:00
Dan Gohman 97d95d6d85 Optimized FCMP_OEQ and FCMP_UNE for x86.
Where previously LLVM might emit code like this:

        ucomisd %xmm1, %xmm0
        setne   %al
        setp    %cl
        orb     %al, %cl
        jne     .LBB4_2

it now emits this:

        ucomisd %xmm1, %xmm0
        jne     .LBB4_2
        jp      .LBB4_2

It has fewer instructions and uses fewer registers, but it does
have more branches. And in the case that this code is followed by
a non-fallthrough edge, it may be followed by a jmp instruction,
resulting in three branch instructions in sequence. Some effort
is made to avoid this situation.

To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and
FCMP_UNE in lowered form, and replace them with code that emits
two branches, except in the case where it would require converting
a fall-through edge to an explicit branch.

Also, X86InstrInfo.cpp's branch analysis and transform code now
knows now to handle blocks with multiple conditional branches. It
uses loops instead of having fixed checks for up to two
instructions. It can now analyze and transform code generated
from FCMP_OEQ and FCMP_UNE.

llvm-svn: 57873
2008-10-21 03:29:32 +00:00
Dan Gohman c835458da9 When the coalescer is doing rematerializing, have it remove
the copy instruction from the instruction list before asking the
target to create the new instruction. This gets the old instruction
out of the way so that it doesn't interfere with the target's
rematerialization code. In the case of x86, this helps it find
more cases where EFLAGS is not live.

Also, in the X86InstrInfo.cpp, teach isSafeToClobberEFLAGS to check
to see if it reached the end of the block after scanning each
instruction, instead of just before. This lets it notice when the
end of the block is only two instructions away, without doing any
additional scanning.

These changes allow rematerialization to clobber EFLAGS in more
cases, for example using xor instead of mov to set the return value
to zero in the included testcase.

llvm-svn: 57872
2008-10-21 03:24:31 +00:00
Dan Gohman a39b0a1f05 Define patterns for shld and shrd that match immediate
shift counts, and patterns that match dynamic shift counts
when the subtract is obscured by a truncate node.

Add DAGCombiner support for recognizing rotate patterns
when the shift counts are defined by truncate nodes.

Fix and simplify the code for commuting shld and shrd
instructions to work even when the given instruction doesn't
have a parent, and when the caller needs a new instruction.

These changes allow LLVM to use the shld, shrd, rol, and ror
instructions on x86 to replace equivalent code using two
shifts and an or in many more cases.

llvm-svn: 57662
2008-10-17 01:23:35 +00:00
Dan Gohman 33332bce17 Const-ify several TargetInstrInfo methods.
llvm-svn: 57622
2008-10-16 01:49:15 +00:00
Anton Korobeynikov 46a9c01fff Update size of inst correctly with segment override.
llvm-svn: 57414
2008-10-12 10:30:11 +00:00
Anton Korobeynikov b52ef06c8c Revert r56675 - it breaks unwinding runtime everywhere.
llvm-svn: 57048
2008-10-04 11:09:36 +00:00
Dan Gohman 0d1e9a8e04 Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.

llvm-svn: 57006
2008-10-03 15:45:36 +00:00
Dan Gohman 6ebe734ca6 Move the GlobalBaseReg field out of X86ISelDAGToDAG.cpp
and X86FastISel.cpp into X86MachineFunction.h, so that it
can be shared, instead of having each selector keep track
of its own.

llvm-svn: 56825
2008-09-30 00:58:23 +00:00
Dan Gohman 7e922aa35d Mark lea fi# as being really rematerializable.
llvm-svn: 56698
2008-09-26 21:30:20 +00:00
Evan Cheng 994dd0bbec Avoid spilling EBP / RBP twice in the prologue.
llvm-svn: 56675
2008-09-26 19:14:21 +00:00
Dan Gohman 2430073657 Move the code for initializing the global base reg out of
X86ISelDAGToDAG.cpp and into X86InstrInfo.cpp. This will allow
it to be reused by FastISel.

llvm-svn: 56494
2008-09-23 18:22:58 +00:00
Dan Gohman 38453eebdc Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.

llvm-svn: 56189
2008-09-13 17:58:21 +00:00
Evan Cheng f93bc7f755 Use static_cast instead of C style cast.
llvm-svn: 55552
2008-08-29 23:21:31 +00:00
Evan Cheng b3ed09703c Backing out 55521. Not safe.
llvm-svn: 55548
2008-08-29 22:13:21 +00:00
Evan Cheng 960b17a3c2 Swap fp comparison operands and change predicate to allow load folding.
llvm-svn: 55521
2008-08-28 23:48:31 +00:00
Owen Anderson 42ccd39689 These assertions should be return false's instead, allowing the client to detect the failure.
llvm-svn: 55377
2008-08-26 18:50:40 +00:00
Owen Anderson 27fb3dcbc7 Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
was inserted or not.  This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.

llvm-svn: 55375
2008-08-26 18:03:31 +00:00
Owen Anderson 4f6bf04616 Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.
llvm-svn: 54802
2008-08-14 22:49:33 +00:00
Dan Gohman 4e2f3ace2c Add an EXTRACTPSmr pattern to match the pattern that
X86ISelLowering creates.

llvm-svn: 54544
2008-08-08 18:30:21 +00:00
Dan Gohman 527ca7e253 Re-enable elimination of unnecessary SUBREG_TO_REG instructions in
LowerSubregs, and fix an x86-64 isel bug that this exposed.

SUBREG_TO_REG for x86-64 implicit zero extension is only safe for
isel to generate when the source is known to always have zeros in
the high 32 bits. The EXTRACT_SUBREG instruction does not clear
the high 32 bits.

llvm-svn: 54444
2008-08-07 02:54:50 +00:00
Dan Gohman 2ce6f2ad5e Rename SDOperand to SDValue.
llvm-svn: 54128
2008-07-27 21:46:04 +00:00
Evan Cheng e001643358 Use movaps instead of movups to spill 16-byte vector values when default alignment is >= 16. This fixes some massive performance regressions.
llvm-svn: 53844
2008-07-21 06:34:17 +00:00
Anton Korobeynikov b7a49925a1 Use aligned stack spills, where possible. This fixes PR2549.
llvm-svn: 53784
2008-07-19 06:30:51 +00:00
Dan Gohman 1705968102 Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.

Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.

This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.

These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.

llvm-svn: 53728
2008-07-17 19:10:17 +00:00
Dan Gohman 9a542a4d5f Add a utility function to MachineInstr for testing whether an instruction
has exactly one MachineMemOperand, and change some X86 lowering code to
make use of it.

llvm-svn: 53498
2008-07-12 00:10:52 +00:00
Dan Gohman 3b46030375 Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.

llvm-svn: 53212
2008-07-07 23:14:23 +00:00
Dan Gohman 38740a98b2 Make DenseMap's insert return a pair, to more closely resemble std::map.
llvm-svn: 53177
2008-07-07 17:46:23 +00:00
Evan Cheng 7d98a48f15 - Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc.
- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.

llvm-svn: 53097
2008-07-03 09:09:37 +00:00
Evan Cheng c939f45fe7 commuteInstruction should preserve dead markers.
llvm-svn: 53060
2008-07-03 00:04:51 +00:00
Owen Anderson 30cc028e4a Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction
Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place.

llvm-svn: 53058
2008-07-02 23:41:07 +00:00
Dan Gohman fb19f9402b Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.

Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.

This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.

llvm-svn: 52943
2008-07-01 00:05:16 +00:00
Evan Cheng 3f2ceac565 If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction.
llvm-svn: 52670
2008-06-24 07:10:51 +00:00
Evan Cheng 03553bb59a Add option to commuteInstruction() which forces it to create a new (commuted) instruction.
llvm-svn: 52308
2008-06-16 07:33:11 +00:00
Duncan Sands 13237ac3b9 Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).

llvm-svn: 52044
2008-06-06 12:08:01 +00:00
Dan Gohman 3388d022ac Use PMULDQ for v2i64 multiplies when SSE4.1 is available. And add
load-folding table entries for PMULDQ and PMULLD.

llvm-svn: 51489
2008-05-23 17:49:40 +00:00
Dan Gohman eabd647cd5 Change target-specific classes to use more precise static types.
This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.

llvm-svn: 51091
2008-05-14 01:58:56 +00:00
Bill Wendling 1e11768a4f Constify the machine instruction passed into the
"is{Trivially,Really}ReMaterializable" methods.

llvm-svn: 51001
2008-05-12 20:54:26 +00:00
Evan Cheng fa8f9f937a Undo r50574. We are already ensuring the folded load address is 16-byte aligned.
llvm-svn: 50578
2008-05-02 17:01:01 +00:00
Evan Cheng 50f82f2c8e Not safe folding a load + FsXORPSrr into FsXORPSrm. It's loading a FR64 value but the load folding variant expects a 16-byte aligned address.
llvm-svn: 50574
2008-05-02 07:50:58 +00:00
Nicolas Geoffray 984e7199cc Don't forget to update the current operand when getting the size of an instruction.
llvm-svn: 50007
2008-04-20 23:36:47 +00:00
Evan Cheng 147cb764b5 Don't forget about sub-register indices when rematting instructions.
llvm-svn: 49830
2008-04-16 23:44:44 +00:00
Nicolas Geoffray ae84bbdbed Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
llvm-svn: 49809
2008-04-16 20:10:13 +00:00
Dan Gohman 3bc3ddd638 Rename MemOperand to MachineMemOperand. This was suggested by
review feedback from Chris quite a while ago. No functionality
change.

llvm-svn: 49348
2008-04-07 19:35:22 +00:00