7258735fa0
ARM: fixup more tests to specify the target more explicitly
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This changes the tests that were targeting ARM EABI to explicitly specify the
environment rather than relying on the default. This breaks with the new
Windows on ARM support when running the tests on Windows where the default
environment is no longer EABI.
Take the opportunity to avoid a pointless redirect (helps when trying to debug
with providing a command line invocation which can be copy and pasted) and
removing a few greps in favour of FileCheck.
llvm-svn: 205541
2014-04-03 16:01:44 +00:00
c0b42f718e
ARM: force soft-float ABI for tests depending on it.
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This should fix the ARM bots.
llvm-svn: 197555
2013-12-18 09:58:06 +00:00
f799e3f944
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion.
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This was done with the following sed invocation to catch label lines demarking function boundaries:
sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll
which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct.
llvm-svn: 186258
2013-07-13 20:38:47 +00:00
0ba797e8f7
Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions.
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The Printer will now print instructions with the correct alignment specifier syntax, like
vld1.8 {d16}, [r0:64]
llvm-svn: 175884
2013-02-22 10:01:33 +00:00
90ae8f8442
Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byte
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aligned address. Based on patch by David Peixotto.
Also use vld1.64 / vst1.64 with 128-bit alignment to take advantage of alignment
hints. rdar://12090772, rdar://12238782
llvm-svn: 164089
2012-09-18 01:42:45 +00:00
3e41a5bb31
Set operation action for FFLOOR to Expand for all vector types for X86. Set FFLOOR of v4f32 to Expand for ARM. v2f64 was already correct.
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llvm-svn: 163458
2012-09-08 04:58:43 +00:00
f39c1a3f72
Add correct set of regression tests for r162094 commit.
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llvm-svn: 162276
2012-08-21 12:43:03 +00:00
74e6f9fc65
Add a missing def flag.
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*** Bad machine code: Explicit definition marked as use ***
- function: test_cos
- basic block: BB#0 L.entry (0x7ff2a2024fd0)
- instruction: VSETLNi32 %D11, %D11<undef>, %R0, 0, pred:14, pred:%noreg, %Q5<imp-use,kill>, %Q5<imp-def>
- operand 0: %D11
llvm-svn: 162247
2012-08-21 00:34:53 +00:00
f66181530f
Implement NEON domain switching for scalar <-> S-register vmovs on ARM
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llvm-svn: 162094
2012-08-17 11:32:52 +00:00
e96286cdf2
Make sure DAGCombiner doesn't introduce multiple loads from the same memory location. PR10747, part 2.
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llvm-svn: 147283
2011-12-26 22:49:32 +00:00
4683740967
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11.
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llvm-svn: 146341
2011-12-11 14:35:48 +00:00
6641294e3b
Revert r146322 to appease buildbots. Original commit message:
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Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for
FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second
attempt.
llvm-svn: 146328
2011-12-10 19:55:03 +00:00
df0b779e9f
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt.
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llvm-svn: 146322
2011-12-10 08:42:24 +00:00
c09e4593b2
Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics
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sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.
llvm-svn: 146157
2011-12-08 17:32:18 +00:00
a4bcf27dae
Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
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llvm-svn: 146143
2011-12-08 07:55:03 +00:00
Saleem Abdulrasool