Commit Graph

25360 Commits

Author SHA1 Message Date
Lang Hames 1316365e2c [MCJIT] Fix the ARM BR24 relocation in RuntimeDyldMachO.
We now (1) correctly decode the branch immediate, (2) modify the immediate to
corretly treat it as PC-rel, and (3) properly populate the stub entry.
Previously we had been doing each of these wrong.

<rdar://problem/17750739>

llvm-svn: 214285
2014-07-30 03:35:05 +00:00
Adam Nemet f1a80c1e17 [AVX512] Test that _mm512_set1_* intrinsics generate broadcasts
llvm-svn: 214275
2014-07-30 01:30:51 +00:00
Adam Nemet 9dcc254a47 [AVX512] Add missing CHECK-LABEL
llvm-svn: 214273
2014-07-30 01:30:45 +00:00
Duncan P. N. Exon Smith 3cbca2055a Reapply "UseListOrder: Order GlobalValue uses after initializers"
This reverts commit r214249, reapplying r214242 and r214243, now that
r214270 has fixed the UB.

llvm-svn: 214271
2014-07-30 01:22:16 +00:00
Petar Jovanovic b7c305f091 Add support for scalarizing ctlz_zero_undef
Fix the missing case in ScalarizeVectorResult() that was exposed with
libclcore.bc in Android.

Differential Revision: http://reviews.llvm.org/D4645

llvm-svn: 214266
2014-07-30 00:44:03 +00:00
Joerg Sonnenberger 130765558b Add rfci instruction.
llvm-svn: 214256
2014-07-29 23:45:20 +00:00
Joerg Sonnenberger 2450768251 mbar without argument is equivalent to mbar 0.
llvm-svn: 214250
2014-07-29 23:31:27 +00:00
Duncan P. N. Exon Smith b57aef0030 Revert "UseListOrder: Order GlobalValue uses after initializers"
This reverts commits r214242 and r214243 while I investigate buildbot
failures [1][2][3].  I can't reproduce these failures locally, so if
anyone can see what I've done wrong, I'd appreciate a note.

[1]: http://lab.llvm.org:8011/builders/llvm-hexagon-elf/builds/9840
[2]: http://lab.llvm.org:8011/builders/clang-hexagon-elf/builds/14981
[3]: http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/15191

llvm-svn: 214249
2014-07-29 23:31:11 +00:00
Joerg Sonnenberger 99ef10f915 Recognize BookE's mbar instruction.
llvm-svn: 214244
2014-07-29 23:16:31 +00:00
Duncan P. N. Exon Smith 508f5b0316 UseListOrder: Additional test coverage for r214242
r214242 was subtle enough it really deserves a targeted test with
comments.  This adds some global variables that trigger the relevant
code path.  Sorry this wasn't committed with the fix.

llvm-svn: 214243
2014-07-29 23:15:49 +00:00
Duncan P. N. Exon Smith 1d501e8f46 UseListOrder: Order GlobalValue uses after initializers
To avoid unnecessary forward references, the reader doesn't process
initializers of `GlobalValue`s until after the constant pool has been
processed, and then in reverse order.  Model this when predicting
use-list order.  This gets two more Bitcode tests passing with
`llvm-uselistorder`.

Part of PR5680.

llvm-svn: 214242
2014-07-29 23:06:14 +00:00
Eli Bendersky 447755be51 Add missing test for r214210.
Thanks dblaikie for reminding me.

llvm-svn: 214239
2014-07-29 22:57:59 +00:00
Joerg Sonnenberger 053566aeab Fix typo in alias: DSIR -> DSISR
llvm-svn: 214238
2014-07-29 22:42:44 +00:00
Justin Bogner cf36a366a8 llvm-profdata: Clean up and reorganize some tests
This moves some tests around to make it clearer what's being tested,
and adds very rudimentary comment syntax to the text input format to
make specifying this kind of test a little bit simpler.

llvm-svn: 214235
2014-07-29 22:29:23 +00:00
Joerg Sonnenberger 9e9623ca64 Support move to/from segment register.
llvm-svn: 214234
2014-07-29 22:21:57 +00:00
Lang Hames 3ce5baefce [MCJIT] XFAIL some RuntimeDyld tests on MIPS - RuntimeDyldChecker isn't properly
endian-aware yet, and this is causing failures when cross-linking on MIPS.

llvm-svn: 214231
2014-07-29 21:48:22 +00:00
Rafael Espindola 6c472e5e14 gold plugin: Fix handling of corrupted bitcode files.
We should still claim them and tell gold about the error.

llvm-svn: 214214
2014-07-29 20:46:19 +00:00
Lang Hames 480763f814 [MCJIT] Make the RuntimeDyldChecker stub_addr builtin use file names rather than
full paths for its first argument.

This allows us to remove the annoying sed lines in the test cases, and write
direct references to file names in stub_addr calls (rather than <filename>
placeholders).

llvm-svn: 214211
2014-07-29 20:40:37 +00:00
Juergen Ributzka 0e913b17d6 [RuntimeDyld][AArch64] Make encode/decodeAddend also work on big-endian hosts.
llvm-svn: 214205
2014-07-29 19:57:15 +00:00
Joerg Sonnenberger b1ccf5623b Add a number of aliases for SPR access.
llvm-svn: 214196
2014-07-29 18:55:43 +00:00
Manman Ren f93ac4bfad [Debug Info] remove DITrivialType and use null to represent unspecified param.
Per feedback on r214111, we are going to use null to represent unspecified
parameter. If the type array is {null}, it means a function that returns void;
If the type array is {null, null}, it means a variadic function that returns
void. In summary if we have more than one element in the type array and the last
element is null, it is a variadic function.

rdar://17628609

llvm-svn: 214189
2014-07-29 18:20:39 +00:00
Rafael Espindola 340aae797d Add a test for the mtriple plugin option.
llvm-svn: 214186
2014-07-29 17:27:07 +00:00
Joerg Sonnenberger accbc9426d Add rfi instruction. Based on feedback by Ulrich Weigand.
llvm-svn: 214181
2014-07-29 15:49:09 +00:00
Sasa Stankovic f4a9e3bc28 [mips] Don't use odd-numbered single precision registers for fastcc calling
convention if -mno-odd-spreg is used.

Differential Revision: http://reviews.llvm.org/D4682

llvm-svn: 214180
2014-07-29 14:39:24 +00:00
Ulrich Weigand e09f73716a [PowerPC] Fix ppc64-elf-abi.ll test case on Darwin
Use full -mtriple instead of just -march to ensure Linux ABI
(ELFv1 or ELFv2) is selected.

llvm-svn: 214179
2014-07-29 12:48:14 +00:00
Tim Northover e2239ff3eb CodeGenPrep: fall back to MVT::Other if instruction's type isn't an EVT.
The test being performed is just an approximation anyway, so it really
shouldn't crash when things don't go entirely as expected.

Should fix PR20474.

llvm-svn: 214177
2014-07-29 10:20:22 +00:00
Tim Northover 4e13a61413 ARM: add __aeabi_d2h for truncation on AEABI systems
ARM does actually define the name for this conversion, so we should use it on
"-eabi" platforms.

llvm-svn: 214176
2014-07-29 09:56:45 +00:00
Tim Northover f67bb2079d ARM: fix @llvm.convert.from.fp16 on softfloat targets.
We need to make sure we use the softened version of all appropriate operands in
the libcall, or things go horribly wrong. This may entail actually executing a
1-stage softening.

llvm-svn: 214175
2014-07-29 09:56:38 +00:00
Jiangning Liu cd296378a7 Implement AArch64 TTI interface isAsCheapAsAMove.
llvm-svn: 214159
2014-07-29 02:09:26 +00:00
Duncan P. N. Exon Smith 3f0fc7bca9 Bitcode: Correctly compare a Use against itself
Fix the sort of expected order in the reader to correctly return `false`
when comparing a `Use` against itself.

This was caught by test/Bitcode/binaryIntInstructions.3.2.ll, so I'm
adding a `RUN` line using `llvm-uselistorder` for every test in
`test/Bitcode` that passes.

A few tests still fail, so I'll investigate those next.

This is part of PR5680.

llvm-svn: 214157
2014-07-29 01:13:56 +00:00
Duncan P. N. Exon Smith fee1f5013c Fix line-endings, NFC
A follow-up commit is adding a RUN line to each of these tests, so fix
the line endings first.  This is a whitespace-only change.

llvm-svn: 214156
2014-07-29 01:10:57 +00:00
Duncan P. N. Exon Smith ff3caa5a3e llvm-uselistorder: Add -num-shuffles option
llvm-svn: 214144
2014-07-28 23:25:21 +00:00
Kevin Enderby 49b4f53cad Tweak llvm-nm’s -undefined-only (aka -u) printing for Mach-O files
to just print the symbol name.  So it matches darwin’s nm(1) -u option.

llvm-svn: 214143
2014-07-28 23:17:38 +00:00
Manman Ren 4dbffad804 Clean up testing cases.
llvm-svn: 214142
2014-07-28 23:16:05 +00:00
Manman Ren bd1628a595 [Debug Info] unique MDNodes in the enum types of each compile unit.
The enum types array by design contains pointers to MDNodes rather than DIRefs.
Unique them when handling the enum types in DwarfDebug.

rdar://17628609

llvm-svn: 214139
2014-07-28 23:04:20 +00:00
Manman Ren bd3c17cc86 Remove extra ; in testing case.
llvm-svn: 214137
2014-07-28 22:46:46 +00:00
Manman Ren f8a1967c8c [Debug Info] add DISubroutineType and its creation takes DITypeArray.
DITypeArray is an array of DITypeRef, at its creation, we will create
DITypeRef (i.e use the identifier if the type node has an identifier).

This is the last patch to unique the type array of a subroutine type.

rdar://17628609

llvm-svn: 214132
2014-07-28 22:24:06 +00:00
Duncan P. N. Exon Smith 1f66c856b5 Bitcode: Serialize (and recover) use-list order
Predict and serialize use-list order in bitcode.  This makes the option
`-preserve-bc-use-list-order` work *most* of the time, but this is still
experimental.

  - Builds a full value-table up front in the writer, sets up a list of
    use-list orders to write out, and discards the table.  This is a
    simpler first step than determining the order from the various
    overlapping IDs of values on-the-fly.

  - The shuffles stored in the use-list order list have an unnecessarily
    large memory footprint.

  - `blockaddress` expressions cause functions to be materialized
    out-of-order.  For now I've ignored this problem, so use-list orders
    will be wrong for constants used by functions that have block
    addresses taken.  There are a couple of ways to fix this, but I
    don't have a concrete plan yet.

  - When materializing functions lazily, the use-lists for constants
    will not be correct.  This use case is out of scope: what should the
    use-list order be, if it's incomplete?

This is part of PR5680.

llvm-svn: 214125
2014-07-28 21:19:41 +00:00
Lang Hames 1f638440c6 [MCJIT] Remove extraneous parentheses in test case.
llvm-svn: 214117
2014-07-28 21:00:48 +00:00
Rafael Espindola 99298fc36a Test the linker plugin handling of llvm.used.
llvm-svn: 214116
2014-07-28 20:42:29 +00:00
Matt Arsenault 2b252ecf6b R600: Modernize test
llvm-svn: 214108
2014-07-28 18:06:08 +00:00
Matt Arsenault 46645fa102 R600/SI: Implement getOptimalMemOpType
The default guess uses i32. This needs an address space argument
to really do the right thing in all cases.

llvm-svn: 214104
2014-07-28 17:49:26 +00:00
Rafael Espindola 6dca51502a Add tests for the various emit-llvm plugin options.
llvm-svn: 214102
2014-07-28 17:37:25 +00:00
Rafael Espindola 2172f51e4e Test the mcpu option.
llvm-svn: 214087
2014-07-28 14:44:33 +00:00
Robert Khasanov 595683da00 [SKX] Enabling mask logic instructions: encoding, lowering
Instructions: KAND{BWDQ}, KANDN{BWDQ}, KOR{BWDQ}, KXOR{BWDQ}, KXNOR{BWDQ}

Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>

llvm-svn: 214081
2014-07-28 13:46:45 +00:00
Ulrich Weigand 085a10c49e [PowerPC] Add testcase forgotten in the 214072 commit.
llvm-svn: 214073
2014-07-28 13:10:25 +00:00
Rafael Espindola 852bad0a95 Start adding some tests for the gold plugin.
These are only used when the 'ld' in the path is gold and the plugin has
been built, but it is already a start to make sure we don't regress features
that cannot be tested with llvm-lto.

llvm-svn: 214058
2014-07-27 23:11:06 +00:00
Saleem Abdulrasool 8988c2a524 ARM: correct handling of features in arch_extension
The subtarget information is the ultimate source of truth for the feature set
that is enabled at this point.  We would previously not propagate the feature
information to the subtarget.  While this worked for the most part (features
would be enabled/disabled as requested), if another operation that changed the
feature bits was encountered (such as a mode switch via a .arm or .thumb
directive), we would end up resetting the behaviour of the architectural
extensions.

Handling this properly requires a slightly more complicated handling.  We need
to check if the feature is now being toggled.  If so, only then do we toggle the
features.  In return, we no longer have to calculate the feature bits ourselves.

The test changes are mostly to the diagnosis, which is now more uniform (a nice
side effect!).  Add an additional test to ensure that we handle this case
properly.

Thanks to Nico Weber for alerting me to this issue!

llvm-svn: 214057
2014-07-27 19:07:09 +00:00
Matt Arsenault 6f2a526101 Add alignment value to allowsUnalignedMemoryAccess
Rename to allowsMisalignedMemoryAccess.

On R600, 8 and 16 byte accesses are mostly OK with 4-byte alignment,
and don't need to be split into multiple accesses. Vector loads with
an alignment of the element type are not uncommon in OpenCL code.

llvm-svn: 214055
2014-07-27 17:46:40 +00:00
Tim Northover 2c46beb0d1 AArch64: fix conversion of 'J' inline asm constraints.
'J' represents a negative number suitable for an add/sub alias
instruction, but while preparing it to become an int64_t we were
mangling the sign extension. So "i32 -1" became 0xffffffffLL, for
example.

Should fix one half of PR20456.

llvm-svn: 214052
2014-07-27 07:10:29 +00:00