ea6b81a2ad
Revert r128691, "IRgen: Improve GCC compatibility when dealing with packed
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arrays by propagating", it's breaking test in ways I don't understand yet.
llvm-svn: 128693
2011-04-01 00:13:33 +00:00
d911f92c46
Remove unused variables
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llvm-svn: 128692
2011-04-01 00:06:01 +00:00
417bf0f147
IRgen: Improve GCC compatibility when dealing with packed arrays by propagating
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the array alignment to the array access.
- This is more or less the best we can do without having alignment present in
the type system, but is a long way from truly matching how GCC handles this.
llvm-svn: 128691
2011-03-31 23:32:15 +00:00
100f53fd25
Fix Thumb and Thumb2 tests to be register allocator independent.
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llvm-svn: 128690
2011-03-31 23:31:50 +00:00
ab8305063b
Apply again changes to support ARM memory asm parsing. I removed
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all LDR/STR changes and left them to a future patch. Passing all
checks now.
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
llvm-svn: 128689
2011-03-31 23:26:08 +00:00
6e597dc8e7
The basic register allocator must also use the inline spiller.
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It is using a trivial rewriter that doesn't know how to insert spill code
requested by the standard spiller.
llvm-svn: 128688
2011-03-31 23:02:17 +00:00
0709342652
Provide a legal pointer register class when targeting thumb1.
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The LocalStackSlotAllocation pass was creating illegal registers.
llvm-svn: 128687
2011-03-31 23:02:15 +00:00
903baeac27
Fix SystemZ tests
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llvm-svn: 128686
2011-03-31 23:02:12 +00:00
8d543de400
Remove unneeded ExecutionContextScope variables.
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llvm-svn: 128685
2011-03-31 23:01:21 +00:00
d74b72b8a9
Instcombile optimization: extractelement(cast) -> cast(extractelement)
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llvm-svn: 128683
2011-03-31 22:57:29 +00:00
ff51d4e559
Fix couple of rewriter bugs related to rewriting a
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__block block declaration. //rdar://9204669
llvm-svn: 128682
2011-03-31 22:49:32 +00:00
77361761fb
-Wuninitialized should not warn about variables captured by blocks as byref.
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Note this can potentially be enhanced to detect if the __block variable
is actually written by the block, or only when the block "escapes" or
is actually used, but that requires more analysis than it is probably worth
for this simple check.
llvm-svn: 128681
2011-03-31 22:32:41 +00:00
0888bcf542
Fix ARM tests to be register allocator independent.
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llvm-svn: 128680
2011-03-31 22:14:03 +00:00
6ffe738f24
Add security syntax checker for strcpy() which causes the Static Analyzer to generate a warning any time the strcpy() function is used with a note suggesting to use a function which provides bounded buffers.
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llvm-svn: 128679
2011-03-31 22:09:14 +00:00
f55a836181
Little bit of cleanup, and added a few new bits.
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llvm-svn: 128678
2011-03-31 21:56:13 +00:00
79d74141b1
Adding Static Analyzer checker for mempcpy().
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Models mempcpy() so that if length is NULL the destination pointer is returned. Otherwise, the source and destination are confirmed not to be NULL and not overlapping. Finally the copy is validated to not cause a buffer overrun and the return value is bound to the address of the byte after the last byte copied.
llvm-svn: 128677
2011-03-31 21:36:53 +00:00
5291054ef1
InstCombine: APFloat can't perform arithmetic on PPC double doubles, don't even try.
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Thanks Eli!
llvm-svn: 128676
2011-03-31 21:35:49 +00:00
d20c8d1a17
Fix a few typos in the previous commit.
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llvm-svn: 128671
2011-03-31 21:31:50 +00:00
70568c2be7
Fix spelling in a comment. (test commit)
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llvm-svn: 128670
2011-03-31 21:26:55 +00:00
028b8b7bb7
Add code to emulate VLD1 (single element to all lanes) ARM instruction.
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llvm-svn: 128669
2011-03-31 21:15:29 +00:00
9cd9c4e5c9
Add a test case for a malformed LDC/LDC2 instructions with PUDW = 0b0000, which
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amounts to an UNDEFINED instruction.
llvm-svn: 128668
2011-03-31 20:54:30 +00:00
38bf5adcea
Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
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accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2
llvm-svn: 128665
2011-03-31 19:38:48 +00:00
7ac974122f
Make ChainedIncludesSource an ExternalSemaSource, otherwise initialization of the ASTReader is incomplete, leading to errors like not realizing std::type_info is already defined.
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llvm-svn: 128664
2011-03-31 19:29:24 +00:00
604caf4008
Tell the diagnostic client about starting and ending source files when automatically creating chained PCHs. This way, we don't get a crash whenever a diagnostic is emitted while processing the include.
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llvm-svn: 128663
2011-03-31 19:29:18 +00:00
7b203f9cae
Fix single word and unsigned byte data transfer instruction encodings so that
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Inst{4} = 0.
rdar://problem/9213022
llvm-svn: 128662
2011-03-31 19:28:35 +00:00
5901ea7e67
Add code to emulate VST1 (single element from one lane) ARM
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instruction (more floating point stores).
llvm-svn: 128661
2011-03-31 19:17:12 +00:00
d64a08144c
Add code to emulate VST1 (multiple single elements) ARM
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instruction (floating point store).
llvm-svn: 128656
2011-03-31 18:44:04 +00:00
f4c9754d5c
Fix Mips, Sparc, and XCore tests that were dependent on register allocation.
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Add an extra run with -regalloc=basic to keep them honest.
llvm-svn: 128654
2011-03-31 18:42:43 +00:00
a535270d91
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons.
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llvm-svn: 128650
2011-03-31 18:26:17 +00:00
9feca67182
Pick better examples. "fpext float 3.1415 to double" won't parse because 3.1415
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isn't an exact float. Also "fpext float 1.0 to float" is invalid IR because
it's not performing an extension.
llvm-svn: 128647
2011-03-31 18:20:19 +00:00
bc2b96b699
Add code to emulate VLD1 (single element to one lane) floating point
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register load instruction (ARM) .
llvm-svn: 128646
2011-03-31 17:58:23 +00:00
e6e6750670
Don't completely eliminate identity copies that also modify super register liveness.
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Turn them into noop KILL instructions instead. This lets the scavenger know when
super-registers are killed and defined.
llvm-svn: 128645
2011-03-31 17:55:25 +00:00
13baa0e650
Add BLXi to the instruction table for disassembly purpose.
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A8.6.23 BLX (immediate)
rdar://problem/9212921
llvm-svn: 128644
2011-03-31 17:53:50 +00:00
561cea0480
Allow kill flags on two-address instructions. They are harmless.
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llvm-svn: 128643
2011-03-31 17:52:41 +00:00
9a78835414
Mark all uses as <undef> when joining a copy.
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This way, shrinkToUses() will ignore the instruction that is about to be
deleted, and we avoid leaving invalid live ranges that SplitKit doesn't like.
Fix a misunderstanding in MachineVerifier about <def,undef> operands. The
<undef> flag is valid on def operands where it has the same meaning as <undef>
on a use operand. It only applies to sub-register defines which also read the
full register.
llvm-svn: 128642
2011-03-31 17:23:25 +00:00
ebc34dff18
Driver/Darwin: Tweak link logic for simulator.
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llvm-svn: 128641
2011-03-31 17:12:33 +00:00
22c5560bc8
Remove stray empty test file.
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llvm-svn: 128640
2011-03-31 17:01:56 +00:00
e0cbe31ebb
Remove dead code.
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llvm-svn: 128639
2011-03-31 16:53:49 +00:00
8071f11208
Revert changes that caused this scheme to be hidden in certain cases.
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llvm-svn: 128638
2011-03-31 16:45:59 +00:00
31d8498f6f
Add code to emulate VLD1 (multiple single elements) ARM instruction.
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llvm-svn: 128637
2011-03-31 16:41:19 +00:00
890477f333
Provide a more readable error message for <atomic> until it is implemented.
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llvm-svn: 128636
2011-03-31 16:39:39 +00:00
c2452a6f1d
Revert r128632 again, until I figure out what break the tests
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llvm-svn: 128635
2011-03-31 15:54:36 +00:00
2ee5a0fc7f
Fix bug found by valgrind.
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llvm-svn: 128634
2011-03-31 15:14:11 +00:00
9a827b30ab
Add XCore intrinsics for initializing / starting / synchronizing threads.
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llvm-svn: 128633
2011-03-31 15:13:13 +00:00
4c0aebfb91
Reapply r128585 without generating a lib depedency cycle. An updated log:
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- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
addrmode2.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
llvm-svn: 128632
2011-03-31 14:52:28 +00:00
3df5c04fe4
Fix whitespace.
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llvm-svn: 128631
2011-03-31 13:06:39 +00:00
c60223ef6c
Switch FileRemover from PathV1 to V2.
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llvm-svn: 128630
2011-03-31 13:04:19 +00:00
41f32c7127
lib/CodeGen/LiveIntervalAnalysis.cpp: [PR9590] Don't use std::pow(float,float) here.
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We don't expect the real "powf()" on some hosts (and powf() would be available on other hosts).
For consistency, std::pow(double,double) may be called instead.
Or, precision issue might attack us, to see unstable regalloc and stack coloring.
llvm-svn: 128629
2011-03-31 12:11:33 +00:00
be209ab8a2
InstCombine: Fix transform to use the swapped predicate.
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Thanks Frits!
llvm-svn: 128628
2011-03-31 10:46:03 +00:00
d159d94644
InstCombine: fold fcmp (fneg x), (fneg y) -> fcmp x, y
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llvm-svn: 128627
2011-03-31 10:12:22 +00:00
Daniel Dunbar