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Author SHA1 Message Date
Sanjay Patel 69ed4710b8 [InstCombine] narrow binops on concatenated vectors (PR33026) 
The motivating case from:
https://bugs.llvm.org/show_bug.cgi?id=33026
...has no shuffles now. This kind of pattern may occur during
vectorization when targets have lumpy ISAs like SSE/AVX.

llvm-svn: 342988
 2018-09-25 15:57:37 +00:00
Sanjay Patel dfe4380440 [InstCombine] add tests for vector concat with binop (PR33026); NFC 
llvm-svn: 342665
 2018-09-20 17:10:38 +00:00