ea31737fef
Don't create a StringRef with a NULL value.
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llvm-svn: 103455
2010-05-11 01:33:39 +00:00
e276c18385
Model some vst3 and vst4 with reg_sequence.
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llvm-svn: 103453
2010-05-11 01:19:40 +00:00
a12c1ff25a
The getDefaultSubtargetFeatures method of SubtargetFeature did actually return a
...
string of features for that target. However LTO was using that string to pass
into the "create target machine" stuff. That stuff needed the feature string to
be in a particular form. In particular, it needed the CPU specified first and
then the attributes. If there isn't a CPU specified, it required it to be blank
-- e.g., ",+altivec". Yuck.
Modify the getDefaultSubtargetFeatures method to be a non-static member
function. For all attributes for a specific subtarget, it will add them in like
normal. It will also take a CPU string so that it can satisfy this horrible
syntax.
llvm-svn: 103451
2010-05-11 00:30:02 +00:00
630063aa0d
Model some vld3 instructions with REG_SEQUENCE.
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llvm-svn: 103437
2010-05-10 21:26:24 +00:00
c2ae5f546f
Model vld2 / vst2 with reg_sequence.
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llvm-svn: 103411
2010-05-10 17:34:18 +00:00
92ea401d8f
Fix encoding of 'sf' and 'sfh' instructions.
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llvm-svn: 103399
2010-05-10 08:13:49 +00:00
b19c598843
updated handling dllexport in X86AsmPrinter
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changed dllexport code to use EmitBytes instead of EmitRawText, and changed the export option to use /EXPORT: instead of -export: on the windows platform
llvm-svn: 103377
2010-05-09 08:40:06 +00:00
2760216c89
made COFF target dllexport logic apply to all subtargets
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llvm-svn: 103373
2010-05-09 05:52:28 +00:00
72afa956db
break coff symbol definition stuff out into proper MCStreamer callbacks,
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patch by Nathan Jeffords!
llvm-svn: 103346
2010-05-08 19:54:22 +00:00
2a41cad900
Clean up the conditional for handling of sign_extend_inreg based on
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whether the extract instructions are available.
rdar://7956878
llvm-svn: 103277
2010-05-07 18:34:55 +00:00
4423abd734
Use overloaded operators instead of DIDescriptor::getNode()
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llvm-svn: 103276
2010-05-07 18:19:32 +00:00
b3c5c4611c
Testing svn access with a note added to documentation.
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llvm-svn: 103271
2010-05-07 18:06:28 +00:00
87cffa9498
switch MCSectionCOFF from a syntactic to semantic representation,
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patch by Peter Housel!
llvm-svn: 103267
2010-05-07 17:17:41 +00:00
86eb22976f
Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise.
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llvm-svn: 103235
2010-05-07 02:04:02 +00:00
04d47e8efa
Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values.
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llvm-svn: 103234
2010-05-07 01:54:08 +00:00
90c600d6d2
When rematerializing, use the debug location of the original
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instruction, rather than a location near where the new instruction
is being inserted.
llvm-svn: 103232
2010-05-07 01:28:10 +00:00
ddc93c7e04
Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers.
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llvm-svn: 103218
2010-05-07 00:24:52 +00:00
21aa523c28
MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand.
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- This fixes "leal 0, %eax", for example.
llvm-svn: 103205
2010-05-06 22:39:14 +00:00
348dc9b15a
fix rdar://7947167 - llvm-mc doesn't match movsq
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llvm-svn: 103199
2010-05-06 21:48:14 +00:00
e7e1cf9fbd
Eliminated the classification of control registers into %ecr_
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and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.
llvm-svn: 103196
2010-05-06 20:59:00 +00:00
358b29c855
MC/X86: Error out if we see a non-constant FK_Data_1 or FK_Data_2 fixup, since
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we don't currently support relaxing them.
llvm-svn: 103195
2010-05-06 20:34:01 +00:00
779c69bbc5
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
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doesn't have to guess.
llvm-svn: 103194
2010-05-06 20:33:48 +00:00
efb126a665
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
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llvm-svn: 103193
2010-05-06 19:06:44 +00:00
f765e1f34a
Add a missing break statement to fix unintentional fall-through
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(replacing the previous patch for the same issue).
llvm-svn: 103183
2010-05-06 16:05:26 +00:00
5e3cccb1e4
Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com>
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llvm-svn: 103181
2010-05-06 15:32:49 +00:00
94231eec1f
Fix "warning: extra ';' inside a struct or union" when building llvm with clang
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llvm-svn: 103179
2010-05-06 14:57:47 +00:00
31cdcd46d6
Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.
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llvm-svn: 103172
2010-05-06 06:36:08 +00:00
77c71811f5
Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll.
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llvm-svn: 103163
2010-05-06 05:08:57 +00:00
9feb1bb117
Revert r103156 since it was breaking the build bots.
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Reverse-merging r103156 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMRegisterInfo.h
U lib/Target/ARM/ARMBaseRegisterInfo.cpp
U lib/Target/ARM/ARMBaseInstrInfo.cpp
U lib/Target/ARM/ARMRegisterInfo.td
llvm-svn: 103159
2010-05-06 02:29:06 +00:00
8fd7b510d6
Fix an obvious bug in isMoveInstr. It needs to return sub-register indices.
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llvm-svn: 103157
2010-05-06 01:54:03 +00:00
8f99a1c6b4
Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them.
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llvm-svn: 103156
2010-05-06 01:52:03 +00:00
9d768f4445
Cosmetic changes.
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llvm-svn: 103155
2010-05-06 01:34:11 +00:00
718ff448df
storeRegToStackSlot has forgotten about QPR_8 register class.
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llvm-svn: 103154
2010-05-06 01:32:54 +00:00
151cd8f159
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
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instructions to subtarget features and update tests to reflect.
PR5717.
llvm-svn: 103136
2010-05-05 23:44:43 +00:00
4cd930f417
Fixed a sign-extension bug in the X86 disassembler
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that was causing PC-relative branch targets to be
evaluated incorrectly. Also added support for
checking operand values to the llvm-mc tester.
llvm-svn: 103128
2010-05-05 22:47:27 +00:00
61908f6b6c
Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order.
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llvm-svn: 103124
2010-05-05 22:15:40 +00:00
f62cd20b62
No-ops emitted for scheduling don't correspond with anything in the
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user's source, so don't arbitrarily assign them a debug location.
llvm-svn: 103121
2010-05-05 20:58:01 +00:00
92d999001c
Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by
...
Jordy <snhjordy@gmail.com>.
Followup patches will add some tests and adjust to use Subtarget features
for the instructions.
llvm-svn: 103119
2010-05-05 20:44:35 +00:00
d85631e700
Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.
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llvm-svn: 103104
2010-05-05 18:28:36 +00:00
5ab29366b5
Trim include.
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llvm-svn: 103103
2010-05-05 18:27:57 +00:00
4e7e4e6b60
Revert 102941, we're going to do this via attr and can just
...
hack the code to turn it off when debugging.
llvm-svn: 103083
2010-05-05 07:35:59 +00:00
a00830df31
Update comment.
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llvm-svn: 103057
2010-05-04 22:13:03 +00:00
8e6b40a881
With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE.
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llvm-svn: 103047
2010-05-04 20:39:49 +00:00
a3a7b0099c
Do not pre-allocate for registers which form a REG_SEQUENCE.
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llvm-svn: 103041
2010-05-04 20:38:12 +00:00
0185047b3f
"on the rare occasion the SPU BE produces illegal assembly - it tries to emit an add instruction of the form 'a reg, reg, imm'."
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Patch by Kalle Raiskila!
llvm-svn: 103021
2010-05-04 17:58:46 +00:00
c3e0bafc6d
MC/X86: Chris pointed that 'as' isn't consistent in accepting the long form of
...
instructions which have no direct register usage.
Darwin 'as' accepts:
add $0, (%rax)
but rejects
mov $0, (%rax)
for example.
Given that, only accept suffix matches which match exactly one form. We still
need to emit nice diagnostics for failures...
llvm-svn: 103015
2010-05-04 17:31:02 +00:00
9b816a1bb3
MC/X86: Add "support" for matching ATT style mnemonic prefixes.
...
- The idea is that when a match fails, we just try to match each of +'b', +'w',
+'l'. If exactly one matches, we assume this is a mnemonic prefix and accept
it. If all match, we assume it is width generic, and take the 'l' form.
- This would be a horrible hack, if it weren't so simple. Therefore it is an
elegant solution! Chris gets the credit for this particular elegant
solution. :)
- Next step to making this more robust is to have the X86 matcher generate the
mnemonic prefix information. Ideally we would also compute up-front exactly
which mnemonic to attempt to match, but this may require more custom code in
the matcher than is really worth it.
llvm-svn: 103012
2010-05-04 16:12:42 +00:00
4c0f838637
fix operand indexes when outputting InvokeInsts
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llvm-svn: 103003
2010-05-04 09:23:54 +00:00
8f0037097f
Fix to r102952. The MOV64toSDrm record in X86Instr64bit.td needed the opcode
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changed to 0x7E from 0x6E as well as the previous change of RPDI to S3SI.
llvm-svn: 102991
2010-05-04 00:42:46 +00:00
30e637c9bc
rdar://7937137 - dbg values not being handled in thumb1 version of
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eliminateFrameIndex(), leading to llvm_unreachable() assertion failure.
llvm-svn: 102980
2010-05-04 00:11:37 +00:00
Bill Wendling