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571 Commits

Author SHA1 Message Date
Duncan Sands 283207a71c Eliminate the remaining uses of getTypeSize. This 
should only effect x86 when using long double.  Now
12/16 bytes are output for long double globals (the
exact amount depends on the alignment).  This brings
globals in line with the rest of LLVM: the space
reserved for an object is now always the ABI size.
One tricky point is that only 10 bytes should be
output for long double if it is a field in a packed
struct, which is the reason for the additional
argument to EmitGlobalConstant.

llvm-svn: 43688
 2007-11-05 00:04:43 +00:00
Rafael Espindola 419b6d7ce4 Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold 
and by restructuring the X86 version.

New I just have to move this to a common place :-)

llvm-svn: 43554
 2007-10-31 14:39:58 +00:00
Rafael Espindola 063f177300 Make ARM an X86 memcpy expansion more similar to each other. 
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.

This should not change generated code.

llvm-svn: 43552
 2007-10-31 11:52:06 +00:00
Dale Johannesen 65e804a9c3 Support non-POSIX hosts by removing use of strncasecmp. 
llvm-svn: 43364
 2007-10-25 21:54:43 +00:00
Evan Cheng 1f2dd35898 Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4. 
llvm-svn: 43234
 2007-10-22 22:11:27 +00:00
Rafael Espindola 18a831d783 split LowerMEMCPY into LowerMEMCPYCall and LowerMEMCPYInline in the ARM backend. 
llvm-svn: 43176
 2007-10-19 14:35:17 +00:00
Chris Lattner 5d979d57ae Add an easy microoptimization I noticed. 
llvm-svn: 43164
 2007-10-19 03:29:26 +00:00
Evan Cheng 463e2ab0ac - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding. 
- Fix some copy+paste bugs.

llvm-svn: 43153
 2007-10-18 22:40:57 +00:00
Evan Cheng aa9a225699 Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface. 
llvm-svn: 43150
 2007-10-18 21:29:24 +00:00
Christopher Lamb 79dfbed6f6 Fix a misnamed parameter. 
llvm-svn: 43145
 2007-10-18 19:29:45 +00:00
Chris Lattner 84f3461c49 legalizing the ret operation on f64 shouldn't introduce a new 
i64 bit convert needlessly.

llvm-svn: 43116
 2007-10-18 06:17:07 +00:00
Evan Cheng cdf3609130 Revert 42908 for now. 
llvm-svn: 42960
 2007-10-14 05:57:21 +00:00
Dan Gohman dc35bd79ca Change the names used for internal labels to use the current 
function symbol name instead of a codegen-assigned function
number.

Thanks Evan! :-)

llvm-svn: 42908
 2007-10-12 14:53:36 +00:00
Dan Gohman 482732af9d Set ISD::FPOW to Expand. 
llvm-svn: 42881
 2007-10-11 23:21:31 +00:00
Dan Gohman a160361c85 Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to 
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.

llvm-svn: 42762
 2007-10-08 18:33:35 +00:00
Evan Cheng f4cf5dcdd2 - Added a few target hooks to generate load / store instructions from / to any 
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.

llvm-svn: 42621
 2007-10-05 01:32:41 +00:00
Dan Gohman c731c97fac Use empty() member functions when that's what's being tested for instead 
of comparing begin() and end().

llvm-svn: 42585
 2007-10-03 19:26:29 +00:00
Gordon Henriksen 0b7cf862bc AsmPrinters overriding getAnalysisUsage should call super. 
And not super's super, either.

llvm-svn: 42482
 2007-09-30 13:39:29 +00:00
Evan Cheng c1e4e3743b Allow copyRegToReg to emit cross register classes copies. 
Tested with "make check"!

llvm-svn: 42346
 2007-09-26 06:25:56 +00:00
Dan Gohman 57211c5550 More explicit keywords. 
llvm-svn: 42316
 2007-09-25 20:27:06 +00:00
Evan Cheng 1ff71872c2 Honor user-defined section specification of a global, ignores whether its initializer is null. 
llvm-svn: 42182
 2007-09-21 00:41:19 +00:00
Evan Cheng 8010320365 Enable if-conversion for ARM by default. 
llvm-svn: 42156
 2007-09-20 00:48:22 +00:00
Evan Cheng d0e360e16e Avoid referencing deleted instruction. 
llvm-svn: 42153
 2007-09-19 21:48:07 +00:00
Dan Gohman 9da02f5ee2 Remove isReg, isImm, and isMBB, and change all their users to use 
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.

llvm-svn: 41958
 2007-09-14 20:33:02 +00:00
Bill Wendling 66c22e8fd6 Enable indirect encoding for the personality function 
llvm-svn: 41873
 2007-09-11 23:55:40 +00:00
Evan Cheng 3e18e504ae Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
llvm-svn: 41863
 2007-09-11 19:55:27 +00:00
Duncan Sands 86e0119822 Fold the adjust_trampoline intrinsic into 
init_trampoline.  There is now only one
trampoline intrinsic.

llvm-svn: 41841
 2007-09-11 14:10:23 +00:00
Evan Cheng f948772f9e 80 col. 
llvm-svn: 41812
 2007-09-10 22:22:23 +00:00
Chris Lattner 6777b72659 Add some notes about better flag handling. 
llvm-svn: 41808
 2007-09-10 21:43:18 +00:00
Owen Anderson e2f23a3abf Add lengthof and endof templates that hide a lot of sizeof computations. 
Patch by Sterling Stein!

llvm-svn: 41758
 2007-09-07 04:06:50 +00:00
Dale Johannesen 3cf889f75e Enhance APFloat to retain bits of NaNs (fixes oggenc). 
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.

llvm-svn: 41632
 2007-08-31 04:03:46 +00:00
Raul Herbster ab871baaf8 Instruction formats added used to generate multiply instructions of V5TE. 
llvm-svn: 41629
 2007-08-30 23:34:14 +00:00
Raul Herbster ff32b62942 Unused relocation type reloc_arm_absolute removed. 
llvm-svn: 41628
 2007-08-30 23:31:35 +00:00
Raul Herbster 1457b2b3b1 Comments added. It now generates V5TE multiply instructions. However, it is still necessary to model PUWLSH bits more clearly. 
llvm-svn: 41627
 2007-08-30 23:29:26 +00:00
Raul Herbster 73489273ae ARM instruction table was modified by adding information to generate multiply instruction of V5TE. 
llvm-svn: 41626
 2007-08-30 23:25:47 +00:00
Raul Herbster ae1b924c79 JITInfo now resolves function addrs and also relocations. It always emits a stub. 
llvm-svn: 41625
 2007-08-30 23:21:27 +00:00
Evan Cheng 9a25d98c86 Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots. 
llvm-svn: 41597
 2007-08-30 05:52:20 +00:00
Evan Cheng f7c6effc44 Initial JIT support for ARM by Raul Fernandes Herbster. 
llvm-svn: 40887
 2007-08-07 01:37:15 +00:00
Dan Gohman 5f6a9da530 More explicit keywords. 
llvm-svn: 40757
 2007-08-02 21:21:54 +00:00
Evan Cheng aa39b39eec Indexed loads each has 2 outputs. 
llvm-svn: 40658
 2007-08-01 00:12:08 +00:00
Dan Gohman e379f08b19 More explicit keywords. 
llvm-svn: 40589
 2007-07-30 14:51:59 +00:00
Duncan Sands 644f917358 Support for trampolines, except for X86 codegen which is 
still under discussion.

llvm-svn: 40549
 2007-07-27 12:58:54 +00:00
Dan Gohman cf0a5349de Don't ignore the return value of AsmPrinter::doInitialization and 
AsmPrinter::doFinalization.

llvm-svn: 40487
 2007-07-25 19:33:14 +00:00
Evan Cheng ac1591be42 No more noResults. 
llvm-svn: 40132
 2007-07-21 00:34:19 +00:00
Evan Cheng 9d5df0a5f6 Added -print-emitted-asm to print out JIT generated asm to cerr. 
llvm-svn: 40123
 2007-07-20 21:56:13 +00:00
Evan Cheng 94b5a80b93 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Evan Cheng 22b0c344db Only adjust esp around calls in presence of alloca. 
llvm-svn: 40030
 2007-07-19 00:42:58 +00:00
Chris Lattner 396156e00b no email addrs in file headers 
llvm-svn: 39962
 2007-07-17 05:56:43 +00:00
Anton Korobeynikov 383a324735 Long live the exception handling! 
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.

llvm-svn: 39855
 2007-07-14 14:06:15 +00:00
Dale Johannesen 85ee72f7ba ARM: make branch folder remove unconditional branches 
following jump tables that it earlier inserted.  This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).

llvm-svn: 39782
 2007-07-12 16:45:35 +00:00