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10 Commits

Author SHA1 Message Date
Shiva Chen 7c17242b92 [RISCV] Implement c.lui immediate operand constraint 
Implement c.lui immediate constraint to [1, 31] and [0xfffe0, 0xfffff].
The RISC-V ISA describes the constraint as [1, 63], with that value
being loaded in to bits 17-12 of the destination register and sign extended
from bit 17. Therefore, this 6-bit immediate can represent values in the
ranges [1, 31] and [0xfffe0, 0xfffff].

Differential Revision: https://reviews.llvm.org/D42834

llvm-svn: 325792
 2018-02-22 15:02:28 +00:00
Shiva Chen b22c1d29bc [RISCV] Fix c.addi and c.addi16sp immediate constraints which should be non-zero 
Differential Revision: https://reviews.llvm.org/D42782

llvm-svn: 324055
 2018-02-02 02:43:23 +00:00
Ana Pazos 1b57c7a0f4 [RISCV] Fixed setting predicates for compressed instructions. 
Summary:
Fixed setting predicates for compressed instructions.
Some instructions were being generated with C extension
enabled only, without proper checks for the other
required extensions like F, D and 32 and 64-bit target checks.
Affected instructions:
C_FLD, C_FLW, C_LD, C_FSD, C_FSW, C_SD,
C_JAL, C_ADDIW, C_SUBW, C_ADDW,
C_FLDSP, C_FLWSP, C_LDSP, C_FSDSP, C_FSWSP, C_SDSP

Reviewers: asb, shiva0217

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, llvm-commits

Differential Revision: https://reviews.llvm.org/D42132

llvm-svn: 322876
 2018-01-18 18:54:05 +00:00
Alex Bradbury 8cb894b34b [RISCV] Add Defs Uses information for c.jal and c.addi4spn 
Differential Revision: https://reviews.llvm.org/D41339
Patch by Shiva Chen.

llvm-svn: 321643
 2018-01-02 12:09:29 +00:00
Alex Bradbury 0ad4c265d7 [RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero 
c.slli/c.srli/c.srai allow a 5-bit shift in RV32C and a 6-bit shift in RV64C.
This patch adds uimmlog2xlennonzero to reflect this constraint as well as
tests.

Differential Revision: https://reviews.llvm.org/D41216

Patch by Shiva Chen.

llvm-svn: 320799
 2017-12-15 10:20:51 +00:00
Alex Bradbury 19c9314aea [RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming convention 
When an instruction mnemonic contains a '.', we usually name the instruction
with a _ in that place. e.g. fadd.s -> FADD_S.

This patch updates RISCVInstrInfoC.td to do the same, e.g. c.nop -> C_NOP.

Also includes some minor formatting changes in RISCVInstrInfoC.td to better
align it with the formatting conventions in the rest of the backend.

llvm-svn: 320560
 2017-12-13 09:57:25 +00:00
Alex Bradbury 581d6b081d [RISCV][NFC] Put isSImm6 and simm6 td definition in correct sorted position 
We sort these helper functions and td definitions by bit width. simm6 was
previously out-of-order with respect to the others.

llvm-svn: 320559
 2017-12-13 09:41:21 +00:00
Alex Bradbury 60714f98ba [RISCV] MC layer support for the remaining RVC instructions 
Differential Revision: https://reviews.llvm.org/D40003

Patch by Shiva Chen.

llvm-svn: 320558
 2017-12-13 09:32:55 +00:00
Alex Bradbury f8f4b90544 [RISCV] MC layer support for the jump/branch instructions of the RVC extension 
Differential Revision: https://reviews.llvm.org/D40002
    
Patch by Shiva Chen.

llvm-svn: 320038
 2017-12-07 13:19:57 +00:00
Alex Bradbury 9f6aec4b7a [RISCV] MC layer support for load/store instructions of the C (compressed) extension 
Differential Revision: https://reviews.llvm.org/D40001
    
Patch by Shiva Chen.

llvm-svn: 320037
 2017-12-07 12:50:32 +00:00