Commit Graph

3795 Commits

Author SHA1 Message Date
Craig Topper 322b67f961 [TableGen] Replace a logically negated xor of bools with just an equality comparison for readability. NFC
llvm-svn: 256699
2016-01-03 07:33:39 +00:00
Craig Topper 58a0e7a0d3 [TableGen] Use std::find_if and a lambda instead of manual loops.
llvm-svn: 256698
2016-01-03 07:33:36 +00:00
Craig Topper f58323ef29 [TableGen] Fix a bug introduced in r256627. If the switch was not emitted we still emitted a closing curly brace.
llvm-svn: 256697
2016-01-03 07:33:34 +00:00
Craig Topper 6e526f13f5 [TableGen] Use range-based for loops. NFC
llvm-svn: 256696
2016-01-03 07:33:30 +00:00
Craig Topper fd2c6a3be0 [TableGen] Modify the AsmMatcherEmitter to only apply the table growth from r252440 to the Hexagon target.
This restores the previous behavior of not including the mnemonic in the classes table for every target that starts instruction lines with the mnemonic. Not only did the table size increase by 1 entry, but the class enum increased in size which caused every class in the array to increase in size. It also grew the size of the function that parsers tokens into classes by a substantial amount.

This adds a new HasMnemonicFirst flag to all AsmParsers. It's set to 1 by default and Hexagon target overrides it to 0.

For the X86 target alone this recovers 324KB of size on the llvm-mc executable.

I believe the current state is still a bad design choice for the Hexagon target as it causes most of the parsing to do a linear search through the entire match table to comparing operands against every instruction until it finds one that works. At least for the other targets we do a binary search based on mnemonic over which to do the linear scan.

llvm-svn: 256669
2015-12-31 08:18:23 +00:00
Craig Topper 869cd5f1c8 [TableGen] Use range-based for loops. NFC
llvm-svn: 256668
2015-12-31 08:18:20 +00:00
Craig Topper bc22e26e38 [TableGen] Move determination of IsIsolatedToken into the tokenizer instead of trying to search characters around the token. No functional change intended. Verified for in-tree targets.
llvm-svn: 256660
2015-12-31 05:01:45 +00:00
Craig Topper 13b2a4e35d [TableGen] Remove unnecessary conversion from StringRef to std::string when outputting to a raw_ostream. NFC
llvm-svn: 256628
2015-12-30 06:00:24 +00:00
Craig Topper 39311c7ed5 [TableGen] Remove raw_string_ostream by just emitting the header for the switch the first time we emit a case. If the header was never emitted just print the default at the end. NFC
llvm-svn: 256627
2015-12-30 06:00:22 +00:00
Craig Topper 77bd2b7581 [TableGen] Use range-based for loops. NFC
llvm-svn: 256626
2015-12-30 06:00:20 +00:00
Craig Topper c8b5b255f7 [TableGen] Move more things that come from variant into the AsmVariantInfo class so we can reduce some parameters. NFC
llvm-svn: 256625
2015-12-30 06:00:18 +00:00
Craig Topper ba61432a9f [TableGen] Use 'size_t' instead of 'unsigned' to better match the argument types of addAsmOperand. Simplify some code by using StringRef::find instead of std::find. These were previously done in r247527 and r247528, but another commit seems to have erased them. NFC
llvm-svn: 256624
2015-12-30 06:00:15 +00:00
Craig Topper 3661c62e4b De-virtualize mnemonicIsValid and remove from the base class. It's not called by any common code.
llvm-svn: 256544
2015-12-29 07:43:03 +00:00
Craig Topper 884409a552 [TableGen] Add missing space to output.
llvm-svn: 256540
2015-12-29 07:03:25 +00:00
Craig Topper e4e7415705 [TableGen] Use range-based for loops. NFC
llvm-svn: 256539
2015-12-29 07:03:23 +00:00
Asaf Badouh 9a5a83a518 [X86][PKU] Add {RD,WR}PKRU encoding
Differential Revision: http://reviews.llvm.org/D15711

llvm-svn: 256366
2015-12-24 08:25:00 +00:00
Akira Hatanaka 1cb242eb13 Provide a way to specify inliner's attribute compatibility and merging.
This reapplies r256277 with two changes:

- In emitFnAttrCompatCheck, change FuncName's type to std::string to fix
  a use-after-free bug.
- Remove an unnecessary install-local target in lib/IR/Makefile. 

Original commit message for r252949:

Provide a way to specify inliner's attribute compatibility and merging
rules using table-gen. NFC.

This commit adds new classes CompatRule and MergeRule to Attributes.td,
which are used to generate code to check attribute compatibility and
merge attributes of the caller and callee.

rdar://problem/19836465

llvm-svn: 256304
2015-12-22 23:57:37 +00:00
Dan Gohman db70d015ad Add an OperandNamespace field to Target.td's Operand.
For targets to add their own operand types as needed, as advertised in
Operand's comment, they need to be able to specify an alternate namespace
for OperandType names too. This matches the RegisterOperand class.

llvm-svn: 256299
2015-12-22 23:37:37 +00:00
Akira Hatanaka 9c05cc5670 Revert r256277 and r256279.
Some of the bots failed again.

llvm-svn: 256280
2015-12-22 20:29:09 +00:00
Akira Hatanaka a61deb249b Provide a way to specify inliner's attribute compatibility and merging.
This reapplies r252990 and r252949. I've added member function getKind
to the Attr classes which returns the enum or string of the attribute.

Original commit message for r252949:

Provide a way to specify inliner's attribute compatibility and merging
rules using table-gen. NFC.

This commit adds new classes CompatRule and MergeRule to Attributes.td,
which are used to generate code to check attribute compatibility and
merge attributes of the caller and callee.

rdar://problem/19836465

llvm-svn: 256277
2015-12-22 20:00:05 +00:00
Chih-Hung Hsieh 7993e18e80 [X86] Part 2 to fix x86-64 fp128 calling convention.
Part 1 was submitted in http://reviews.llvm.org/D15134.
Changes in this part:
* X86RegisterInfo.td, X86RecognizableInstr.cpp: Add FR128 register class.
* X86CallingConv.td: Pass f128 values in XMM registers or on stack.
* X86InstrCompiler.td, X86InstrInfo.td, X86InstrSSE.td:
  Add instruction selection patterns for f128.
* X86ISelLowering.cpp:
  When target has MMX registers, configure MVT::f128 in FR128RegClass,
  with TypeSoftenFloat action, and custom actions for some opcodes.
  Add missed cases of MVT::f128 in places that handle f32, f64, or vector types.
  Add TODO comment to support f128 type in inline assembly code.
* SelectionDAGBuilder.cpp:
  Fix infinite loop when f128 type can have
  VT == TLI.getTypeToTransformTo(Ctx, VT).
* Add unit tests for x86-64 fp128 type.

Differential Revision: http://reviews.llvm.org/D11438

llvm-svn: 255558
2015-12-14 22:08:36 +00:00
Hal Finkel cd5f984670 [TableGen] Correct Namespace lookup with AltNames in AsmWriterEmitter
AsmWriterEmitter will generate a getRegisterName function with an alternate
register name index as its second argument if the target makes use of them. The
enum of these values is generated in RegisterInfoEmitter. The getRegisterName
generator would assume the namespace could always be found by reading index 1
of the list of AltNameIndices, but this will fail if this list is sorted such
that the NoRegAltName is at index 1. Because this list is sorted by record name
(in CodeGenTarget::ReadRegAltNameIndices), you only run in to problems if your
MyTargetRegisterInfo.td defines a single RegAltNameIndex that sorts lexically
before NoRegAltName.

For example, if a target has something like

  def AnAltNameIndex : RegAltNameIndex

and defines RegAltNameIndices for some registers then, prior to this change,
AsmWriterEmitter would generate references to

  ::AnAltNameIndex and ::NoRegAltName

Patch by Alex Bradbury!

llvm-svn: 255344
2015-12-11 17:31:27 +00:00
Craig Topper 15576e1c8f Use make_range to reduce mentions of iterator type. NFC
llvm-svn: 254872
2015-12-06 05:08:07 +00:00
Craig Topper e5e035a3a8 Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical register arrays already use this typedef.
llvm-svn: 254843
2015-12-05 07:13:35 +00:00
Craig Topper 1282df50c4 [TableGen] Remove an assumption about the order of encodings in the MVT::SimpleValueType enum. Instead of assuming the types are sorted by size, scan the typeset arrays to find the smallest/largest type. NFC
llvm-svn: 254589
2015-12-03 05:57:37 +00:00
Oliver Stannard a34e47066e [AArch64] Add ARMv8.2-A Statistical Profiling Extension
The Statistical Profiling Extension is an optional extension to
ARMv8.2-A. Since it is an optional extension, I have added the
FeatureSPE subtarget feature to control it. The assembler-visible parts
of this extension are the new "psb csync" instruction, which is
equivalent to "hint #17", and a number of system registers.

Differential Revision: http://reviews.llvm.org/D15021

llvm-svn: 254401
2015-12-01 10:48:51 +00:00
Craig Topper 3522ab30db [TableGen] Use SmallString instead of std::string to build up a string to avoid heap allocations. NFC
llvm-svn: 254221
2015-11-28 08:23:02 +00:00
Craig Topper 8985efe546 [TableGen] Sort pattern predicates before concatenating into a string so that different orders of the same set will produce the same string. This can reduce the number of unique predicates in the isel tables. NFC
llvm-svn: 254192
2015-11-27 05:44:04 +00:00
Craig Topper 9a44b3fa58 [SelectionDAG] Add a SDTCisSameSizeAs type constraint that can be used to ensure vector widths match even if the element size and count don't.
llvm-svn: 254138
2015-11-26 07:02:18 +00:00
Craig Topper 25ce6b82c6 [TableGen] Flip reversed comments.
llvm-svn: 254136
2015-11-26 06:30:40 +00:00
Krzysztof Parzyszek b8bb90b744 Add vector types for intrinsics
Author: Ron Lieberman <ronl@codeaurora.org>
llvm-svn: 253992
2015-11-24 16:28:14 +00:00
Krzysztof Parzyszek 47c1baeb1f Add names for the new vector types in CodeGenTarget.cpp
llvm-svn: 253989
2015-11-24 15:50:22 +00:00
Craig Topper 5712d46114 [TableGen] Use std::remove_if instead of manually coded loops that call erase multiple times. NFC
llvm-svn: 253964
2015-11-24 08:20:47 +00:00
Craig Topper 16f1cbd1e4 [TableGen] Use the other version of EnforceVectorEltTypeIs inside the TypeSet version of EnforceVectorEltTypeIs to reduce duplicated code. NFC
llvm-svn: 253963
2015-11-24 08:20:45 +00:00
Craig Topper dbfcc10e44 [TableGen] Fix formatting and use logical OR. NFC
llvm-svn: 253962
2015-11-24 08:20:44 +00:00
Craig Topper fef745c36a [TableGen] Use std::set_intersection to merge TypeSets. NFC
llvm-svn: 253961
2015-11-24 08:20:42 +00:00
Craig Topper 4856c81b46 [TableGen] Use SmallVector::assign instead of a resize and replace element.
llvm-svn: 253960
2015-11-24 08:20:41 +00:00
Craig Topper d324d75102 Revert change that accidentally snuck into r253955.
llvm-svn: 253956
2015-11-24 06:24:06 +00:00
Craig Topper 030418802a [TableGen] Use array_pod_sort. NFC
llvm-svn: 253955
2015-11-24 06:22:43 +00:00
Craig Topper de2d7593a2 [TableGen] Use std::remove_if instead of manually coded loops that called erase inside them. NFC
llvm-svn: 253857
2015-11-23 07:19:10 +00:00
Craig Topper d2177de61a [TableGen] Use empty() instead of checking if size of vector is greater than or equal to 1.
llvm-svn: 253856
2015-11-23 07:19:08 +00:00
Craig Topper 2f70a7ef57 Revert a portion of r253836 that seems to have broke a couple bots.
llvm-svn: 253838
2015-11-22 22:43:40 +00:00
Craig Topper 306cb12286 [TableGen] Use range-based for loops. NFC
llvm-svn: 253836
2015-11-22 20:46:24 +00:00
Craig Topper 43c414f31b [TableGen] Use std::fill instead of a manually coded loop. NFC
llvm-svn: 253835
2015-11-22 20:46:22 +00:00
David Blaikie fda69dd736 Further simplify from r253832 with some unique_ptr and coalescing conditions
llvm-svn: 253834
2015-11-22 20:11:21 +00:00
David Blaikie b8fc0186c7 Further simplify from r253832, removing unnecessary intermediate lambdas
llvm-svn: 253833
2015-11-22 20:02:58 +00:00
Craig Topper cbdc27eb74 [TableGen] Use std::any_of and std::find instead of manual loops. NFC
llvm-svn: 253832
2015-11-22 19:27:02 +00:00
Krzysztof Parzyszek 6753f33388 Avoid dependency between TableGen and CodeGen
Duplicate a few common definitions between DFAPacketizer.cpp and
DFAPacketizerEmitter.cpp to avoid including files from CodeGen
in TableGen.

llvm-svn: 253820
2015-11-22 15:20:19 +00:00
Krzysztof Parzyszek dd1352499c Now fix errors in NDEBUG build.
Hope this won't break any hardware next.

llvm-svn: 253799
2015-11-21 22:46:52 +00:00
Krzysztof Parzyszek 8dd552db29 Fix warnings in NDEBUG build
llvm-svn: 253798
2015-11-21 22:19:50 +00:00
Krzysztof Parzyszek b46557292c Hexagon V60/HVX DFA scheduler support
Extended DFA tablegen to:
  - added "-debug-only dfa-emitter" support to llvm-tblgen

  - defined CVI_PIPE* resources for the V60 vector coprocessor

  - allow specification of multiple required resources
    - supports ANDs of ORs
    - e.g. [SLOT2, SLOT3], [CVI_MPY0, CVI_MPY1] means:
           (SLOT2 OR SLOT3) AND (CVI_MPY0 OR CVI_MPY1)

  - added support for combo resources
    - allows specifying ORs of ANDs
    - e.g. [CVI_XLSHF, CVI_MPY01] means:
           (CVI_XLANE AND CVI_SHIFT) OR (CVI_MPY0 AND CVI_MPY1)

  - increased DFA input size from 32-bit to 64-bit
    - allows for a maximum of 4 AND'ed terms of 16 resources

  - supported expressions now include:

    expression     => term [AND term] [AND term] [AND term]
    term           => resource [OR resource]*
    resource       => one_resource | combo_resource
    combo_resource => (one_resource [AND one_resource]*)

Author: Dan Palermo <dpalermo@codeaurora.org>

kparzysz: Verified AMDGPU codegen to be unchanged on all llc
tests, except those dealing with instruction encodings.

Reapply the previous patch, this time without circular dependencies.

llvm-svn: 253793
2015-11-21 20:00:45 +00:00
Krzysztof Parzyszek 4ca21fc1aa Revert r253790: it breaks all builds for some reason.
llvm-svn: 253791
2015-11-21 17:38:33 +00:00
Krzysztof Parzyszek 220a9bc018 Hexagon V60/HVX DFA scheduler support
Extended DFA tablegen to:
  - added "-debug-only dfa-emitter" support to llvm-tblgen

  - defined CVI_PIPE* resources for the V60 vector coprocessor

  - allow specification of multiple required resources
    - supports ANDs of ORs
    - e.g. [SLOT2, SLOT3], [CVI_MPY0, CVI_MPY1] means:
           (SLOT2 OR SLOT3) AND (CVI_MPY0 OR CVI_MPY1)

  - added support for combo resources
    - allows specifying ORs of ANDs
    - e.g. [CVI_XLSHF, CVI_MPY01] means:
           (CVI_XLANE AND CVI_SHIFT) OR (CVI_MPY0 AND CVI_MPY1)

  - increased DFA input size from 32-bit to 64-bit
    - allows for a maximum of 4 AND'ed terms of 16 resources

  - supported expressions now include:

    expression     => term [AND term] [AND term] [AND term]
    term           => resource [OR resource]*
    resource       => one_resource | combo_resource
    combo_resource => (one_resource [AND one_resource]*)

Author: Dan Palermo <dpalermo@codeaurora.org>

kparzysz: Verified AMDGPU codegen to be unchanged on all llc
tests, except those dealing with instruction encodings.

llvm-svn: 253790
2015-11-21 17:23:52 +00:00
Rafael Espindola 55512f9b25 Default SetVector to use a DenseSet.
We use to have an odd difference among MapVector and SetVector. The map
used a DenseMop, but the set used a SmallSet, which in turn uses a
std::set.

I have changed SetVector to use a DenseSet. If you were depending on the
old behaviour you can pass an explicit set type or use SmallSetVector.
The common cases for needing to do it are:

* Optimizing for small sets.
* Sets for types not supported by DenseSet.

llvm-svn: 253439
2015-11-18 06:52:18 +00:00
Matthias Braun fe9d6f211f Assume lane masks are always precise
Allowing imprecise lane masks in case of more than 32 sub register lanes
lead to some tricky corner cases, and I need another bugfix for another
one. Instead I rather declare lane masks as precise and let tablegen
abort if we do not have enough bits.

This does not affect any in-tree target, even AMDGPU only needs 16 lanes
at the moment. If the 32 lanes turn out to be a problem in the future,
then we can easily change the LaneBitmask typedef to uint64_t.

Differential Revision: http://reviews.llvm.org/D14557

llvm-svn: 253279
2015-11-17 00:50:55 +00:00
Akira Hatanaka bd9fc28444 [MCTargetAsmParser] Move the member varialbes that reference
MCSubtargetInfo in the subclasses into MCTargetAsmParser and define a
member function getSTI.

This is done in preparation for making changes to shrink the size of
MCRelaxableFragment. (see http://reviews.llvm.org/D14346).

llvm-svn: 253124
2015-11-14 05:20:05 +00:00
Matthias Braun 167cbd2167 tablegen: Add a simple heuristic to get better names for pressure sets
Differential Revision: http://reviews.llvm.org/D14597

llvm-svn: 253095
2015-11-13 22:30:27 +00:00
Akira Hatanaka 5af7ace4ee Revert r252990.
Some of the buildbots are still failing.

llvm-svn: 252999
2015-11-13 01:44:32 +00:00
Akira Hatanaka c7dfb76fe7 Provide a way to specify inliner's attribute compatibility and merging.
This reapplies r252949. I've changed the type of FuncName to be
std::string instead of StringRef in emitFnAttrCompatCheck.

Original commit message for r252949:

Provide a way to specify inliner's attribute compatibility and merging
rules using table-gen. NFC.

This commit adds new classes CompatRule and MergeRule to Attributes.td,
which are used to generate code to check attribute compatibility and
merge attributes of the caller and callee.

rdar://problem/19836465

llvm-svn: 252990
2015-11-13 01:23:11 +00:00
Akira Hatanaka f3aa82f666 Revert r252949.
It broke some of the bots including clang-x64-ninja-win7.

llvm-svn: 252951
2015-11-12 21:19:18 +00:00
Akira Hatanaka 61b81a563a Provide a way to specify inliner's attribute compatibility and merging
rules using table-gen. NFC.

This commit adds new classes CompatRule and MergeRule to Attributes.td,
which are used to generate code to check attribute compatibility and
merge attributes of the caller and callee.

rdar://problem/19836465

llvm-svn: 252949
2015-11-12 20:59:43 +00:00
Akira Hatanaka d932679c71 Move the enum attributes defined in Attributes.h to a table-gen file.
This is a step towards consolidating some of the information regarding
attributes in a single place.

This patch moves the enum attributes in Attributes.h to the table-gen
file. Additionally, it adds definitions of target independent string
attributes that will be used in follow-up commits by the inliner to
check attribute compatibility.

rdar://problem/19836465

llvm-svn: 252796
2015-11-11 20:35:42 +00:00
Matthias Braun 4353b30542 TableGen: Emit LaneMask for register classes without subregisters as ~0u
This makes it slightly easier to handle classes with and without
subregister uniformly.

llvm-svn: 252671
2015-11-10 23:23:05 +00:00
Colin LeMahieu 23403c277a [AsmParser] Generalize matching for grammars without mnemonic-lead statements
Differential Revision: http://reviews.llvm.org/D14257

llvm-svn: 252440
2015-11-09 00:46:46 +00:00
Colin LeMahieu 8a0453e23a [AsmParser] Backends can parameterize ASM tokenization.
llvm-svn: 252439
2015-11-09 00:31:07 +00:00
Eugene Zelenko ffec81ca00 Fix some Clang-tidy modernize warnings, other minor fixes.
Fixed warnings are: modernize-use-override, modernize-use-nullptr and modernize-redundant-void-arg.

Differential revision: http://reviews.llvm.org/D14312

llvm-svn: 252087
2015-11-04 22:32:32 +00:00
Benjamin Kramer e1761952b4 [TblGen] ArrayRefize CodeGenSchedule. No functionality change intended.
llvm-svn: 251187
2015-10-24 12:46:49 +00:00
Igor Laevsky 63d23d1b12 [IntrinsicEmitter] Remove GET_INTRINSIC_MODREF_BEHAVIOR table
There is no need to generate separate table for intrinsics mod ref behaviour.
It can now be determined purely from function attributes.

Differential Revision: http://reviews.llvm.org/D13917

llvm-svn: 251040
2015-10-22 18:35:34 +00:00
Craig Topper 5b0f57df1c [TableGen] Add a space between type and '*' in front of a variable name in output file. While there replace type with 'auto' since there's a cast on the right side of the assignment. NFC
llvm-svn: 249980
2015-10-11 16:59:29 +00:00
Hans Wennborg 083ca9bb32 Fix Clang-tidy modernize-use-nullptr warnings in source directories and generated files; other minor cleanups.
Patch by Eugene Zelenko!

Differential Revision: http://reviews.llvm.org/D13321

llvm-svn: 249482
2015-10-06 23:24:35 +00:00
David Majnemer f828a0ccc7 [WinEH] Make FuncletLayout more robust against catchret
Catchret transfers control from a catch funclet to an earlier funclet.
However, it is not completely clear which funclet the catchret target is
part of.  Make this clear by stapling the catchret target's funclet
membership onto the CATCHRET SDAG node.

llvm-svn: 249052
2015-10-01 18:44:59 +00:00
Matt Arsenault b12c0d9e38 TableGen: Add LLVM_READONLY to generated InstrMapping functions
These just read from a generated table.

llvm-svn: 248473
2015-09-24 07:51:20 +00:00
Craig Topper 844deef50f Remove extra 'nullptr' entry from an array in tablegen register info file. It should never have been accessed.
llvm-svn: 248246
2015-09-22 05:37:16 +00:00
Craig Topper 882a7ff91d Fix formatting of a tablegen register info file by putting a line break in a better place.
llvm-svn: 248245
2015-09-22 05:37:14 +00:00
Craig Topper 859adfaf5e Use makeArrayRef and None to simplify some code in a tablegen register info file. Additionally const correct a couple static array.
Previously the code added an extra nullptr entry to a static array and then created an ArrayRef with a size one less than the static array. If there were no other entries the array would just contain the nullptr and the ArrayRef would be crated with size 0.

Instead, put the right number of entries in the array and explicitly emit 'None' if the size would be 0. This allows the static array constructor of makeArrayRef to be used.

llvm-svn: 248244
2015-09-22 05:37:12 +00:00
Daniel Sanders 50f17235dd Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.
Eric has replied and has demanded the patch be reverted.

llvm-svn: 247702
2015-09-15 16:17:27 +00:00
Daniel Sanders 153010c52d Re-commit r247683: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.
Summary:
This is the first patch in the series to migrate Triple's (which are ambiguous)
to TargetTuple's (which aren't).

For the moment, TargetTuple simply passes all requests to the Triple object it
holds. Once it has replaced Triple, it will start to implement the interface in
a more suitable way.

This change makes some changes to the public C++ API. In particular,
InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer()
now take TargetTuples instead of Triples. The other public C++ API's have
been left as-is for the moment to reduce patch size.

This commit also contains a trivial patch to clang to account for the C++ API
change. Thanks go to Pavel Labath for fixing LLDB for me.

Reviewers: rengolin

Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D10969

llvm-svn: 247692
2015-09-15 14:08:28 +00:00
Daniel Sanders c40de48041 Revert r247684 - Replace Triple with a new TargetTuple ...
LLDB needs to be updated in the same commit.

llvm-svn: 247686
2015-09-15 13:46:21 +00:00
Daniel Sanders 18d4b0dab7 Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.
Summary:
This is the first patch in the series to migrate Triple's (which are ambiguous)
to TargetTuple's (which aren't).

For the moment, TargetTuple simply passes all requests to the Triple object it
holds. Once it has replaced Triple, it will start to implement the interface in
a more suitable way.

This change makes some changes to the public C++ API. In particular,
InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer()
now take TargetTuples instead of Triples. The other public C++ API's have
been left as-is for the moment to reduce patch size.

This commit also contains a trivial patch to clang to account for the C++ API
change.

Reviewers: rengolin

Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D10969

llvm-svn: 247683
2015-09-15 13:17:40 +00:00
Craig Topper 22fa45fc7d [TableGen] Use range-based for loops and make a helper function static. NFC
llvm-svn: 247529
2015-09-13 18:01:25 +00:00
Craig Topper b5c22252c0 [TableGen] Simplify some code by using StringRef::find instead of std::find. NFC
llvm-svn: 247528
2015-09-13 18:01:20 +00:00
Craig Topper e461214fe1 [TableGen] Use 'size_t' instead of 'unsigned' to better match the argument types of addAsmOperand. NFC
llvm-svn: 247527
2015-09-13 18:01:09 +00:00
Bruce Mitchener e9ffb45b60 Fix typos.
Summary: This fixes a variety of typos in docs, code and headers.

Subscribers: jholewinski, sanjoy, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D12626

llvm-svn: 247495
2015-09-12 01:17:08 +00:00
Hans Wennborg aa15bffa1f Re-commit r247216: "Fix Clang-tidy misc-use-override warnings, other minor fixes"
Except the changes that defined virtual destructors as =default, because that
ran into problems with GCC 4.7 and overriding methods that weren't noexcept.

llvm-svn: 247298
2015-09-10 16:49:58 +00:00
Hans Wennborg d2799a963f Revert r247216: "Fix Clang-tidy misc-use-override warnings, other minor fixes"
This caused build breakges, e.g.
http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/24926

llvm-svn: 247226
2015-09-10 00:57:26 +00:00
Hans Wennborg 6fa09455ed Fix Clang-tidy misc-use-override warnings, other minor fixes
Patch by Eugene Zelenko!

Differential Revision: http://reviews.llvm.org/D12740

llvm-svn: 247216
2015-09-10 00:12:56 +00:00
Craig Topper 1c8fbd24f3 [TableGen] Use make_unique. NFC.
llvm-svn: 246936
2015-09-06 03:44:50 +00:00
Joseph Tremoulet 917c7382c1 [TableGen] Allow TokenTy in intrinsic signatures
Summary:
Add the necessary plumbing so that llvm_token_ty can be used as an
argument/return type in intrinsic definitions and correspondingly require
TokenTy in function types.  TokenTy is an opaque type that has no target
lowering, but can be used in machine-independent intrinsics.  It is
required for the upcoming llvm.eh.padparam intrinsic.

Reviewers: majnemer, rnk

Subscribers: stoklund, llvm-commits

Differential Revision: http://reviews.llvm.org/D12532

llvm-svn: 246651
2015-09-02 13:36:25 +00:00
Ahmed Bougacha 199fa13fff [TableGen][DAGISel] Dedup predicates with same code to run. NFCI.
I locally hit the 255 limit, but a lot of these are redundant: each
predicate coming from a different record was allocated a new number,
even when we already emitted the same code for another predicate.

Instead, re-use numbers and emit the predicate code only once.
This reduces the total text size of *DAGISel.cpp.o by ~1%.

llvm-svn: 246208
2015-08-27 20:43:34 +00:00
Ahmed Bougacha 874e93f4b4 [TableGen] Remove dead code. NFC.
The only user of this was removed in r129670.

llvm-svn: 246176
2015-08-27 18:14:21 +00:00
Nick Lewycky 06b0ea2e8f Fix three typos in comments; "easilly" -> "easily".
llvm-svn: 245379
2015-08-18 22:41:58 +00:00
Craig Topper 802d3d397c [TableGen] Use range-based for loop.
llvm-svn: 245191
2015-08-16 21:27:10 +00:00
Craig Topper c4de7ee73d [TableGen] Move the ConversionRow vector into the ConversionTable instead of copying.
llvm-svn: 245190
2015-08-16 21:27:08 +00:00
Yaron Keren 556b21aa10 Remove and forbid raw_svector_ostream::flush() calls.
After r244870 flush() will only compare two null pointers and return,
doing nothing but wasting run time. The call is not required any more
as the stream and its SmallString are always in sync.

Thanks to David Blaikie for reviewing.

llvm-svn: 244928
2015-08-13 18:12:56 +00:00
Igor Laevsky 30143aee11 Emit argmemonly attribute for intrinsics.
Differential Revision: http://reviews.llvm.org/D11352

llvm-svn: 244920
2015-08-13 17:40:04 +00:00
Yaron Keren a3668a3fcd Remove raw_svector_ostream::resync and users. It's no-op after r244870.
llvm-svn: 244888
2015-08-13 12:42:25 +00:00
Cameron Esfahani f97999dc46 Explicitly clear the MI operand list when getInstruction() is called. Call MI.clear() within MCD::OPC_Decode case and inside of translateInstruction() for the X86 target. Remove now unnecessary MI.clear() from ARMDisassembler.
Summary: Explicitly clear the MI operand list when getInstruction() is called.

Reviewers: hfinkel, t.p.northover, hvarga, kparzysz, jyknight, qcolombet, uweigand

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11665

llvm-svn: 244557
2015-08-11 01:15:07 +00:00
Colin LeMahieu 3d9057470f [TableGen] NFC improving comments about what the tokenized identifiers will contain.
llvm-svn: 244493
2015-08-10 19:58:06 +00:00
David Blaikie 4ab57cd9ab Fix memory leaks by avoiding extra manual dynamic allocation
Improvement to r244212.

llvm-svn: 244252
2015-08-06 19:23:33 +00:00
Yaron Keren 6501e399ce Plug memory leaks in AsmWriterEmitter::EmitPrintAliasInstruction.
llvm-svn: 244212
2015-08-06 13:18:59 +00:00
David Blaikie 6e48a81309 -Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are deprecated in C++11
llvm-svn: 243816
2015-08-01 01:08:30 +00:00
Eric Christopher 10f5d60d37 Fix TableGen code generation for ReadNone attribute.
Patch by Pete Abred!

llvm-svn: 243689
2015-07-30 21:16:34 +00:00
Chandler Carruth 194f59ca5d [PM/AA] Extract the ModRef enums from the AliasAnalysis class in
preparation for de-coupling the AA implementations.

In order to do this, they had to become fake-scoped using the
traditional LLVM pattern of a leading initialism. These can't be actual
scoped enumerations because they're bitfields and thus inherently we use
them as integers.

I've also renamed the behavior enums that are specific to reasoning
about the mod/ref behavior of functions when called. This makes it more
clear that they have a very narrow domain of applicability.

I think there is a significantly cleaner API for all of this, but
I don't want to try to do really substantive changes for now, I just
want to refactor the things away from analysis groups so I'm preserving
the exact original design and just cleaning up the names, style, and
lifting out of the class.

Differential Revision: http://reviews.llvm.org/D10564

llvm-svn: 242963
2015-07-22 23:15:57 +00:00
JF Bastien e4d22d59d1 Targets: commonize some stack realignment code
This patch does the following:
* Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`.
* Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute.

Multiple targets duplicated the same `needsStackRealignment` code:
 - Aarch64.
 - ARM.
 - Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has.
 - PowerPC.
 - WebAssembly.
 - x86 almost: has an extra `-force-align-stack` option, which the default implementation now has.

The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects:
 - AMDGPU
 - BPF
 - CppBackend
 - MSP430
 - NVPTX
 - Sparc
 - SystemZ
 - XCore
 - Out-of-tree targets
This is a breaking change! `make check` passes.

The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation.

`needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone.

Reviewers: sunfish

Subscribers: aemerson, llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11160

llvm-svn: 242727
2015-07-20 22:51:32 +00:00
Mehdi Amini bd7287ebe5 Move most user of TargetMachine::getDataLayout to the Module one
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

This patch is quite boring overall, except for some uglyness in
ASMPrinter which has a getDataLayout function but has some clients
that use it without a Module (llmv-dsymutil, llvm-dwarfdump), so
some methods are taking a DataLayout as parameter.

Reviewers: echristo

Subscribers: yaron.keren, rafael, llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D11090

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 242386
2015-07-16 06:11:10 +00:00
Petr Pavlu 182b05784a [TableGen] Improve decoding options for non-orthogonal instructions
When FixedLenDecoder matches an input bitpattern of form [01]+ with an
instruction bitpattern of form [01?]+ (where 0/1 are static bits and ? are
mixed/variable bits) it passes the input bitpattern to a specific instruction
decoder method which then makes a final decision whether the bitpattern is a
valid instruction or not. This means the decoder must handle all possible
values of the variable bits which sometimes leads to opcode rewrites in the
decoder method when the instructions are not fully orthogonal.

The patch provides a way for the decoder method to say that when it returns
Fail it does not necessarily mean the bitpattern is invalid, but rather that
the bitpattern is definitely not an instruction that is recognized by the
decoder method. The decoder can then try to match the input bitpattern with
other possible instruction bitpatterns.

For example, this allows to solve a situation on AArch64 where the `MSR
(immediate)` instruction has form:
1101 0101 0000 0??? 0100 ???? ???1 1111
but not all values of the ? bits are allowed. The rejected values should be
handled by the `extended MSR (register)` instruction:
1101 0101 000? ???? ???? ???? ???? ????

The decoder will first try to decode an input bitpattern that matches both
bitpatterns as `MSR (immediate)` but currently this puts the decoder method of
`MSR (immediate)` into a situation when it must be able to decode all possible
values of the ? bits, i.e. it would need to rewrite the instruction to `MSR
(register)` when it is not `MSR (immediate)`.

The patch allows to specify that the decoder method cannot determine if the
instruction is valid for all variable values. The decoder method can simply
return Fail when it knows it is definitely not `MSR (immediate)`. The decoder
will then backtrack the decoding and find that it can match the input
bitpattern with the more generic `MSR (register)` bitpattern too.

Differential Revision: http://reviews.llvm.org/D7174

llvm-svn: 242274
2015-07-15 08:04:27 +00:00
Petr Pavlu 2189465af9 Fix comment typo
Test commit access.

llvm-svn: 242128
2015-07-14 08:00:34 +00:00
Elena Demikhovsky 0f370936a0 AVX-512: Added all AVX-512 forms of Vector Convert for Float/Double/Int/Long types.
In this patch I have only encoding. Intrinsics and DAG lowering will be in the next patch.
I temporary removed the old intrinsics test (just to split this patch).
Half types are not covered here.

Differential Revision: http://reviews.llvm.org/D11134

llvm-svn: 242023
2015-07-13 13:26:20 +00:00
Duncan P. N. Exon Smith 754e21f244 MC: Remove MCSubtargetInfo() default constructor
Force all creators of `MCSubtargetInfo` to immediately initialize it,
merging the default constructor and the initializer into an initializing
constructor.  Besides cleaning up the code a little, this makes it clear
that the initializer is never called again later.

Out-of-tree backends need a trivial change: instead of calling:

    auto *X = new MCSubtargetInfo();
    InitXYZMCSubtargetInfo(X, ...);
    return X;

they should call:

    return createXYZMCSubtargetInfoImpl(...);

There's no real functionality change here.

llvm-svn: 241957
2015-07-10 22:43:42 +00:00
JF Bastien b73a2ed20e Target RegisterInfo: devirtualize TargetFrameLowering
Summary:
The target frame lowering's concrete type is always known in RegisterInfo, yet it's only sometimes devirtualized through a static_cast. This change adds an auto-generated static function <Target>GenRegisterInfo::getFrameLowering(const MachineFunction &MF) which does this devirtualization, and uses this function in all targets which can.

This change was suggested by sunfish in D11070 for WebAssembly, I figure that I may as well improve the other targets while I'm here.

Subscribers: sunfish, ted, llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11093

llvm-svn: 241921
2015-07-10 18:13:17 +00:00
Reid Kleckner 60381791b5 Rename llvm.frameescape and llvm.framerecover to localescape and localrecover
Summary:
Initially, these intrinsics seemed like part of a family of "frame"
related intrinsics, but now I think that's more confusing than helpful.
Initially, the LangRef specified that this would create a new kind of
allocation that would be allocated at a fixed offset from the frame
pointer (EBP/RBP). We ended up dropping that design, and leaving the
stack frame layout alone.

These intrinsics are really about sharing local stack allocations, not
frame pointers. I intend to go further and add an `llvm.localaddress()`
intrinsic that returns whatever register (EBP, ESI, ESP, RBX) is being
used to address locals, which should not be confused with the frame
pointer.

Naming suggestions at this point are welcome, I'm happy to re-run sed.

Reviewers: majnemer, nicholas

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11011

llvm-svn: 241633
2015-07-07 22:25:32 +00:00
Ranjeet Singh 86ecbb7b54 Reverting r241058 because it's causing buildbot failures.
llvm-svn: 241061
2015-06-30 12:32:53 +00:00
Ranjeet Singh 5b119091a1 There are a few places where subtarget features are still
represented by uint64_t, this patch replaces these
usages with the FeatureBitset (std::bitset) type.

Differential Revision: http://reviews.llvm.org/D10542

llvm-svn: 241058
2015-06-30 11:30:42 +00:00
Alex Lorenz 8f6f4285f3 MIR Serialization: Serialize the register mask machine operands.
This commit implements serialization of the register mask machine
operands. This commit serializes only the call preserved register
masks that are defined by a target, it doesn't serialize arbitrary
register masks.

This commit also extends the TargetRegisterInfo class and TableGen so that
the users of TRI can get the list of all the call preserved register masks and
their names.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10673

llvm-svn: 240966
2015-06-29 16:57:06 +00:00
Elena Demikhovsky 6a1a357f1f AVX-512: Added all SKX forms of GATHER instructions.
Added intrinsics.
Added encoding and tests.

llvm-svn: 240905
2015-06-28 10:53:29 +00:00
Rafael Espindola 36b718fc74 Avoid a Symbol -> Name -> Symbol conversion.
Before this we were producing a TargetExternalSymbol from a MCSymbol.
That meant extracting the symbol name and fetching the symbol again
down the pipeline.

This patch adds a DAG.getMCSymbol that lets the MCSymbol pass unchanged on the
DAG.

Doing so removes the need for MO_NOPREFIX and fixes the root cause of pr23900,
allowing r240130 to be committed again.

llvm-svn: 240300
2015-06-22 17:46:53 +00:00
Sanjoy Das c63244daa1 [CodeGen] Introduce a FAULTING_LOAD_OP pseudo-op.
Summary:
This instruction encodes a loading operation that may fault, and a label
to branch to if the load page-faults.  The locations of potentially
faulting loads and their "handler" destinations are recorded in a
FaultMap section, meant to be consumed by LLVM's clients.

Nothing generates FAULTING_LOAD_OP instructions yet, but they will be
used in a future change.

The documentation (FaultMaps.rst) needs improvement and I will update
this diff with a more expanded version shortly.

Depends on D10196

Reviewers: rnk, reames, AndyAyers, ab, atrick, pgavlin

Reviewed By: atrick, pgavlin

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10197

llvm-svn: 239740
2015-06-15 18:44:08 +00:00
Daniel Sanders a73f1fdb19 Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and create*MCSubtargetInfo(). NFC.
Summary:
This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

Reviewers: rafael

Reviewed By: rafael

Subscribers: rafael, ted, jfb, llvm-commits, rengolin, jholewinski

Differential Revision: http://reviews.llvm.org/D10311

llvm-svn: 239467
2015-06-10 12:11:26 +00:00
Elena Demikhovsky 6b62b659cb X86-MPX: Implemented encoding for MPX instructions.
Added encoding tests.

llvm-svn: 239403
2015-06-09 13:02:10 +00:00
Craig Topper 1797bda23a [TableGen] Remove unnecessary default constructed SMLoc that just existed to return. Instead just call the default constructor in the return.
llvm-svn: 239277
2015-06-08 01:35:45 +00:00
Craig Topper e78e7c74dc [TableGen] Use range-based for loop. NFC
llvm-svn: 239276
2015-06-08 01:35:43 +00:00
Craig Topper 67bd10ea83 [TableGen] Remove unnecessary extern declaration that's already in an included header file.
llvm-svn: 239275
2015-06-08 01:35:42 +00:00
Craig Topper f7ce7242b7 [TableGen] Use the SMLoc header file instead of SourceMgr header file in a couple places. NFC
llvm-svn: 239274
2015-06-08 01:35:40 +00:00
Craig Topper 664f6a0405 [TableGen] Rename ListInit::getSize to just 'size' to be more consistent.
llvm-svn: 238806
2015-06-02 04:15:57 +00:00
Craig Topper ef0578a8cb [TableGen] Use range-based for loops. NFC.
llvm-svn: 238805
2015-06-02 04:15:51 +00:00
Benjamin Kramer f5e2fc474d Replace push_back(Constructor(foo)) with emplace_back(foo) for non-trivial types
If the type isn't trivially moveable emplace can skip a potentially
expensive move. It also saves a couple of characters.


Call sites were found with the ASTMatcher + some semi-automated cleanup.

memberCallExpr(
    argumentCountIs(1), callee(methodDecl(hasName("push_back"))),
    on(hasType(recordDecl(has(namedDecl(hasName("emplace_back")))))),
    hasArgument(0, bindTemporaryExpr(
                       hasType(recordDecl(hasNonTrivialDestructor())),
                       has(constructExpr()))),
    unless(isInTemplateInstantiation()))

No functional change intended.

llvm-svn: 238602
2015-05-29 19:43:39 +00:00
Ahmed Bougacha eb4dbd8552 [TableGen][AsmMatcherEmitter] Only parse isolated tokens as registers.
Fixes PR23455, where, when TableGen generates the matcher from the
AsmString, it splits "cmp${cc}ss" into tokens, and the "ss" suffix
is recognized as the SS register.

I can't think of a situation where that's a feature, not a bug, hence:
when a token is "isolated", i.e., it is followed and preceded by
separators, it shouldn't be parsed as a register.

Differential Revision: http://reviews.llvm.org/D9844

llvm-svn: 238536
2015-05-29 01:03:37 +00:00
Ahmed Bougacha d8dc2acda2 [TableGen][AsmMatcherEmitter] Factor out AsmOperand creation. NFC.
llvm-svn: 238534
2015-05-29 00:55:55 +00:00
Owen Anderson abaa523e9e Add support for the convergent flag at the MC and MachineInstr levels.
llvm-svn: 238450
2015-05-28 18:33:39 +00:00
Owen Anderson ca5480062a Expand the Flags field of MCInstrDesc to 64 bits, while simultaneously
shrinking the Size and NumDefs fields to offset the size growth, and
reordering the fields to preserve a good packing.

This is necessary in the short term for adding a convergent flag, and
simultaneously future-proofs us against more flags being added in the
future.

llvm-svn: 238445
2015-05-28 18:03:07 +00:00
Owen Anderson 85fa7d5037 Add initial support for the convergent attribute.
llvm-svn: 238264
2015-05-26 23:48:40 +00:00
Tom Stellard 74c87c825e AsmMatcherEmitter: Add an option to override custom converters for InstAlias
If there is an InstAlias defined for an instruction that had a custom
converter (AsmMatchConverter), then when the alias is matched,
the custom converter will be used rather than the converter generated
by the InstAlias.

This patch adds the UseInstAsmMatchConverter field to the InstAlias
class, which allows you to override this behavior and force the
converter generated by the InstAlias to be used.

This is required for some future improvemnts to the R600 assembler.

Differential Revision: http://reviews.llvm.org/D9083

llvm-svn: 238210
2015-05-26 15:55:50 +00:00
Michael Kuperstein db0712f986 Use std::bitset for SubtargetFeatures.
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures.
Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. 
This should now be fixed.

llvm-svn: 238192
2015-05-26 10:47:10 +00:00
Kit Barton 6646033e6e This patch adds support for the vector quadword add/sub instructions introduced
in POWER8:

vadduqm
vaddeuqm
vaddcuq
vaddecuq
vsubuqm
vsubeuqm
vsubcuq
vsubecuq
In addition to adding the instructions themselves, it also adds support for the
v1i128 type for intrinsics (Intrinsics.td, Function.cpp, and
IntrinsicEmitter.cpp).

http://reviews.llvm.org/D9081

llvm-svn: 238144
2015-05-25 15:49:26 +00:00
Craig Topper be91e627d9 [TableGen] Remove ListInit::size() in favor of getSize() which does the same thing and is already used in most places. NFC.
llvm-svn: 237341
2015-05-14 05:53:56 +00:00
Craig Topper ec9072d661 [TableGen] Replace some calls to ListInit::getSize() with ListInit::empty() if it was just comparing to 0. NFC.
llvm-svn: 237340
2015-05-14 05:53:53 +00:00
Jim Grosbach e9119e41ef MC: Modernize MCOperand API naming. NFC.
MCOperand::Create*() methods renamed to MCOperand::create*().

llvm-svn: 237275
2015-05-13 18:37:00 +00:00
Michael Kuperstein c3434b390d Reverting r237234, "Use std::bitset for SubtargetFeatures"
The buildbots are still not satisfied.
MIPS and ARM are failing (even though at least MIPS was expected to pass).

llvm-svn: 237245
2015-05-13 10:28:46 +00:00
Michael Kuperstein aba4a34ef2 Use std::bitset for SubtargetFeatures
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first two times this was committed (r229831, r233055), it caused several buildbot failures. 
At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed.

llvm-svn: 237234
2015-05-13 08:27:08 +00:00
James Y Knight e452e27129 Fix tablegen's PrintFatalError function to run registered file
cleanups.

Also, change code in tablegen which printed a message and then called
"exit(1)" to use PrintFatalError, instead.

This fixes instances where an empty output file was left behind after
a failed tablegen invocation, which would confuse subsequent ninja
runs into not attempting to rebuild.

Differential Revision: http://reviews.llvm.org/D9608

llvm-svn: 237058
2015-05-11 22:17:13 +00:00
Craig Topper ba6057de71 [TableGen] Don't leak Expanders and Operators in SetTheory.
llvm-svn: 235697
2015-04-24 06:49:44 +00:00
Craig Topper 1bf3d1f5dd [TableGen] Use 'isa' to identify UnsetInits rather than comparing with the singleton object created by UnsetInit::get(). Makes it more consistent with the other types.
llvm-svn: 235465
2015-04-22 02:09:45 +00:00
Elena Demikhovsky 0e6d6d54ce AVX-512: Added VPMOVx2M instructions for SKX,
fixed encoding of VPMOVM2x.

llvm-svn: 235385
2015-04-21 14:38:31 +00:00
Elena Demikhovsky 431b81e41f AVX-512: Added VPTESTM and VPTESTNM instructions for SKX
llvm-svn: 235383
2015-04-21 13:13:46 +00:00
Kit Barton f4669f5905 Add support for v1i128 type.
The v1i128 type is needed for the quadword add/substract instructions introduced
in POWER8. Futhermore, the PowerPC ABI specifies that parameters of type v1i128
are to be passed in a single vector register, while parameters of type i128 are
passed in pairs of GPRs. Thus, it is necessary to be able to differentiate
between v1i128 and i128 in LLVM.

http://reviews.llvm.org/D8564

llvm-svn: 235198
2015-04-17 16:11:05 +00:00
Richard Trieu 6b1aa5f5e1 Change range-based for-loops to be -Wrange-loop-analysis clean.
No functionality change.

llvm-svn: 234963
2015-04-15 01:21:15 +00:00
Alexander Kornienko f817c1cb9a Use 'override/final' instead of 'virtual' for overridden methods
The patch is generated using clang-tidy misc-use-override check.

This command was used:

  tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py \
    -checks='-*,misc-use-override' -header-filter='llvm|clang' \
    -j=32 -fix -format

http://reviews.llvm.org/D8925

llvm-svn: 234679
2015-04-11 02:11:45 +00:00
Craig Topper 8b88cc284f Use SmallVector instead of std::vector for uniquing X86 disassembler operand sets. The number of operands is a small fixed size.
llvm-svn: 234465
2015-04-09 04:08:48 +00:00
Craig Topper 34136874fd Simplify some printing code by combining new lines onto previous strings. Don't work so hard not to print a comma on the last entry of an array.
llvm-svn: 234464
2015-04-09 04:08:46 +00:00
Craig Topper d434e39557 Don't convert enum to strings just to put them in the uniquing map. Use the enum directly. Only convert to a string for printing.
llvm-svn: 234463
2015-04-09 04:08:42 +00:00
Craig Topper 08f4bd2847 Revert r234389. It really was needed but really should have been cstring instead of string.h
llvm-svn: 234390
2015-04-08 06:03:17 +00:00
Craig Topper 9bfac7b2e3 Remove unnecessary include. NFC
llvm-svn: 234389
2015-04-08 05:56:30 +00:00
Toma Tabacu 3d5ce49ce5 [TableGen] Prevent invalid code generation when emitting AssemblerPredicate conditions.
Summary:
The loop which emits AssemblerPredicate conditions also links them together by emitting a '&&'.
If the 1st predicate is not an AssemblerPredicate, while the 2nd one is, nothing gets emitted for the 1st one, but we still emit the '&&' because of the 2nd predicate.
This generated code looks like "( && Cond2)" and is invalid.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D8294

llvm-svn: 234312
2015-04-07 12:10:11 +00:00
Matthias Braun d85d09bfb5 TableGen: Generate more const goodness
llvm-svn: 233857
2015-04-01 22:09:55 +00:00
Matthias Braun d5fa8fb106 Fix AllocationPriority not getting set for derived register classes.
llvm-svn: 233752
2015-03-31 20:52:25 +00:00
Matthias Braun a354cdd0c5 RegAllocGreedy: Allow target to specify register class ordering.
Specify an allocation order with a register class. This is used by register
allocators with a greedy heuristic. This is usefull as it is sometimes
beneficial to color more constrained classes first.

Differential Revision: http://reviews.llvm.org/D8626

llvm-svn: 233743
2015-03-31 19:57:53 +00:00
Akira Hatanaka b46d0234a6 [MCInstPrinter] Enable MCInstPrinter to change its behavior based on the
per-function subtarget.

Currently, code-gen passes the default or generic subtarget to the constructors
of MCInstPrinter subclasses (see LLVMTargetMachine::addPassesToEmitFile), which
enables some targets (AArch64, ARM, and X86) to change their instprinter's
behavior based on the subtarget feature bits. Since the backend can now use
different subtargets for each function, instprinter has to be changed to use the
per-function subtarget rather than the default subtarget.

This patch takes the first step towards enabling instprinter to change its
behavior based on the per-function subtarget. It adds a bit "PassSubtarget" to
AsmWriter which tells table-gen to pass a reference to MCSubtargetInfo to the
various print methods table-gen auto-generates. 

I will follow up with changes to instprinters of AArch64, ARM, and X86.

llvm-svn: 233411
2015-03-27 20:36:02 +00:00
Michael Kuperstein 29704e7fb4 Revert "Use std::bitset for SubtargetFeatures"
This reverts commit r233055.

It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time.

llvm-svn: 233068
2015-03-24 12:56:59 +00:00
Michael Kuperstein 774b441b5e Use std::bitset for SubtargetFeatures
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first time this was committed (r229831), it caused several buildbot failures. 
At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed.

Differential Revision: http://reviews.llvm.org/D8542

llvm-svn: 233055
2015-03-24 09:17:25 +00:00
Benjamin Kramer b85d3756a6 Another set of missing raw_ostream.h. Still no functional change.
llvm-svn: 232993
2015-03-23 18:45:56 +00:00
Craig Topper 3a8eb896c9 [Tablegen] Attempt to add support for patterns containing nodes with multiple results.
This is needed for AVX512 masked scatter/gather support.

The R600 change is necessary to remove a hack that was working around the lack of multiple results.

llvm-svn: 232798
2015-03-20 05:09:06 +00:00
Matthias Braun a25e13aaf1 Do not track subregister liveness when it brings no benefits
Some subregisters are only to indicate different access sizes, while not
providing any way to actually divide the register up into multiple
disjunct parts. Avoid tracking subregister liveness in these cases as it
is not beneficial.

Differential Revision: http://reviews.llvm.org/D8429

llvm-svn: 232695
2015-03-19 00:21:58 +00:00
Matthias Braun 3b36533112 TableGen: Fix register class lane masks being too conservative.
When calculating the lanemask of a register class we have to include the
masks of subregisters supported by any of the class members, not just
the ones supported by all class members.

This fixes problems when coalescing towards a subclass with additional
subregisters available.

The attached testcase works fine as is, but does crash if you enable
subregister liveness on x86 without this change applied.

llvm-svn: 232652
2015-03-18 17:56:09 +00:00
Yaron Keren 92e1b62d45 Remove many superfluous SmallString::str() calls.
Now that SmallString is a first-class citizen, most SmallString::str()
calls are not required. This patch removes a whole bunch of them, yet
there are lots more.

There are two use cases where str() is really needed:
1) To use one of StringRef member functions which is not available in
SmallString.
2) To convert to std::string, as StringRef implicitly converts while 
SmallString do not. We may wish to change this, but it may introduce
ambiguity.

llvm-svn: 232622
2015-03-18 10:17:07 +00:00
Eric Christopher 44fd498a04 Use the variable names from the TargetInstrInfo source when we
reference them in the generated files. A few characters aren't huge
here and CFSetupOpcode is much more readable than S0.

llvm-svn: 232132
2015-03-13 01:26:39 +00:00
Eric Christopher 69c0a7c981 Add a return after the llvm namespace code for a little extra
readability in generated files.

llvm-svn: 232131
2015-03-13 01:10:08 +00:00
Eric Christopher 4320495319 Have getRegPressureSetLimit take a MachineFunction so that a
we can inspect the subtarget and function when computing values.

llvm-svn: 231951
2015-03-11 18:34:58 +00:00
Yaron Keren 09fb7c6e7a Teach raw_ostream to accept SmallString.
Saves adding .str() call to any raw_ostream << SmallString usage
and a small step towards making .str() consistent in the ADTs by
removing one of the SmallString::str() use cases, discussion at

http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20141013/240026.html

I'll update the Phabricator patch http://reviews.llvm.org/D6372
for review of the Twine SmallString support, it's more complex
than this one.

llvm-svn: 231763
2015-03-10 07:33:23 +00:00
Craig Topper 7bbd37b277 Improve and simplify EnforceSmallerThan for vector types.
Explicitly compare the size of the scalar types and the whole vector size rather than just comparing enum encodings.

llvm-svn: 231746
2015-03-10 03:25:07 +00:00
Craig Topper 0d1fb90e3c Remove extra indentation of entire function body. NFC.
llvm-svn: 231745
2015-03-10 03:25:04 +00:00
Reid Kleckner 294fa7aa9d TableGen: Use 'enum : uint64_t' for feature flags to fix -Wmicrosoft
clang-cl would warn that this value is not representable in 'int':
  enum { FeatureX = 1ULL << 31 };
All MS enums are 'ints' unless otherwise specified, so we have to use an
explicit type.  The AMDGPU target just hit 32 features, triggering this
warning.

Now that we have C++11 strong enum types, we can also eliminate the
'const uint64_t' codepath from tablegen and just use 'enum : uint64_t'.

llvm-svn: 231697
2015-03-09 20:23:14 +00:00
Tom Stellard 5698d63348 TableGen: Initialize ErrorInfo to ~0ULL in the MatchInstructionImpl
This is what all the targets check for and is consistent with the
initialized value of MissingFeatures, which is sometimes assinged
to ErrorInfo.

llvm-svn: 231397
2015-03-05 19:46:55 +00:00
Craig Topper 35b3dbc4a3 Revert "[TableGen] Implement at least some support for multiple explicit results in an instruction pattern. No functional change to existing patterns."
This is failing on several build bots.

llvm-svn: 231358
2015-03-05 07:17:52 +00:00
Craig Topper 5edbf1ccaf [TableGen] Implement at least some support for multiple explicit results in an instruction pattern. No functional change to existing patterns.
This should help with the AVX512 masked gather changes Elena is working on. This patch is derived from some of the changes Elena made to tablegen, but modified by me to support arbitrary number of results.

llvm-svn: 231357
2015-03-05 07:11:36 +00:00
Craig Topper 0be3458006 [TableGen] Add support constraining a vector type in a pattern to have a specific element type and for constraining a vector type to have the same number of elements as another vector type. This is useful for AVX512 mask operations so we relate the mask type to the type of the other arguments.
llvm-svn: 231356
2015-03-05 07:11:34 +00:00
David Blaikie eb6c31f900 Add a FIXME for PR22796, broken ordering of ClassInfo in TableGen
As discussed (at length) in code review of r222935, with Duncan.

llvm-svn: 231282
2015-03-04 19:56:44 +00:00
Craig Topper 483a3000f5 [Tablegen] Use correct result number variables with the pattern nodes they go with when handling SDTCisSameAs. No functional change as they are always both 0 unless you try to define a multi result type profile that uses SDTCisSame on one of the other results.
llvm-svn: 231226
2015-03-04 09:04:54 +00:00
David Blaikie 7f1e0565b3 Revert "Remove the explicit SDNodeIterator::operator= in favor of the implicit default"
Accidentally committed a few more of these cleanup changes than
intended. Still breaking these out & tidying them up.

This reverts commit r231135.

llvm-svn: 231136
2015-03-03 21:18:16 +00:00
David Blaikie bb8da4c08f Remove the explicit SDNodeIterator::operator= in favor of the implicit default
There doesn't seem to be any need to assert that iterator assignment is
between iterators over the same node - if you want to reuse an iterator
variable to iterate another node, that's perfectly acceptable. Just
don't mix comparisons between iterators into disjoint sequences, as
usual.

llvm-svn: 231135
2015-03-03 21:17:08 +00:00
Nick Lewycky b1de8c2b73 Switch up whitespace with better whitespace.
llvm-svn: 231059
2015-03-03 07:59:45 +00:00
Nick Lewycky fe9cee7b0a Revert the non-cleanup part of r230769 because it introduced a non-determinism found only in the names of symbols.
llvm-svn: 231058
2015-03-03 07:57:45 +00:00
Benjamin Kramer e1e33139c5 TblGen: Remove copy of SmallVector::operator==. NFC intended.
llvm-svn: 230964
2015-03-02 15:24:30 +00:00
Benjamin Kramer 0a446fd56c Add missing includes. make_unique proliferated everywhere.
llvm-svn: 230909
2015-03-01 21:28:53 +00:00
Elena Demikhovsky 0995479e67 Reverted 230471 - gather scatter handling in table gen.
llvm-svn: 230892
2015-03-01 08:23:41 +00:00
Elena Demikhovsky 02ffd26023 AVX-512: Added mask and rounding mode for scalar arithmetics
Added more tests for scalar instructions to destinguish between AVX and AVX-512 forms.

llvm-svn: 230891
2015-03-01 07:44:04 +00:00
Yaron Keren 96e68a0c47 Silence variable set but not used warning in CodeGenRegisters.cpp, NFC.
llvm-svn: 230854
2015-02-28 15:54:04 +00:00
Benjamin Kramer 4f6ac16292 Replace std::copy with a back inserter with vector append where feasible
All of the cases were just appending from random access iterators to a
vector. Using insert/append can grow the vector to the perfect size
directly and moves the growing out of the loop. No intended functionalty
change.

llvm-svn: 230845
2015-02-28 10:11:12 +00:00
Owen Anderson 4f527a22d2 Switch a std::map to a DenseMap in CodeGenRegisters.
The keys of the map are unique by pointer address, so there's no need
to use the llvm::less comparator. This allows us to use DenseMap
instead, which reduces tblgen time by 20% on my stress test.

llvm-svn: 230769
2015-02-27 17:57:01 +00:00
Reid Kleckner f3c8209c77 Re-instate the pragma optimize hack for MSVC, but not clang-cl
Reverts commit r230686 with define modifications.

llvm-svn: 230692
2015-02-26 21:34:11 +00:00
Reid Kleckner 94ce865c81 Remove stale pragma hack for an unsupported MSVC version
llvm-svn: 230686
2015-02-26 21:08:27 +00:00
Eric Christopher 834d6420c1 Fix a couple of depedent->dependent typos.
llvm-svn: 230584
2015-02-26 00:00:33 +00:00
Elena Demikhovsky 56eadcf5ce AVX-512: Gather and Scatter patterns
Gather and scatter instructions additionally write to one of the source operands - mask register.
In this case Gather has 2 destination values - the loaded value and the mask.
Till now we did not support code gen pattern for gather - the instruction was generated from 
intrinsic only and machine node was hardcoded.
When we introduce the masked_gather node, we need to select instruction automatically,
in the standard way.
I added a flag "hasTwoExplicitDefs" that allows to handle 2 destination operands.

(Some code in the X86InstrFragmentsSIMD.td is commented out, just to split one big
patch in many small patches)

llvm-svn: 230471
2015-02-25 09:46:31 +00:00
Tim Northover 3b6b7ca2bc CodeGen: convert CCState interface to using ArrayRefs
Everyone except R600 was manually passing the length of a static array
at each callsite, calculated in a variety of interesting ways. Far
easier to let ArrayRef handle that.

There should be no functional change, but out of tree targets may have
to tweak their calls as with these examples.

llvm-svn: 230118
2015-02-21 02:11:17 +00:00
Michael Kuperstein efd7a96d2e Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.
llvm-svn: 229841
2015-02-19 11:38:11 +00:00
Michael Kuperstein ba5b04c798 Use std::bitset for SubtargetFeatures
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.

No functional change.

Differential Revision: http://reviews.llvm.org/D7065

llvm-svn: 229831
2015-02-19 09:01:04 +00:00
Aaron Ballman 97a59fb464 MSVC 2013 does not ICE on this code in the same fashion that MSVC 2012 did; NFC.
llvm-svn: 229422
2015-02-16 19:33:36 +00:00
Aaron Ballman f9a1897c72 Removing LLVM_DELETED_FUNCTION, as MSVC 2012 was the last reason for requiring the macro. NFC; LLVM edition.
llvm-svn: 229340
2015-02-15 22:54:22 +00:00
Craig Topper a3776de242 [X86] Add the remaining 11 possible exact ModRM formats. This makes their encodings linear which can then be used to simplify some other code.
llvm-svn: 229279
2015-02-15 04:16:44 +00:00
Craig Topper 916708f152 [X86] Add support for parsing and printing the mnemonic aliases for the XOP VPCOM instructions.
llvm-svn: 229078
2015-02-13 07:42:25 +00:00
Benjamin Kramer 5f6a907288 MathExtras: Bring Count(Trailing|Leading)Ones and CountPopulation in line with countTrailingZeros
Update all callers.

llvm-svn: 228930
2015-02-12 15:35:40 +00:00