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26 Commits

Author SHA1 Message Date
Eric Christopher ae32649ff2 In preparation for moving ARM's TargetRegisterInfo to the TargetMachine 
merge Thumb1RegisterInfo and Thumb2RegisterInfo. This will enable
us to match the TargetMachine for our TargetRegisterInfo classes.

llvm-svn: 232117
 2015-03-12 22:48:50 +00:00
James Molloy 556763d2ef Fix the Load/Store optimization pass to work with Thumb1. 
Patch by Moritz Roth!

llvm-svn: 208992
 2014-05-16 14:14:30 +00:00
Gordon Keiser fb1ce5fa25 Testing commit access to llvm. Remove two lines of whitespace from the Thumb README. 
llvm-svn: 178256
 2013-03-28 18:26:15 +00:00
Nick Lewycky 7ecc2fc4ca Add another note taken from the gcc bugzilla. 
llvm-svn: 123315
 2011-01-12 09:06:19 +00:00
Jim Grosbach d7cf55cd0e Use Unified Assembly Syntax for the ARM backend. 
llvm-svn: 86494
 2009-11-09 00:11:35 +00:00
Jim Grosbach f5f263f1b4 Enable allocation of R3 in Thumb1 
llvm-svn: 84563
 2009-10-19 22:57:03 +00:00
Evan Cheng b2c22f00de Another TODO. 
llvm-svn: 77026
 2009-07-25 00:39:37 +00:00
Evan Cheng fa60698c29 Fix PR4567. Thumb1 target was using the wrong instruction to handle sp = sub fp, #c. 
llvm-svn: 76401
 2009-07-20 06:59:32 +00:00
Evan Cheng 0794c6a083 Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible. 
llvm-svn: 75360
 2009-07-11 07:08:13 +00:00
Evan Cheng cd4cdd1157 Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. 
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.

llvm-svn: 75359
 2009-07-11 06:43:01 +00:00
Evan Cheng 01b8630879 More info about Thumb1 predication support. 
llvm-svn: 75220
 2009-07-10 02:10:17 +00:00
Evan Cheng ae4f2e142a Another todo entry. 
llvm-svn: 75192
 2009-07-09 23:17:28 +00:00
Evan Cheng f9870125fc Add a Thumb readme entry. 
llvm-svn: 75173
 2009-07-09 20:50:52 +00:00
Jim Grosbach 643e60e19c Whitespace cleanup. Test commit. 
llvm-svn: 54695
 2008-08-12 18:34:45 +00:00
Evan Cheng 1f2dd35898 Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4. 
llvm-svn: 43234
 2007-10-22 22:11:27 +00:00
Chris Lattner 446548d2a3 update this entry, now that Anton implemented shift/and lowering for 
switches.  There is one really easy isel thing here with tst we are not
getting.

llvm-svn: 37400
 2007-06-02 18:45:14 +00:00
Evan Cheng 045414aa8e New entry. 
llvm-svn: 35480
 2007-03-29 21:40:13 +00:00
Evan Cheng 39eb62ea3b New entry. 
llvm-svn: 35206
 2007-03-20 08:10:17 +00:00
Evan Cheng b216ea1aa6 New entry. 
llvm-svn: 34000
 2007-02-07 09:22:15 +00:00
Evan Cheng 2ff0d3a2ab Update 
llvm-svn: 33998
 2007-02-07 08:37:57 +00:00
Evan Cheng ec13f826a2 Spill / restore should avoid modifying the condition register. 
llvm-svn: 33971
 2007-02-07 00:06:56 +00:00
Evan Cheng 0df1536173 Add a note. 
llvm-svn: 33743
 2007-02-01 02:46:20 +00:00
Evan Cheng 29f920877d Possible JT improvements. 
llvm-svn: 33733
 2007-02-01 01:07:48 +00:00
Evan Cheng 2e309b15a7 Add entry. 
llvm-svn: 33723
 2007-01-31 22:11:38 +00:00
Evan Cheng 0cd49bc8a2 New entry. 
llvm-svn: 33569
 2007-01-27 02:33:22 +00:00
Evan Cheng 10043e215b ARM backend contribution from Apple. 
llvm-svn: 33353
 2007-01-19 07:51:42 +00:00