Commit Graph

2148 Commits

Author SHA1 Message Date
Rafael Espindola e8d060dba9 Don't hardcode the order of the aliases.
llvm-svn: 192601
2013-10-14 16:05:12 +00:00
Chad Rosier 193573ec89 [AArch64] Add support for NEON scalar integer compare instructions.
llvm-svn: 192597
2013-10-14 14:37:40 +00:00
Manman Ren f5d9d348f7 Turn struct-path aware TBAA on by default.
Use -no-struct-path-tbaa to turn it off.
This is the same as r191695, which was reverted because it depends on a
commit that has issues.

llvm-svn: 192497
2013-10-11 20:48:38 +00:00
Warren Hunt 8f8bad723d Adds Microsoft compatiable C++ record layout code to clang.
llvm-svn: 192494
2013-10-11 20:19:00 +00:00
Robert Lytton 2d1969584a XCore : Fix bug in XCoreABIInfo::EmitVAArg()
Incorrect handling of 'double' and 'long long int'

llvm-svn: 192436
2013-10-11 10:29:34 +00:00
Nick Lewycky ce6a4aacb4 The emitted IR is the same, we need these flags to actually use the LLVM target.
Mark it as requiring the x86 target.

llvm-svn: 192417
2013-10-11 03:52:43 +00:00
Nick Lewycky 3a410fe085 Add -fno-function-sections and -fno-data-sections. Since
-f{function,data}-sections had no tests at all, add some, and verify that the
-fno variants work as well.

llvm-svn: 192413
2013-10-11 03:35:10 +00:00
Kevin Qin f22bf50443 Implemented aarch64 SIMD copy related ACLE intrinsic :
vget_lane, vset_lane, vcopy_lane, vcreate, vdup_n, vdup_lane, vmov_n.

llvm-svn: 192411
2013-10-11 02:34:30 +00:00
Hao Liu 1eade6d927 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 192362
2013-10-10 17:01:49 +00:00
Tim Northover 72ace5cf12 Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). "
This reverts commit r192351. The LLVM side broke the build and the Clang tests
will inevitably fail without it.

llvm-svn: 192356
2013-10-10 16:00:08 +00:00
Hao Liu c319193636 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

E.g. ld1(3 registers version) will load 32-bit elements {A, B, C, D, E, F} sequentially into the three 64-bit vectors list {BA, DC, FE}.
E.g. ld3 will load 32-bit elements {A, B, C, D, E, F} into the three 64-bit vectors list {DA, EB, FC}.

llvm-svn: 192351
2013-10-10 14:59:36 +00:00
Hans Wennborg 1e109804f5 Tighten diagnostics for calling conventions on variadic functions
Follow-up from r192240.

This makes it an error to use callee-cleanup conventions on variadic
functions, except for __fastcall and __stdcall, which we ignore with
a warning for GCC and MSVC compatibility.

Differential Revision: http://llvm-reviews.chandlerc.com/D1870

llvm-svn: 192308
2013-10-09 18:10:25 +00:00
Chad Rosier 0a903478c6 [AArch64] Add support for NEON scalar floating-point reciprocal estimate,
reciprocal exponent, and reciprocal square root estimate instructions.

llvm-svn: 192243
2013-10-08 22:09:29 +00:00
Hans Wennborg 9112ac2136 Turn error about fastcall variadic function into warning in MS mode (PR12535)
MSVC allows this and silently falls back to __cdecl for variadic functions.
This patch turns Clang's error into a warning in MS mode and adds a test
to make sure we generate correct code.

Differential Revision: http://llvm-reviews.chandlerc.com/D1861

llvm-svn: 192240
2013-10-08 21:52:56 +00:00
Chad Rosier 0babda4b9c [AArch64] Add support for NEON scalar signed/unsigned integer to floating-point
convert instructions.

llvm-svn: 192232
2013-10-08 20:43:46 +00:00
Akira Hatanaka 71cd285dc8 [mips] Remove XFAIL.
Triple x86_64 has been added to the command line, so this test doesn't fail
on mips anymore.

llvm-svn: 192219
2013-10-08 19:08:54 +00:00
Manman Ren 4f755deaf6 TBAA: use the same format for scalar TBAA and struct-path aware TBAA.
An updated version of r191586 with bug fix.

Struct-path aware TBAA generates tags to specify the access path,
while scalar TBAA only generates tags to scalar types.

We should not generate a TBAA tag with null being the first field. When
a TBAA type node is null, the tag should be null too. Make sure we
don't decorate an instruction with a null TBAA tag.

Added a testing case for the bug reported by Richard with -relaxed-aliasing
and -fsanitizer=thread.

llvm-svn: 192145
2013-10-08 00:08:49 +00:00
Matt Arsenault 2f15263807 Fix objectsize tests after r192117
llvm-svn: 192120
2013-10-07 19:00:18 +00:00
Chad Rosier 027dfade54 [AArch64] Add support for NEON scalar arithmetic instructions:
SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS.

llvm-svn: 192112
2013-10-07 17:07:17 +00:00
Craig Topper d335c9da22 Use logical/arithmetic operations instead of builtins in tbmintrin.h. This way we can remove the intrinsic support from the backend.
llvm-svn: 192036
2013-10-05 17:08:42 +00:00
Jiangning Liu b96ebac02b Implement aarch64 neon instruction set AdvSIMD (Across).
llvm-svn: 192029
2013-10-05 08:22:55 +00:00
Rafael Espindola aa2976f388 Don't assume instruction names in the output.
llvm-svn: 191957
2013-10-04 14:42:00 +00:00
Amaury de la Vieuville 21bf6ed730 Do not emit undefined lsrh/ashr for NEON shifts
These IR instructions are undefined when the amount is equal to operand
size, but NEON right shifts support such shifts. Work around that by
emitting a different IR in these cases.

llvm-svn: 191953
2013-10-04 13:13:15 +00:00
Jiangning Liu 4617e9dc85 Implement aarch64 neon instruction set AdvSIMD (3V elem).
llvm-svn: 191945
2013-10-04 09:21:17 +00:00
Matthew Curtis 274a9cc84b Gracefully (and correctly) handle init of multiple union members
We now emit warnings when doing so and code generation is consistent
with GCC. Note that the C99 spec is unclear as to the precise
behavior.

See also ...
Bug:
  http://llvm.org/bugs/show_bug.cgi?id=16644 and

cfe-dev discussion:
  http://lists.cs.uiuc.edu/pipermail/cfe-dev/2013-September/031918.html

llvm-svn: 191890
2013-10-03 12:14:24 +00:00
Craig Topper d867805739 Change __builtin_ia32_bextri_u64 to take an i64imm to match up with LLVM backend changes.
An explicit cast is still needed in tbmintrin.h to convert any big integer down to i32imm.

Patch from Yunzhong Gao.

llvm-svn: 191872
2013-10-03 04:21:19 +00:00
Joey Gouly 75987a65f3 [ARM] Add a builtin to allow you to use the 'sevl' instruction.
llvm-svn: 191816
2013-10-02 10:00:18 +00:00
Tim Northover a484bc00ff Implement ARM GNU-style interrupt attribute
This attribute allows users to use a modified C or C++ function as an ARM
exception-handling function and, with care, to successfully return control to
user-space after the issue has been dealt with.

rdar://problem/14207019

llvm-svn: 191769
2013-10-01 14:34:25 +00:00
Richard Smith e4aaac506c Revert r191586 and r191695. They cause crashes when building with
-relaxed-aliasing.

llvm-svn: 191725
2013-10-01 02:20:23 +00:00
Manman Ren e5c2d919b6 Turn struct-path aware TBAA on by default.
Use -no-struct-path-tbaa to turn it off.

llvm-svn: 191695
2013-09-30 19:35:19 +00:00
Yunzhong Gao f4e0b1047a Adding intrinsics to the clang front end for the x86 TBM instruction set.
Differential Revision: http://llvm-reviews.chandlerc.com/D1751

llvm-svn: 191681
2013-09-30 17:25:14 +00:00
Benjamin Kramer 5352717508 The second parameter of nexttoward is always long double.
llvm-svn: 191623
2013-09-28 17:41:03 +00:00
Manman Ren 4f04263347 TBAA: use the same format for scalar TBAA and struct-path aware TBAA.
Struct-path aware TBAA generates tags to specify the access path,
while scalar TBAA only generates tags to scalar types.

llvm-svn: 191586
2013-09-27 23:06:41 +00:00
Jiangning Liu 036f16dc8c Initial support for Neon scalar instructions.
Patch by Ana Pazos.

1.Added support for v1ix and v1fx types.
2.Added Scalar Pairwise Reduce instructions.
3.Added initial implementation of Scalar Arithmetic instructions.

llvm-svn: 191264
2013-09-24 02:48:06 +00:00
Eli Friedman 3cd55f49ab Fix argument types of some AVX2 intrinsics.
This fix makes our headers consistent with gcc.

PR17312.

llvm-svn: 191248
2013-09-23 23:52:04 +00:00
Eli Friedman f9d8c6cebb Add _mm_stream_si64 intrinsic.
While I'm here, also fix the alignment computation for the whole family of
intrinsics.

PR17298.

llvm-svn: 191243
2013-09-23 23:38:39 +00:00
Eli Friedman 9b04f41899 Fix return type of _mm_extract_epi8 etc.
PR17300.

llvm-svn: 191120
2013-09-21 00:05:25 +00:00
Ben Langmuir ed6e97d2c3 Fix ifdef macro missed in previous commit
llvm-svn: 191003
2013-09-19 14:07:14 +00:00
Ben Langmuir 58078d0103 Add C intrinsics for Intel SHA Extensions
Intrinsics added shaintrin.h, which is included from x86intrin.h if __SHA__ is
enabled. SHA implies SSE2, which is needed for the __m128i type.

Also add the -msha/-mno-sha option.

llvm-svn: 190999
2013-09-19 13:22:04 +00:00
Adrian Prantl 0315f38a92 Debug info: Explicitly set the DIVariable::isIndirect() flag for VLAs.
This allows us to get rid of an ugly hack in the backend.
Paired commit with LLVM.

llvm-svn: 190960
2013-09-18 22:08:57 +00:00
Joey Gouly 1e8637b259 [ARMv8] Add builtins for CRC instructions.
Patch by Bradley Smith!

llvm-svn: 190931
2013-09-18 10:07:09 +00:00
Amaury de la Vieuville 718ce62b3c Add support for poly16 vtst and vtstq
vtst and vtstq currently support poly8 types, but they should also work on
poly16.

llvm-svn: 190925
2013-09-18 08:33:53 +00:00
Hal Finkel 33be5e0e5c Add new libm LIBBUILTIN definitions, synchronizing with __builtin_*
For all libm __builtin_* functions that are defined, this adds the
corresponding LIBBUILTIN definitions (tagged, as necessary, with "e" instead of
"c" when the function may set errno).

Note that this changes the current definitions for lrint and fma
(unfortunately). The Linux man page documents that these don't set errno, but
the POSIX standard says that they should.

llvm-svn: 190922
2013-09-18 06:19:40 +00:00
Hal Finkel c4d7c82c7f Add the intrinsic __builtin_convertvector
LLVM supports applying conversion instructions to vectors of the same number of
elements (fptrunc, fptosi, etc.) but there had been no way for a Clang user to
cause such instructions to be generated when using builtin vector types.

C-style casting on vectors is already defined in terms of bitcasts, and so
cannot be used for these conversions as well (without leading to a very
confusing set of semantics). As a result, this adds a __builtin_convertvector
intrinsic (patterned after the OpenCL __builtin_astype intrinsic). This is
intended to aid the creation of vector intrinsic headers that create generic IR
instead of target-dependent intrinsics (in other words, this is a generic
_mm_cvtepi32_ps). As noted in the documentation, the action of
__builtin_convertvector is defined in terms of the action of a C-style cast on
each vector element.

llvm-svn: 190915
2013-09-18 03:29:45 +00:00
Reid Kleckner 543a16c06b Emit an error when attempting to generate IR for SEH __try
Currently we silently omit the code in the try and finally bodies, which
is pretty bad.  This way we fail loudly.

llvm-svn: 190809
2013-09-16 21:46:30 +00:00
Amara Emerson 8c3de546d6 Add error checking to reject neon_vector_type attribute on targets without NEON.
Patch by Artyom Skrobov.

llvm-svn: 190801
2013-09-16 18:07:35 +00:00
Hal Finkel 28b2ae3692 Restore the sqrt -> llvm.sqrt mapping in fast-math mode
This restores the sqrt -> llvm.sqrt mapping, but only in fast-math mode
(specifically, when the UnsafeFPMath or NoNaNsFPMath CodeGen options are
enabled). The @llvm.sqrt* intrinsics have slightly different semantics from the
libm call, specifically, they are undefined when given a non-zero negative
number (the libm calls will always return NaN for any negative number).

This mapping was removed in r100613, and replaced with a TODO, but at that time
the fast-math flags were not yet implemented. Now that we have these, restoring
this mapping is important because it will enable autovectorization of sqrt
calls in loops (at least in fast-math mode).

llvm-svn: 190646
2013-09-12 23:57:55 +00:00
Daniel Sanders cb2929c239 [mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsics
The elements of the operands should be half the width of the elements of
the result.

llvm-svn: 190505
2013-09-11 09:59:17 +00:00
Daniel Sanders 3615c45d76 [mips][msa] Removed unsupported dot product instructions (dotp_[su].b).
The dotp_[su].b instructions never existed in any revision of the MSA spec.

llvm-svn: 190399
2013-09-10 10:10:39 +00:00
Jiangning Liu 1bda93a252 Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions,
SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL

llvm-svn: 190289
2013-09-09 02:21:08 +00:00