58a7c9fd3e
Fix test.
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llvm-svn: 153095
2012-03-20 17:20:46 +00:00
07a4cb9382
[avx] Adjust the VINSERTF128rm pattern to allow for unaligned loads.
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This results in things such as
vmovups 16(%rdi), %xmm0
vinsertf128 $1, %xmm0, %ymm0, %ymm0
to be combined to
vinsertf128 $1, 16(%rdi), %ymm0, %ymm0
rdar://11076953
llvm-svn: 153092
2012-03-20 17:08:51 +00:00
b9b73170e3
[avx] Add patterns for VINSERTF128rm.
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This results in things such as
vmovaps -96(%rbx), %xmm1
vinsertf128 $1, %xmm1, %ymm0, %ymm0
to be combined to
vinsertf128 $1, -96(%rbx), %ymm0, %ymm0
rdar://10643481
llvm-svn: 152762
2012-03-15 00:45:30 +00:00
682c76b7d4
Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove duplicate patterns for selecting the intrinsics
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llvm-svn: 151342
2012-02-24 03:51:49 +00:00
6cb23f6e7f
Add a DAGCombine for subvector extracts to remove useless chains of
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subvector inserts and extracts. Initial patch by Rackover, Zvi with
some tweak done by me.
llvm-svn: 140204
2011-09-20 23:19:33 +00:00
8058234b32
Revert r140097, working on a better approach
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llvm-svn: 140203
2011-09-20 23:19:29 +00:00
51792dcc4d
Based on the small opt Zvi's patch was trying to achieve, eliminate
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128-bit undef subvector insertion into a 256-bit vector
llvm-svn: 140097
2011-09-19 23:36:50 +00:00
cbe7feeab9
Fix PR10656. It's only profitable to use 128-bit inserts and extracts
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when AVX mode is one. Otherwise is just more work for the type
legalizer.
llvm-svn: 137661
2011-08-15 21:45:54 +00:00
8fbf023c9b
Add a dag combine to xform 256-bit shuffles into simple vector
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inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.
llvm-svn: 137362
2011-08-11 21:50:44 +00:00
Chad Rosier