uint32_t insn;
MemoryObject.readBytes(Address, 4, (uint8_t*)&insn, NULL)
to read 4 bytes of memory contents into a 32-bit uint variable. This leaves the
interpretation of byte order up to the host machine and causes PPC test cases of
arm-tests, neon-tests, and thumb-tests to fail. Fixed to use a byte array for
reading the memory contents and shift the bytes into place for the 32-bit uint
variable in the ARM case and 16-bit halfword in the Thumb case.
llvm-svn: 100403
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
llvm-svn: 100384
"asm printering" happens through MCStreamer. This also
Streamerizes PIC16 debug info, which escaped my attention.
This removes a leak from LLVMTargetMachine of the 'legacy'
output stream.
llvm-svn: 100327
raw_ostream to print an instruction to had to be specified
at MCInstPrinter construction time instead of being able
to pick at each call to printInstruction.
llvm-svn: 100307
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
llvm-svn: 100304
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.
Reviewed by Chris Latter and Bob Wilson.
llvm-svn: 100233
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
llvm-svn: 100191
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.
llvm-svn: 99928
create symbols. It is extremely error prone and a source of a lot
of the remaining integrated assembler bugs on x86-64.
This fixes rdar://7807601.
llvm-svn: 99902
These instructions use byte index in a control vector (M:Vm) to lookup byte
values in a table and generate a new vector (D:Vd). The table is specified via
a list of vectors, which can be:
{Dn}
{Dn D<n+1>}
{Dn D<n+1> D<n+2>}
{Dn D<n+1> D<n+2> D<n+3>}
llvm-svn: 99789
input to be v8i8 or v16i8, which buildvectors get canonicalized to.
This allows the patterns that were previously using a bare 'vnot' to
match, before they couldn't.
llvm-svn: 99754
it as the format for the appropriate N3V*SL*<> classes. These instructions
require special handling of the M:Vm field which encodes the restricted Dm and
the lane index within Dm.
Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar):
vmlal.s32 q3, d2, d10[0]
llvm-svn: 99690
through to the generic version. The generic functions use STR/LDR, but T2
needs the t2STR/t2LDR instead so we get the addressing mode correct.
llvm-svn: 99678
to encode the byte location of the extracted result in the concatenation of the
operands, from the least significant end.
Modify VEXTd and VEXTq classes to use the format.
llvm-svn: 99659
follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm. The operand order of
N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).
Add a parent class N3Vf which requires passing a Format argument and which the
N3V class is modified to inherit from. N3V class represents the "normal"
3-Register NEON Instructions with N3RegFrm.
Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
Instructions and replace 8 invocations with it.
llvm-svn: 99655
Examples are VABA (Vector Absolute Difference and Accumulate), VABAL (Vector
Absolute Difference and Accumulate Long), and VABD (Vector Absolute Difference).
llvm-svn: 99628
dispatch to the appropriate routines to handle the different interpretations of
the shift amount encoded in the imm6 field. The Vd, Vm fields are interpreted
the same between the two, though.
See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and
A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format.
llvm-svn: 99590
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.
llvm-svn: 99309
with changes to add a separate optional register update argument. Change all
the NEON instructions with address register writeback to use it.
llvm-svn: 99095
writeback, and refactor the existing double-spaced VST2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.
llvm-svn: 99090
load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.
llvm-svn: 99066
writeback, and refactor the existing double-spaced VLD2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.
llvm-svn: 99065
load/store optimizer would incorrectly think that registers D26 and D28
were consecutive and would generate a VLDM instruction to load them.
The assembler was not convinced.
llvm-svn: 99043
--- Reverse-merging r98889 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMISelLowering.h
U lib/Target/ARM/ARMInstrInfo.td
U lib/Target/ARM/ARMInstrVFP.td
U lib/Target/ARM/ARMISelLowering.cpp
U lib/Target/ARM/ARMInstrFormats.td
llvm-svn: 99010
matches that of Firstcond[0] and E means otherwise. The Firstcond[0] is also
tagged in the Mask to facilitate Asm printing. The disassembler also depends
on this arrangement. This is similar to what's described in A2.5.2 ITSTATE.
Ran:
utils/lit/lit.py test/CodeGen/ARM test/CodeGen/Thumb test/CodeGen/Thumb2
successfully.
llvm-svn: 98775
addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>.
This patch removes the impl of printT2AddrModeImm8s4OffsetOperand() from
ARMAsmPrinter.cpp. It is used by disassembler as of now.
llvm-svn: 98774
instructions to help disassembly.
We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60.
And modified test cases to not expect '+' in +reg or #+num. For example,
; CHECK: ldr.w r9, [r7, #28]
llvm-svn: 98745
This is for the disassembly work.
There are cases where this is not possible, for example, A8.6.53 LDM Encoding T1.
In such case, we'll use an adhoc approach to deduce the Opcode programmatically.
llvm-svn: 98679
U test/CodeGen/ARM/tls2.ll
U test/CodeGen/ARM/arm-negative-stride.ll
U test/CodeGen/ARM/2009-10-30.ll
U test/CodeGen/ARM/globals.ll
U test/CodeGen/ARM/str_pre-2.ll
U test/CodeGen/ARM/ldrd.ll
U test/CodeGen/ARM/2009-10-27-double-align.ll
U test/CodeGen/Thumb2/thumb2-strb.ll
U test/CodeGen/Thumb2/ldr-str-imm12.ll
U test/CodeGen/Thumb2/thumb2-strh.ll
U test/CodeGen/Thumb2/thumb2-ldr.ll
U test/CodeGen/Thumb2/thumb2-str_pre.ll
U test/CodeGen/Thumb2/thumb2-str.ll
U test/CodeGen/Thumb2/thumb2-ldrh.ll
U utils/TableGen/TableGen.cpp
U utils/TableGen/DisassemblerEmitter.cpp
D utils/TableGen/RISCDisassemblerEmitter.h
D utils/TableGen/RISCDisassemblerEmitter.cpp
U Makefile.rules
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/Makefile
U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
D lib/Target/ARM/Disassembler
U lib/Target/ARM/ARMInstrFormats.td
U lib/Target/ARM/ARMAddressingModes.h
U lib/Target/ARM/Thumb2ITBlockPass.cpp
llvm-svn: 98640
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.
We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60.
And modified test cases to not expect '+' in +reg or #+num. For example,
; CHECK: ldr.w r9, [r7, #28]
llvm-svn: 98637
an MCSymbol. Make the EH_LABEL MachineInstr hold its label
with an MCSymbol instead of ID. Fix a bug in MMI.cpp which
would return labels named "Label4" instead of "label4".
llvm-svn: 98463
instead of label ID's. This cleans up and regularizes a bunch
of code and makes way for future progress.
Unfortunately, this pointed out to me that JITDwarfEmitter.cpp
is largely copy and paste from DwarfException/MachineModuleInfo
and other places. This is very sad and disturbing. :(
One major change here is that TidyLandingPads moved from being
called in DwarfException::BeginFunction to being called in
DwarfException::EndFunction. There should not be any
functionality change from doing this, but I'm not an EH expert.
llvm-svn: 98459
and passing off ownership to AsmPrinter. Now MachineModuleInfo
creates it and owns it by value. This allows us to use MCSymbols
more consistently throughout the rest of the code generator, and
simplifies a bit of code. This also allows MachineFunction to
keep an MCContext reference handy, and cleans up the TargetRegistry
interfaces for AsmPrinters.
llvm-svn: 98450
writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback register operand. There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand. The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other. This also fixes Radar 7495976 and should help the verifier work
better for ARM code.
There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.
llvm-svn: 98409
for the NLP because the object it's pointing to may be internal to the file.
This seems counter-intuitive, but bear with me. When we place the LSDA into the
TEXT section, the type info pointers need to be indirect and pc-rel. We
accomplish this by using NLPs. However, sometimes the types are local to the
file. GCC gets around this by not using a NLP in this case, but a "regular"
indirection like this:
GCC_except_tbl:
.long Lfoo-.
__ZTIA: @ This is local
...
Lfoo:
.long __ZTIA
LLVM prefers NLPs on Darwin. In fact, it's more optimal for load performance to
use them.
llvm-svn: 98218
indicates that an MCSymbol is external or not. (It's true if it's external.)
This will be used to specify the correct information to add to non-lazy
pointers. That will be explained further when this bit is used.
llvm-svn: 98199
is preparatory to having PEI's scavenged frame index value reuse logic
properly distinguish types of frame values (e.g., whether the value is
stack-pointer relative or frame-pointer relative).
No functionality change.
llvm-svn: 98086
register is involved for thumb1. Work around this for the moment by only
re-using SP-relative offsets. This is temporary 'til the code can distinguish
multiple base registers.
llvm-svn: 98071
Place the LSDA into the TEXT section for ARM platforms. This involves making the
encoding indirect, pcrel, and sdata4 instead of an absolute pointer. The
references to the type infos are then non-lazy pointers. Revision 98019 changed
the encoding of non-lazy pointers to add the symbol to the non-lazy pointer
definition if it's a local symbol (otherwise, it's external and set to '0' so
that the loader can adjust it to the real value). This paved the way for this
change to work on ARM.
llvm-svn: 98068
immediate instructions cannot set the condition codes, so they do not have
the extra cc_out operand. We hit an assertion during tail duplication
because the instruction being duplicated had more operands that expected.
llvm-svn: 98001
example, this:
(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))
is ambiguous because DPR contains both f64 and v2f32. tblgen
currently accidentally picks f64 because it's first in the
regclass.
llvm-svn: 97955
an undef value. This is only going to come up for bugpoint-reduced tests --
correct programs will not access memory at undefined addresses -- so it's not
worth the effort of doing anything more aggressive.
llvm-svn: 97745
Instruction (PLI) for disassembly only.
According to A8.6.120 PLI (immediate, literal), for example, different
instructions are generated for "pli [pc, #0]" and "pli [pc, #-0"]. The
disassembler solves it by mapping -0 (negative zero) to -1, -1 to -2, ..., etc.
llvm-svn: 97731
- Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools).
llvm-svn: 97628
Anton Korobeynikov