2c452fcd14
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
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llvm-svn: 104102
2010-05-19 01:52:25 +00:00
c601801a7e
Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests.
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Obvious in retrospect but not fun to debug.
llvm-svn: 103969
2010-05-17 20:31:13 +00:00
497d831966
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
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llvm-svn: 103903
2010-05-16 09:15:36 +00:00
2b7aace2e0
"trap" pseudo-op turned out to be apple-local.
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Temporary emit it as raw bytes until it will be added to binutils as well.
llvm-svn: 103878
2010-05-15 17:19:20 +00:00
2fa5a7e7e4
Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
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llvm-svn: 103459
2010-05-11 07:26:32 +00:00
0433699ef0
set SDNPVariadic on nodes throughout the rest of the targets that
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need them.
llvm-svn: 98937
2010-03-19 05:33:51 +00:00
d6243b49d4
Remove the writeback flag from ARM's address mode 4. Now that we have separate
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instructions for ld/st with writeback, the flag is completely redundant.
llvm-svn: 98643
2010-03-16 17:46:45 +00:00
947f04bad0
Change ARM ld/st multiple instructions to have variant instructions for
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writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback register operand. There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand. The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other. This also fixes Radar 7495976 and should help the verifier work
better for ARM code.
There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.
llvm-svn: 98409
2010-03-13 01:08:20 +00:00
9a3e2398ae
Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero
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operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.
llvm-svn: 98172
2010-03-10 18:59:38 +00:00
1d63b9574d
Modified the asm string of 16-bit Thumb MUL instruction so that it prints:
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MULS <Rdm>, <Rn>, <Rdm>
according to A8.6.105 MUL Encoding T1.
llvm-svn: 97675
2010-03-03 23:15:43 +00:00
44908a5e17
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
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SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
llvm-svn: 97573
2010-03-02 18:14:57 +00:00
8c5d683aa9
The mayHaveSideEffects flag is no longer used.
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llvm-svn: 97348
2010-02-27 23:47:46 +00:00
74cca5a989
Added the following 16-bit Thumb instructions for disassembly only: YIELD, WFE,
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WFI, SEV, SETEND.
llvm-svn: 97149
2010-02-25 17:51:03 +00:00
90adefcf7e
Added tNOP for disassembly only.
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llvm-svn: 97105
2010-02-25 03:28:51 +00:00
57656da73f
Added tSVC and tTRAP for disassembly only.
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llvm-svn: 97098
2010-02-25 02:21:11 +00:00
45fceea0e4
Updated version of r96634 (which was reverted due to failing 176.gcc and
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126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.
llvm-svn: 96822
2010-02-22 23:10:38 +00:00
3e2cad3b1a
80 column cleanup
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llvm-svn: 96393
2010-02-16 21:23:02 +00:00
fba7fce5be
Remove trailing whitespace
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llvm-svn: 96388
2010-02-16 21:07:46 +00:00
f40b8e03fb
Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose.
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llvm-svn: 95884
2010-02-11 18:12:29 +00:00
f7279bd10f
Radar 7417921
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tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.
llvm-svn: 95686
2010-02-09 19:51:37 +00:00
a570d05228
tighten up eh.setjmp sequence a bit.
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llvm-svn: 95603
2010-02-08 23:22:00 +00:00
a3575ca846
Adjust setjmp instruction sequence to not need 32-bit alignment padding
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llvm-svn: 94627
2010-01-27 00:07:20 +00:00
267430f74d
Fix PR5694. The CMN instructions set the flags differently from CMP, so they
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cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.
llvm-svn: 94119
2010-01-22 00:08:13 +00:00
27f000a9af
The most significant encoding bit of GPR:$src or GPR:$dst was over-specified in
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the various MOV (register) instructions (16-bit Thumb), including tBRIND (the
indirect branch). Instead of '1', it should be specified as '?', because GPR
only specifies the register class, which includes both hi-and-lo registers.
llvm-svn: 93759
2010-01-18 20:15:56 +00:00
0f45f4f849
Added 16-bit Thumb Load/Store immediate instructions with encoding bits so that
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the disassembler can properly decode Load/Store register/immediate instructions.
llvm-svn: 93471
2010-01-14 22:42:17 +00:00
b34888b6d0
Fixed a couple of places for Thumb MOV where encoding bits are underspecified.
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llvm-svn: 93349
2010-01-13 21:00:26 +00:00
a94837dc24
Remove the JustSP single-register regclass.
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It was only being used by instructions with the t_addrmode_sp addressing mode,
and that is pattern matched in a way that guarantees SP is used. There is
never any register allocation done from this class.
llvm-svn: 93280
2010-01-13 00:43:06 +00:00
b05fbe1486
Add a SPR register class to the ARM target.
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Certain Thumb instructions require only SP (e.g. tSTRspi).
llvm-svn: 91944
2009-12-22 23:54:44 +00:00
7f30b64dce
Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings.
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llvm-svn: 91571
2009-12-16 23:36:52 +00:00
466231ab92
Add encoding bits for some Thumb instructions. Plus explicitly set the top two
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bytes of Inst to 0x0000 for the benefit of the Thumb decoder.
llvm-svn: 91496
2009-12-16 02:32:54 +00:00
c28e629c2d
Added encoding bits for the Thumb ISA. Initial checkin.
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llvm-svn: 91434
2009-12-15 17:24:14 +00:00
36d4dec28a
Thumb1 exception handling setjmp
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llvm-svn: 90246
2009-12-01 18:10:36 +00:00
bdb43a9d99
Remat VLDRD from constpool. Clean up some instruction property specifications.
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llvm-svn: 89478
2009-11-20 19:57:15 +00:00
b18525937c
More consistent thumb1 asm printing.
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llvm-svn: 89328
2009-11-19 06:57:41 +00:00
207b246650
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
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load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
llvm-svn: 86304
2009-11-06 23:52:48 +00:00
c63943018f
The .n suffix must go after the predicate.
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llvm-svn: 86019
2009-11-04 07:38:48 +00:00
3f1a92468a
Use ldr.n to workaround a darwin assembler bug.
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llvm-svn: 85980
2009-11-04 00:00:39 +00:00
064c5fef11
For Thumb indirect branches, use "mov pc, reg" which does not switch
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between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.
llvm-svn: 85874
2009-11-03 06:29:56 +00:00
1c66e8a6b7
Put BlockAddresses into ARM constant pools.
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llvm-svn: 85824
2009-11-02 20:59:23 +00:00
6f29ad9170
Use cbz and cbnz instructions.
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llvm-svn: 85698
2009-10-31 23:46:45 +00:00
1cf0b03064
Add ARM codegen for indirect branches.
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clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
llvm-svn: 85577
2009-10-30 05:45:42 +00:00
453d64c9f5
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
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bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
llvm-svn: 85517
2009-10-29 18:10:34 +00:00
73789b848d
Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
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opcode and operand with a tab. Check for these instructions in the usual
places.
llvm-svn: 85411
2009-10-28 18:26:41 +00:00
b02bdb4552
Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
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llvm-svn: 85184
2009-10-27 00:08:59 +00:00
1b2b64f618
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
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ld / st pairs, etc.
llvm-svn: 83197
2009-10-01 08:22:27 +00:00
3bbc6c3ae6
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
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llvm-svn: 83191
2009-10-01 01:33:39 +00:00
bcad0c8421
Add "isBarrier = 1" to return instructions.
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Patch by Sylvere Teissier.
llvm-svn: 83135
2009-09-30 01:35:11 +00:00
a1c6495af7
Remove comments which don't add much to .s readibility.
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llvm-svn: 81306
2009-09-09 01:38:23 +00:00
d93c668f00
Calls clobber FPSCR.
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llvm-svn: 80956
2009-09-03 22:12:28 +00:00
4f835f1d7d
Remove .n suffix for some 16-bit opcodes now that Darwin assembler is fixed.
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llvm-svn: 80615
2009-08-31 20:14:07 +00:00
Evan Cheng