656e8515fc
x86 -- add the XTEST instruction
...
llvm-svn: 177888
2013-03-25 18:59:43 +00:00
fee7d21ae7
X86: Make sure we account for the FMA4 register immediate value, otherwise rip-rel relocations will be off by one byte.
...
PR15040.
llvm-svn: 173176
2013-01-22 18:05:59 +00:00
72beaa6733
Fix execution domain for packed FMA4 instructions.
...
llvm-svn: 168417
2012-11-21 08:08:21 +00:00
73cffddb95
Add support of RTM from TSX extension
...
- Add RTM code generation support throught 3 X86 intrinsics:
xbegin()/xend() to start/end a transaction region, and xabort() to abort a
tranaction region
llvm-svn: 167573
2012-11-08 07:28:54 +00:00
bbd10792c2
Introduce 'UseSSEx' to force SSE legacy encoding
...
- Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is
enabled.
As the penalty of inter-mixing SSE and AVX instructions, we need
prevent SSE legacy insn from being generated except explicitly
specified through some intrinsics. For patterns supported by both
SSE and AVX, so far, we force AVX insn will be tried first relying on
AddedComplexity or position in td file. It's error-prone and
introduces bugs accidentally.
'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited
by AVX, we need this predicate to force VEX encoding or SSE legacy
encoding only.
For insns not inherited by AVX, we still use the previous predicates,
i.e. 'HasSSEx'. So far, these insns fall into the following
categories:
* SSE insns with MMX operands
* SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH,
CRC, and etc.)
* SSE4A insns.
* MMX insns.
* x87 insns added by SSE.
2 test cases are modified:
- test/CodeGen/X86/fast-isel-x86-64.ll
AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be
selected by fast-isel due to complicated pattern and fast-isel
fallback to materialize it from constant pool.
- test/CodeGen/X86/widen_load-1.ll
AVX code generation is different from SSE one after fixing SSE/AVX
inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of
'vmovaps'.
llvm-svn: 162919
2012-08-30 16:54:46 +00:00
f881d385da
Fix patterns for CVTTPS2DQ to specify SSE2 instead of SSE1.
...
llvm-svn: 160941
2012-07-30 02:14:02 +00:00
7e9415220a
Make CVTDQ2PS instruction use SSE2 predicate instead of SSE1. No functional change because there are no patterns in the instructions. Also fix a typo in a comment.
...
llvm-svn: 159087
2012-06-23 20:52:45 +00:00
24e3418215
Move CVTPD2DQ to use SSE2 predicate instead of SSE3. Move DQ2PD and PD2DQ to the SSE2 section of the file.
...
llvm-svn: 159086
2012-06-23 20:15:42 +00:00
bf2409e8aa
Mark several instructions SSE2 instead of SSE3 as they should be.
...
llvm-svn: 158049
2012-06-06 06:45:27 +00:00
79dbb0c6e4
Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang.
...
llvm-svn: 157903
2012-06-03 18:58:46 +00:00
a0396e4583
X86: Rename the CLMUL target feature to PCLMUL.
...
It was renamed in gcc/gas a while ago and causes all kinds of
confusion because it was named differently in llvm and clang.
llvm-svn: 157745
2012-05-31 14:34:17 +00:00
09de6ae399
Added X86 Atom latencies to X86InstrMMX.td.
...
llvm-svn: 156615
2012-05-11 14:27:12 +00:00
fa3f6cb830
This patch continues the work of adding instruction latencies for X86 Atom,
...
by providing the latencies for the instructions in X86InstrFPStack.td.
llvm-svn: 155996
2012-05-02 16:03:35 +00:00
c0cef32b83
Remove HasSSE2 from AES and CLMUL predicates. It's now implied by the HasAES and HasCLMUL predicates.
...
llvm-svn: 155890
2012-05-01 05:35:02 +00:00
66a3597a4a
Add vmfunc instruction to X86 assembler and disassembler.
...
llvm-svn: 150899
2012-02-19 01:39:49 +00:00
b22310fda6
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
...
llvm-svn: 150878
2012-02-18 12:03:15 +00:00
ed7aa46366
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
...
llvm-svn: 150873
2012-02-18 08:19:49 +00:00
8523b16ff5
Instruction scheduling itinerary for Intel Atom.
...
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.
Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.
Adds a test to verify that the scheduler is working.
Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.
Patch by Preston Gurd!
llvm-svn: 149558
2012-02-01 23:20:51 +00:00
eb8f9e9e5b
Instruction selection priority fixes to remove the XMM/XMMInt/orAVX predicates. Another commit will remove orAVX functions from X86SubTarget.
...
llvm-svn: 147841
2012-01-10 06:30:56 +00:00
744f6311d3
Don't disable MMX support when AVX is enabled. Fix predicates for MMX instructions that were added along with SSE instructions to check for AVX in addition to SSE level.
...
llvm-svn: 147762
2012-01-09 00:11:29 +00:00
b910984458
Allow CRC32 instructions to be selected when AVX is enabled.
...
llvm-svn: 147411
2012-01-01 19:51:58 +00:00
1c064e0a89
Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers.
...
llvm-svn: 147409
2012-01-01 19:40:22 +00:00
cd93de93fa
Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation.
...
llvm-svn: 147366
2011-12-30 04:48:54 +00:00
d773607eee
Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions.
...
llvm-svn: 147353
2011-12-29 20:43:40 +00:00
97f05c5768
Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled along with CLMUL. That's required for the XMM registers to be valid for integer data. Doesn't change any behavior since the CLMUL instructions don't have patterns yet.
...
llvm-svn: 147345
2011-12-29 18:08:36 +00:00
1559123c77
Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along with AES. Since that's required for the XMM registers to be valid for integer data. Doesn't change any behavior though since you can't use an intrinsic with an illegal type anyway. Just makes it consistent with the VEX forms.
...
llvm-svn: 147344
2011-12-29 18:00:08 +00:00
64944090ff
Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
...
llvm-svn: 146709
2011-12-15 23:46:18 +00:00
7c0face455
XOP instructions and encoding tests.
...
llvm-svn: 146407
2011-12-12 19:37:49 +00:00
6dd2488383
XOP encoding bits and logic.
...
llvm-svn: 146397
2011-12-12 19:12:26 +00:00
557cda7f1d
Remove hasSSE1orAVX(). It's the same as hasXMM().
...
llvm-svn: 146246
2011-12-09 06:32:46 +00:00
4d1a2d449f
Many of the SSE patterns should not be selected when AVX is available. This led to the following code in X86Subtarget.cpp
...
if (HasAVX)
X86SSELevel = NoMMXSSE;
This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected.
However, this breaks instructions which do not have AVX variants.
The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX().
Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change.
However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case,
the prefetch instructions. rdar://10538297
llvm-svn: 146163
2011-12-08 19:00:42 +00:00
0f9a1f5e6c
This patch contains support for encoding FMA4 instructions and
...
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.
Patch by Jan Sjodin
llvm-svn: 145133
2011-11-25 19:33:42 +00:00
f01f1b5cb9
More AVX2 instructions and their intrinsics.
...
llvm-svn: 143895
2011-11-06 23:04:08 +00:00
05d1cb98e7
Add more AVX2 instructions and intrinsics.
...
llvm-svn: 143861
2011-11-06 06:12:20 +00:00
980d59832a
Add X86 RORX instruction
...
llvm-svn: 142741
2011-10-23 07:34:00 +00:00
96fa597828
Add X86 PEXTR and PDEP instructions.
...
llvm-svn: 142141
2011-10-16 16:50:08 +00:00
aea148c366
Add X86 BZHI instruction as well as BMI2 feature detection.
...
llvm-svn: 142122
2011-10-16 07:55:05 +00:00
f18c896337
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
...
llvm-svn: 141065
2011-10-04 06:30:42 +00:00
123dff0f58
- Handle special scalar_to_vector case: splats. Using a native 128-bit
...
shuffle before inserting on a 256-bit vector.
- Add AVX versions of movd/movq instructions
- Introduce a few COPY patterns to match insert_subvector instructions.
This turns a trivial insert_subvector instruction into a register copy,
coalescing the xmm into a ymm and avoid emiting on more instruction.
llvm-svn: 136002
2011-07-25 23:05:25 +00:00
415412e82f
Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269.
...
llvm-svn: 134424
2011-07-05 18:21:20 +00:00
fc4789da4a
Add support for the VIA PadLock instructions.
...
llvm-svn: 128826
2011-04-04 16:58:13 +00:00
cc53d9919f
Expand Op0Mask by one bit in preparation for the PadLock prefixes.
...
Define most shift masks incrementally to reduce the redundant
hard-coding. Introduce new shift for the VEX flags to replace the
magic constant 32 in various places.
llvm-svn: 128822
2011-04-04 15:58:30 +00:00
b60b0bc47e
Enabled disassembler support for AVX instructions
...
in the instruction tables and fixed a few bugs that
were causing decode conflicts. Rudimentary tests
are coming up in the next patch.
llvm-svn: 127646
2011-03-15 01:28:15 +00:00
e39062199e
Implement xgetbv and xsetbv.
...
Patch by Jai Menon.
llvm-svn: 126165
2011-02-22 00:35:18 +00:00
3a8ae23313
Fix some grammar in comments I noticed.
...
llvm-svn: 120416
2010-11-30 09:11:54 +00:00
ed13239dc0
This defaults to GenericDomain.
...
llvm-svn: 120415
2010-11-30 09:11:07 +00:00
ef62f57d4f
Implement a PseudoI class and transfer the sse instructions over to use
...
it.
llvm-svn: 120412
2010-11-30 08:57:23 +00:00
7ff334687d
fix the !eq operator in tblgen to return a bit instead of an int.
...
Use this to make the X86 and ARM targets set isCodeGenOnly=1
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.
llvm-svn: 117862
2010-10-31 19:22:57 +00:00
45270db916
Implement support for the bizarre 3DNow! encoding (which is unlike anything
...
else in X86), and add support for pavgusb. This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.
If someone else is interested in banging out the rest of the 3DNow!
instructions, it should be quite easy now.
llvm-svn: 115466
2010-10-03 18:08:05 +00:00
cea0a8d7ae
fix rdar://8444631 - encoder crash on 'enter'
...
What a weird instruction.
llvm-svn: 114190
2010-09-17 18:02:29 +00:00
a967c42a3d
Fix comment typos.
...
llvm-svn: 112202
2010-08-26 18:08:11 +00:00
f547740d3f
fix PR7465, mishandling of lcall and ljmp: intersegment long
...
call and jumps.
llvm-svn: 111496
2010-08-19 01:18:43 +00:00
beb506eeed
minor progress towards fixing PR7465
...
llvm-svn: 111494
2010-08-19 01:00:34 +00:00
ea0e05a3ce
Add AVX version of CLMUL instructions
...
llvm-svn: 109248
2010-07-23 18:41:12 +00:00
acd9230b1b
Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual
...
llvm-svn: 109204
2010-07-23 00:54:35 +00:00
3b505848fd
Add new AVX instruction vinsertf128
...
llvm-svn: 108892
2010-07-20 19:44:51 +00:00
14c5fd437c
Add AVX vbroadcast new instruction
...
llvm-svn: 108788
2010-07-20 00:11:13 +00:00
fd8bfcd6e1
AVX 256-bit conversion instructions
...
Add the x86 VEX_L form to handle special cases where VEX_L must be set.
llvm-svn: 108274
2010-07-13 21:07:28 +00:00
77a3c4462f
Since AVX is a superset of all SSE versions, only use HasAVX for AVX instructions
...
llvm-svn: 108222
2010-07-13 00:38:47 +00:00
ac5881295c
Implement the major chunk of PR7195: support for 'callw'
...
in the integrated assembler. Still some discussion to be
done.
llvm-svn: 107825
2010-07-07 22:27:31 +00:00
e2bd058d32
Add AVX vblendvpd, vblendvps and vpblendvb instructions
...
Update VEX encoding to support those new instructions
llvm-svn: 107715
2010-07-06 22:36:24 +00:00
05166740eb
- Add AVX SSE2 Move doubleword and quadword instructions.
...
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
in the .td file now have a AVX encoded form already working.
llvm-svn: 107365
2010-07-01 01:20:06 +00:00
83651094ad
Reapply r106896:
...
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg
llvm-svn: 106912
2010-06-25 23:33:42 +00:00
191a1cd2bb
Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases
...
llvm-svn: 106705
2010-06-24 00:32:06 +00:00
1e13c17a55
Add AVX compare packed instructions
...
llvm-svn: 106600
2010-06-22 23:37:59 +00:00
1a890f9dc0
Add AVX MOV{SS,SD}{rr,rm} instructions
...
llvm-svn: 106588
2010-06-22 22:38:56 +00:00
66d2d57d9b
Fix typo, SSE1 should be used by XS, not SSE2
...
llvm-svn: 106357
2010-06-18 23:53:27 +00:00
2bfad417a1
Apply some refactor to packed instructions
...
llvm-svn: 106349
2010-06-18 23:13:35 +00:00
6b98f7129f
Use new tablegen resources in SSE tablegen code. This will
...
be done incrementally and intermixed with the adding of more
AVX instructions. This is a first step in that direction
llvm-svn: 106251
2010-06-17 23:05:30 +00:00
b06f54b852
More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rr
...
Handle OpSize TSFlag for AVX
llvm-svn: 105869
2010-06-12 01:23:26 +00:00
c2f87b7bb2
Reapply r105521, this time appending "LLU" to 64 bit
...
immediates to avoid breaking the build.
llvm-svn: 105652
2010-06-08 22:51:23 +00:00
fdd2614330
revert r105521, which is breaking the buildbots with stuff like this:
...
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
llvm-svn: 105524
2010-06-05 04:17:30 +00:00
594fa26317
Initial AVX support for some instructions. No patterns matched
...
yet, only assembly encoding support.
llvm-svn: 105521
2010-06-05 03:53:24 +00:00
1290fa0f72
Remove FIXME.
...
llvm-svn: 100466
2010-04-05 21:14:32 +00:00
b93331f3be
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
...
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
llvm-svn: 100384
2010-04-05 03:10:20 +00:00
2ef63183a5
Separate out the AES-NI instructions from the SSE4.2 instructions. Add
...
a new subtarget option for AES and check for the support. Add "westmere"
line of processors and add AES-NI support to the core i7.
Add a couple of TODOs for information I couldn't verify.
llvm-svn: 100231
2010-04-02 21:54:27 +00:00
dbff4e8103
Renumber SSE execution domains for better code size.
...
SSEDomainFix will collapse to the domain with the lower number when it has a
choice. The SSEPackedSingle domain often has smaller instructions, so prefer
that.
llvm-svn: 99952
2010-03-30 22:46:53 +00:00
f8d7eda663
Teach TableGen to understand X.Y notation in the TSFlagsFields strings.
...
Remove much horribleness from X86InstrFormats as a result. Similar
simplifications are probably possible for other targets.
llvm-svn: 99539
2010-03-25 18:52:01 +00:00
49e121d5e4
Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings.
...
On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register
in a different domain than where it was defined. Some instructions have
equvivalents for different domains, like por/orps/orpd.
The SSEDomainFix pass tries to minimize the number of domain crossings by
changing between equvivalent opcodes where possible.
This is a work in progress, in particular the pass doesn't do anything yet. SSE
instructions are tagged with their execution domain in TableGen using the last
two bits of TSFlags. Note that not all instructions are tagged correctly. Life
just isn't that simple.
The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline
issue handled by NEONMoveFixPass. This pass may become target independent to
handle both.
llvm-svn: 99524
2010-03-25 17:25:00 +00:00
b96eb68497
Fixed the SS42AI template for the SSE 4.2 instructions with TA prefix so it does
...
not get an "Unknown immediate size" assert failure when used. All instructions
of this form have an 8-bit immediate. Also added a test case of an example
instruction that is of this form.
llvm-svn: 99435
2010-03-24 22:28:42 +00:00
4d804d794f
Added the rdtscp instruction to the x86 instruction
...
tables.
llvm-svn: 96073
2010-02-13 02:06:11 +00:00
140caa7240
remove special cases for vmlaunch, vmresume, vmxoff, and swapgs
...
fix swapgs to be spelled right.
llvm-svn: 96058
2010-02-13 00:41:14 +00:00
12455ca03d
enhance the immediate field encoding to know whether the immediate
...
is pc relative or not, mark call and branches as pcrel.
llvm-svn: 96026
2010-02-12 22:27:07 +00:00
f7477e599f
add a bunch of mod/rm encoding types for fixed mod/rm bytes.
...
This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.
llvm-svn: 95960
2010-02-12 02:06:33 +00:00
04d8cb74f3
Instruction fixes, added instructions, and AsmString changes in the
...
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
llvm-svn: 91638
2009-12-18 00:01:26 +00:00
5ca7b345b9
PR 5245 - The imediate size target flag was not set on 3A-prefixed SSSE3 instructions.
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llvm-svn: 84506
2009-10-19 17:31:16 +00:00
050e0cdb9a
Modified the Intel instruction tables to include
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versions of CALL and JMP with segmented addresses
provided in-line, as pairs of immediates.
llvm-svn: 81818
2009-09-15 00:35:17 +00:00
9fe912de5f
Implement sse4.2 string/text processing instructions:
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Add patterns and instruction encoding information.
Add custom lowering to deal with hardwired return register of
uncertain type (xmm0).
llvm-svn: 79377
2009-08-18 22:50:32 +00:00
7dfa9f2e56
Add crc32 instruction and intrinsics. Add a new class of prefix
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bytes for F2 0F 38 and propagate. Add a FIXME for a set
of possibilities which correspond to intrinsics already used.
New test.
llvm-svn: 78508
2009-08-08 21:55:08 +00:00
2589777f3f
Add ability to override segment (mostly for code emitter purposes).
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llvm-svn: 57380
2008-10-11 19:09:15 +00:00
76105a4a4f
Make "movdq2q" and "movq2dq" dependent upon having SSE2 because they use the
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SSE2 registers as well as the MMX registers.
llvm-svn: 55436
2008-08-27 21:32:04 +00:00
6cfd3830fb
Nevermind. This broke the bootstrap (?!).
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llvm-svn: 55318
2008-08-25 18:32:39 +00:00
dd6759aea7
MOVQ2DQ and MOVQ2DQ use SSE2. We should conditionalize the use of these
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instructions on having SSE2.
llvm-svn: 55317
2008-08-25 18:20:52 +00:00
31099519d0
Provide a 64 bit variant of mmx.maskmovq intrinsic lowering.
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Is there way to avoid explicit target check?
llvm-svn: 55238
2008-08-23 15:53:19 +00:00
a21bdda961
Fix comment spacing.
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llvm-svn: 55047
2008-08-20 13:46:21 +00:00
55b7becb29
SSE codegen for vsetcc nodes
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llvm-svn: 53719
2008-07-17 16:51:19 +00:00
96bdbd6c5d
Fix a number of encoding bugs. SSE 4.1 instructions MPSADBWrri, PINSRDrr, etc. have 8-bits immediate field (ImmT == Imm8).
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llvm-svn: 48360
2008-03-14 07:39:27 +00:00
0070dd1de3
Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode.
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llvm-svn: 47795
2008-03-01 13:37:02 +00:00
8ef50214f0
SSE4.1 64b integer insert/extract pattern support
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Move formats into the formats file
llvm-svn: 47035
2008-02-12 22:51:28 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
01c7c198ee
Fix JIT encoding for CMPSD as well.
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llvm-svn: 45268
2007-12-20 19:57:09 +00:00
dab6bd902e
Fix the JIT encoding of cmp*ss, which aborts with this assertion currently:
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X86CodeEmitter.cpp:378: failed assertion `0 && "Immediate size not set!"'
I *think* this is right, but Evan, please verify. It also looks like
CMPSDrr and maybe others are missing this info. Evan, plz investigate.
llvm-svn: 45074
2007-12-16 20:12:41 +00:00
12c6be84ff
Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load )
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llvm-svn: 40628
2007-07-31 08:04:03 +00:00
Dave Zarzycki