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Author SHA1 Message Date
Ulrich Weigand 18f6930fef [SystemZ] Support vector registers in inline asm 
This adds support for specifying vector registers for use with inline
asm statements, either via the 'v' constraint or by explicit register
names (v0 ... v31).

llvm-svn: 326609
 2018-03-02 20:36:34 +00:00