Commit Graph

159261 Commits

Author SHA1 Message Date
Reid Kleckner b525872288 [CodeView] Sink complex inline functions to .cpp file, NFC
I'm cleaning up this code before I attempt to fix a line table bug.

llvm-svn: 322904
2018-01-18 22:55:14 +00:00
Changpeng Fang 4737e892de AMDGPU/SI: Add d16 support for image intrinsics.
Summary:
  This patch implements d16 support for image load, image store and image sample intrinsics.

Reviewers:
  Matt, Brian.

Differential Revision:
  https://reviews.llvm.org/D3991

llvm-svn: 322903
2018-01-18 22:08:53 +00:00
Eric Christopher 668e6b4b05 Typo fix SIBABRT -> SIGABRT.
Based on a patch by Henry Wong!

llvm-svn: 322902
2018-01-18 21:45:51 +00:00
Martin Storsjo d96be854e5 [test] Actually check the common parts in CodeGen/ARM/global-merge-external.ll. NFC.
Previously, these parts weren't ever checked. The label patterns
need to be extended to match successfully on macho.

Differential Revision: https://reviews.llvm.org/D42126

llvm-svn: 322900
2018-01-18 21:21:48 +00:00
Peter Collingbourne 719c1f7405 Support: Add missing #include.
This #include is necessary to provide the definitions of _fpclass
and _FPCLASS_NZ when building with libc++.

llvm-svn: 322885
2018-01-18 20:49:33 +00:00
Paul Robinson 8181d23b3d [DWARFv5] Number the line-table's directory array correctly.
The compilation directory has always been #0, but as of DWARF v5 it is
explicitly listed in the line-table section instead of implicitly
being a reference to the compile_unit DIE's DW_AT_comp_dir attribute.
This means the dumper should number the dumped array starting with 0
or 1 depending on the DWARF version of the line table.

References in the generated DWARF are correct, it's just the dumper
that was wrong.  Also some assembler-coded tests were similarly
confused about directory numbers.

llvm-svn: 322884
2018-01-18 20:33:35 +00:00
Sylvestre Ledru 6dce59bc37 we have now https support for apt.llvm.org. Updating the URL
llvm-svn: 322881
2018-01-18 19:57:35 +00:00
Dimitry Andric aad72b77c6 Follow-up to rL322875 by initializing the do_libcxxabi variable properly.
llvm-svn: 322879
2018-01-18 19:30:30 +00:00
Amara Emerson d5785775f8 [AArch64][GlobalISel] Add isel support for global values in the large code model.
Fixes PR35958.

Differential Revision: https://reviews.llvm.org/D42175

llvm-svn: 322878
2018-01-18 19:21:27 +00:00
Simon Pilgrim f7ca8ff071 [X86][SSE] Regenerate vector promotion tests
llvm-svn: 322877
2018-01-18 19:17:26 +00:00
Ana Pazos 1b57c7a0f4 [RISCV] Fixed setting predicates for compressed instructions.
Summary:
Fixed setting predicates for compressed instructions.
Some instructions were being generated with C extension
enabled only, without proper checks for the other
required extensions like F, D and 32 and 64-bit target checks.
Affected instructions:
C_FLD, C_FLW, C_LD, C_FSD, C_FSW, C_SD,
C_JAL, C_ADDIW, C_SUBW, C_ADDW,
C_FLDSP, C_FLWSP, C_LDSP, C_FSDSP, C_FSWSP, C_SDSP

Reviewers: asb, shiva0217

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, llvm-commits

Differential Revision: https://reviews.llvm.org/D42132

llvm-svn: 322876
2018-01-18 18:54:05 +00:00
Dimitry Andric d05541f7d6 Add a -no-libcxxabi option to the test-release.sh script.
On FreeBSD, it is currently not possible to build libcxxabi and link
against it, so we have been building releases with -no-libs for quite
some time.

However, libcxx and libunwind should build without problems, so provide
an option to skip just libcxxabi.

llvm-svn: 322875
2018-01-18 18:39:13 +00:00
Simon Pilgrim 3c8e2bf830 [X86][AVX] Add 256/512-bit slow PMULLD tests
llvm-svn: 322874
2018-01-18 18:38:32 +00:00
Zachary Turner 1bc2ce6b9b Speed up iteration of CodeView record streams.
There's some abstraction overhead in the underlying
mechanisms that were being used, and it was leading to an
abundance of small but not-free copies being made.  This
showed up on a profile.  Eliminating this and going back to
a low-level byte-based implementation speeds up lld with
/DEBUG between 10 and 15%.

Differential Revision: https://reviews.llvm.org/D42148

llvm-svn: 322871
2018-01-18 18:35:01 +00:00
Francis Visoiu Mistrih eb3f76fc83 [CodeGen][NFC] Rename IsVerbose to IsStandalone in Machine*::print
Committed r322867 too soon.

Differential Revision: https://reviews.llvm.org/D42239

llvm-svn: 322868
2018-01-18 18:05:15 +00:00
Francis Visoiu Mistrih 378b5f3de6 [CodeGen] Print RegClasses on MI in verbose mode
r322086 removed the trailing information describing reg classes for each
register.

This patch adds printing reg classes next to every register when
individual operands/instructions/basic blocks are printed. In the case
of dumping MIR or printing a full function, by default don't print it.

Differential Revision: https://reviews.llvm.org/D42239

llvm-svn: 322867
2018-01-18 17:59:06 +00:00
Alexey Bataev a2d6fe4ab4 [SLP] Fix test checks, NFC.
llvm-svn: 322865
2018-01-18 17:34:27 +00:00
Benjamin Kramer 0a2193054b [ADT] Just give up on GCC, I can't fix this.
While the memmove workaround fixed it for GCC 6.3. GCC 4.8 and GCC 7.1
are still broken. I have no clue what's going on, just blacklist GCC for
now.

Needless to say this code is ubsan, asan and msan-clean.

llvm-svn: 322862
2018-01-18 16:23:40 +00:00
Benjamin Kramer 6b5c300327 [ADT] Add a workaround for GCC miscompiling the trivially copyable Optional
I've seen random crashes with GCC 4.8, GCC 6.3 and GCC 7.3, triggered by
my Optional change. All of them affect a different set of targets. This
change fixes the instance of the problem I'm seeing on my local machine,
let's hope it's good enough for the other instances too.

llvm-svn: 322859
2018-01-18 15:47:59 +00:00
Sanjay Patel 0e690b05d1 [TargetLowering] add punctuation for readability; NFC
llvm-svn: 322855
2018-01-18 15:25:32 +00:00
Sam McCall 768efb5379 [MachineOutliner] Fix r322788 - don't write to working directory
llvm-svn: 322850
2018-01-18 15:02:28 +00:00
Joel Jones 57c22698f5 [docs] Make ReleaseProcess.rst 80 column. NFCI
llvm-svn: 322849
2018-01-18 14:57:55 +00:00
Francis Visoiu Mistrih 586444e42b [CodeGen][NFC] Refactor MachineInstr::print
* Handle more cases where the MI is not attached yet
* Add similar asserts like in MIRPrinter::print

llvm-svn: 322848
2018-01-18 14:52:14 +00:00
Benjamin Kramer bfc1d976ca [HWAsan] Fix uninitialized variable.
Found by msan.

llvm-svn: 322847
2018-01-18 14:19:04 +00:00
Simon Pilgrim dc25e1d8e2 [X86] Add PR35918 test case
llvm-svn: 322846
2018-01-18 13:42:02 +00:00
Klaus Kretzschmar c47e7214f1 test commit
llvm-svn: 322844
2018-01-18 12:58:50 +00:00
Alex Bradbury 921383828e [RISCV] Codegen support for the standard RV32M instruction set extension
llvm-svn: 322843
2018-01-18 12:36:38 +00:00
Alex Bradbury 7d6aa1f7ae [RISCV] Implement frame pointer elimination
llvm-svn: 322839
2018-01-18 11:34:02 +00:00
Benjamin Kramer c806d39182 [ADT] Split optional to only include copy mechanics and dtor for non-trivial types.
This makes uses of Optional more transparent to the compiler (and
clang-tidy) and generates slightly smaller code.

This is a re-land of r317019, which had issues with GCC 4.8 back then.
Those issues don't reproduce anymore, but I'll watch the buildbots
closely in case anything goes wrong.

llvm-svn: 322838
2018-01-18 11:26:24 +00:00
Andrew V. Tischenko 360974a559 A new test to demostrate the current SHLD/SHRD code generation.
llvm-svn: 322828
2018-01-18 10:40:48 +00:00
Alex Bradbury d3263aa1df [RISCV][NFC] Add nounwind to functions in div.ll and mul.ll
Committing this separately to minimise irrelevant changes for an upcoming 
patch.

llvm-svn: 322825
2018-01-18 09:41:14 +00:00
Sam Parker 1f8c035d6b [SelectionDAG] Convert assert to condtion
Follow-up to r322120 which can cause assertions for AArch64 because
v1f64 and v1i64 are legal types.

Differential Revision: https://reviews.llvm.org/D42097

llvm-svn: 322823
2018-01-18 09:22:24 +00:00
Craig Topper 83b0a98902 [X86] Use vmovdqu64/vmovdqa64 for unmasked integer vector stores for consistency with loads.
Previously we used 64 for vXi64 stores and 32 for everything else. This change uses 64 for everything just like do for loads.

llvm-svn: 322820
2018-01-18 07:44:09 +00:00
Craig Topper 21c8a8fa49 [X86] Remove isel patterns for using unmasked vmovdqa32/vmovdqu32 for integer vector loads.
These patterns were just looking for a vXi64 bitcasted to vXi32, but there is no advantage to using vmovdqa32 over vmovdqa64.

llvm-svn: 322819
2018-01-18 07:44:06 +00:00
Clement Courbet 899d6980fa Revert "Add a value_type to ArrayRef."
clang OOMs on arm.

This reverts commit a272b2f2ef63f7f602c9ef4d9e10dc4eb9f00aa1.

llvm-svn: 322818
2018-01-18 07:26:34 +00:00
Craig Topper 6620a69f18 [X86] Remove windows line endings from a test file. NFC
llvm-svn: 322817
2018-01-18 06:47:09 +00:00
Rafael Espindola 8a1ca67461 Don't drop dso_local in LTO.
LTO sets dso_local as an optimization, so don't clear it.

This avoid clearing it from undefined hidden symbols, which would then
fail the verifier.

llvm-svn: 322814
2018-01-18 05:38:43 +00:00
Craig Topper 7f0d85ec1e [DAGCombiner] Add a DAG combine to turn a splat build_vector where the splat elemnt is a bitcast from a vector type into a concat_vector
For example, a build_vector of i64 bitcasted from v2i32 can be turned into a concat_vectors of the v2i32 vectors with a bitcast to a vXi64 type

Differential Revision: https://reviews.llvm.org/D42090

llvm-svn: 322811
2018-01-18 04:17:06 +00:00
Rafael Espindola 9fbc040599 Make GlobalValues with non-default visibilility dso_local.
This is similar to r322317, but for visibility. It is not as neat
because we have to special case extern_weak.

The idea is the same as the previous change, make the transition to
explicit dso_local easier for the frontends. With this they only have
to add dso_local to symbols where we need some external information to
decide if it is dso_local (like it being part of an ELF executable).

llvm-svn: 322806
2018-01-18 02:08:23 +00:00
Justin Bogner a9346e050f GlobalISel: Make MachineCSE runnable in the middle of the GlobalISel
Right now, it is not possible to run MachineCSE in the middle of the
GlobalISel pipeline. Being able to run generic optimizations between the
core passes of GlobalISel was one of the goals of the new ISel framework.
This is the first attempt to do it.

The problem is that MachineCSE pass assumes all register operands have a
register class, which, in GlobalISel context, won't be true until after the
InstructionSelect pass. The reason for this behaviour is that before
replacing one virtual register with another, MachineCSE pass (and most of
the other optimization machine passes) must check if the virtual registers'
constraints have a (sufficiently large) intersection, and constrain the
resulting register appropriately if such intersection exists.

GlobalISel extends the representation of such constraints from just a
register class to a triple (low-level type, register bank, register
class).

This commit adds MachineRegisterInfo::constrainRegAttrs method that extends
MachineRegisterInfo::constrainRegClass to such a triple.

The idea is that going forward we should use:

- RegisterBankInfo::constrainGenericRegister within GlobalISel's
  InstructionSelect pass
- MachineRegisterInfo::constrainRegClass within SelectionDAG ISel
- MachineRegisterInfo::constrainRegAttrs everywhere else regardless
  the target and instruction selector it uses.

Patch by Roman Tereshin. Thanks!

llvm-svn: 322805
2018-01-18 02:06:56 +00:00
Derek Schuff 53b3855b2b [WebAssembly] Remove duplicated RTLIB names
Remove the tight coupling between llvm/CodeGenRuntimeLibcalls.def and
the table of supported singatures for wasm. This will allow adding new libcalls
without changing wasm's signature table.

Also, some cleanup:
Use ManagedStatics instead of const tables to avoid memory/binary bloat.
Use a StringMap instead of a linear search for name lookup.

Differential Revision: https://reviews.llvm.org/D35592

llvm-svn: 322802
2018-01-18 01:15:45 +00:00
Volkan Keles 4aa73a649a Fix the failure caused by r322773
Do not run GlobalISel if `-fast-isel=0 -global-isel=false`.

llvm-svn: 322800
2018-01-18 01:10:30 +00:00
Jessica Paquette 729e68693f [MachineOutliner] Add DISubprograms to outlined functions.
Before, it wasn't possible to get backtraces inside outlined functions. This
commit adds DISubprograms to the IR functions created by the outliner which
makes this possible. Also attached a test that ensures that the produced
debug information is correct. This is useful to users that want to debug
outlined code.

llvm-svn: 322789
2018-01-18 00:00:58 +00:00
Reid Kleckner 1aa9061c5f [CodeGen] Hoist common AsmPrinter code out of X86, ARM, and AArch64
Every known PE COFF target emits /EXPORT: linker flags into a .drective
section. The AsmPrinter should handle this.

While we're at it, use global_values() and emit each export flag with
its own .ascii directive. This should make the .s file output more
readable.

llvm-svn: 322788
2018-01-17 23:55:23 +00:00
Florian Hahn edae5a6e11 [LangRef] Clarify Varargs forwarding for musttail calls.
This clarification was suggested by @efriedma in D41335, which uses this
behavior to inline musttail calls with varargs.

Reviewers: hfinkel, efriedma, rnk

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D41861

llvm-svn: 322786
2018-01-17 23:29:25 +00:00
Evgeniy Stepanov 5bd669dc8f [hwasan] LLVM-level flags for linux kernel-compatible hwasan instrumentation.
Summary:
-hwasan-mapping-offset defines the non-zero shadow base address.
-hwasan-kernel disables calls to __hwasan_init in module constructors.
Unlike ASan, -hwasan-kernel does not force callback instrumentation.
This is controlled separately with -hwasan-instrument-with-calls.

Reviewers: kcc

Subscribers: srhines, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D42141

llvm-svn: 322785
2018-01-17 23:24:38 +00:00
Volkan Keles a79b0620a0 Add a TargetOption to enable/disable GlobalISel
Summary:
This patch adds a new target option in order to control GlobalISel.
This will allow the users to enable/disable GlobalISel prior to the
backend by calling `TargetMachine::setGlobalISel(bool Enable)`.

No test case as there is already a test to check GlobalISel
command line options.
See: CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll.

Reviewers: qcolombet, aemerson, ab, dsanders

Reviewed By: qcolombet

Subscribers: rovka, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D42137

llvm-svn: 322773
2018-01-17 22:34:21 +00:00
Benjamin Kramer 8b1986b5cb Add support for emitting libcalls for x86_fp80 -> fp128 and vice-versa
compiler_rt doesn't provide them (yet), but libgcc does. PR34076.

llvm-svn: 322772
2018-01-17 22:29:16 +00:00
Easwaran Raman e5b8de2f1f Add a ProfileCount class to represent entry counts.
Summary:
The class wraps a uint64_t and an enum to represent the type of profile
count (real and synthetic) with some helper methods.

Reviewers: davidxl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41883

llvm-svn: 322771
2018-01-17 22:24:23 +00:00
Simon Pilgrim d109b5e027 [X86][MMX] Add PR35982 test cases
FEMMS has the same problem as EMMS

llvm-svn: 322770
2018-01-17 22:19:31 +00:00
Eli Friedman c60a23a6af [LegalizeDAG] Fix ATOMIC_CMP_SWAP_WITH_SUCCESS legalization.
The code wasn't zero-extending correctly, so the comparison could
spuriously fail.

Adds some AArch64 tests to cover this case.

Inspired by D41791.

Differential Revision: https://reviews.llvm.org/D41798

llvm-svn: 322767
2018-01-17 22:04:36 +00:00
Javed Absar 1e28194a40 [SCEV] Fix typo. NFC.
Fix confusing typo in comment.

llvm-svn: 322765
2018-01-17 21:58:35 +00:00
Daniel Sanders 12e6e709e9 [globalisel][tablegen] Honour priority order within nested instructions.
It appears that we haven't been prioritizing rules that contain nested
instructions properly. InstructionOperandMatcher didn't override
isHigherPriorityThan so it never compared the instructions/operands/predicates
inside nested instructions.

Fixes PR35926. Thanks to Diana Picus for the bug report.

llvm-svn: 322754
2018-01-17 20:34:29 +00:00
Zaara Syeda c9dc7b451b Revert [PowerPC] This reverts commit rL322721
Failing build bots. Revert the commit now.

llvm-svn: 322748
2018-01-17 20:00:15 +00:00
Philip Reames f5ff5d584e [MDA] Use common code instead of reimplementing same. [NFC]
llvm-svn: 322747
2018-01-17 19:57:19 +00:00
Aditya Nandakumar 18b3f9d384 [GISel] Make constrainSelectedInstRegOperands() available to the legalizer. NFC
https://reviews.llvm.org/D42149

llvm-svn: 322743
2018-01-17 19:31:33 +00:00
Sam Clegg 9f3fe42e19 [WebAssembly] Remove debug names from symbol table
Get rid of DEBUG_FUNCTION_NAME symbols. When we actually debug
data, maybe we'll want somewhere to put it... but having a symbol
that just stores the name of another symbol seems odd.
It means you have multiple Symbols with the same name, one
containing the actual function and another containing the name!

Store the names in a vector on the WasmObjectFile when reading
them in. Also stash them on the WasmFunctions themselves.
The names are //not// "symbol names" or aliases or anything,
they're just the name that a debugger should show against the
function body itself. NB. The WasmObjectFile stores them so that
they can be exported in the YAML losslessly, and hence the tests
can be precise.

Enforce that the CODE section has been read in before reading
the "names" section. Requires minor adjustment to some tests.

Patch by Nicholas Wilson!

Differential Revision: https://reviews.llvm.org/D42075

llvm-svn: 322741
2018-01-17 19:28:43 +00:00
Rafael Espindola d700869235 Use a got to access a hidden weak undefined on MachO.
Trying to link

__attribute__((weak, visibility("hidden"))) extern int foo;
int *main(void) {
  return &foo;
}

on OS X fails with

ld: 32-bit RIP relative reference out of range (-4294971318 max is +/-2GB): from _main (0x100000FAB) to _foo@0x00001000 (0x00000000) in '_main' from test.o for architecture x86_64

The problem being that 0 cannot be computed as a fixed difference from
%rip. Exactly the same issue exists on ELF and we can use the same
solution.

llvm-svn: 322739
2018-01-17 19:19:55 +00:00
Joel Galenson bbcaf4ac5c [ARM] Optimize {s,u}mul.with.overflow.
This extends my previous patches to also optimize overflow-checked multiplies during SelectionDAG.

Differential revision: https://reviews.llvm.org/D40922

llvm-svn: 322738
2018-01-17 19:19:05 +00:00
Joel Galenson fe7fa40869 [ARM] Optimize {s,u}{add,sub}.with.overflow.
The ARM backend contains code that tries to optimize compares by replacing them with an existing instruction that sets the flags the same way. This allows it to replace a "cmp" with a "adds", generalizing the code that replaces "cmp" with "sub". It also heuristically disables sinking of instructions that could potentially be used to replace compares (currently only if they're next to each other).

Differential revision: https://reviews.llvm.org/D38378

llvm-svn: 322737
2018-01-17 19:19:05 +00:00
Daniel Neilson 88dddb8948 [Attributes] Fix crash when attempting to remove alignment from an attribute list/set
Summary:
 Discovered while working on a patch to move alignment in
@llvm.memcpy/move/set from an arg into parameter attributes.

 The current implementations of AttributeSet::removeAttribute() and
AttributeList::removeAttribute crash when attempting to remove the
alignment attribute. Currently, these implementations add the
to-be-removed attributes to an AttrBuilder and then remove
the builder from the list/set. Alignment is special in that it
must be added to a builder with an integer value for the alignment;
attempts to add alignment to a builder without a value is an error.

 This change fixes the removeAttribute implementations for AttributeSet and
AttributeList to make them able to remove the alignment, and other similar,
attributes.

Reviewers: rnk, chandlerc, pete, javed.absar, reames

Reviewed By: rnk

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41951

llvm-svn: 322735
2018-01-17 19:15:21 +00:00
Simon Pilgrim 8c87a2e7bd [X86][BTVER2] Reduce instregex usage (PR35955)
Most are just replaced with instrs lists, but a few regexps have been further generalized to match more instructions with a single pattern.

llvm-svn: 322734
2018-01-17 19:12:48 +00:00
Sanjay Patel 218a0b51dd [InstCombine] add baseline tests for D39958; NFC
llvm-svn: 322733
2018-01-17 19:04:18 +00:00
Craig Topper b70ca5060f [X86] Teach LowerBUILD_VECTOR to recognize pair-wise splats of 32-bit elements and use a 64-bit broadcast
If we are splatting pairs of 32-bit elements, we can use a 64-bit broadcast to get the job done.

We could probably could probably do this with other sizes too, for example four 16-bit elements. Or we could broadcast pairs of 16-bit elements using a 32-bit element broadcast. But I've left that as a future improvement.

I've also restricted this to AVX2 only because we can only broadcast loads under AVX.

Differential Revision: https://reviews.llvm.org/D42086

llvm-svn: 322730
2018-01-17 18:58:22 +00:00
Fangrui Song c4526fc5af [utils] Make .cfi_startproc optional for powerpc
Summary: llc sometimes may not emit .cfi_startproc which makes func_dict to have less entries.

Subscribers: nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D42144

llvm-svn: 322725
2018-01-17 18:48:50 +00:00
Craig Topper 279ace187a [X86] When legalizing (v64i1 select i8, v64i1, v64i1) make sure not to introduce bitcasts to i64 in 32-bit mode
We legalize selects of masks with scalar conditions using a bitcast to an integer type. But if we are in 32-bit mode we can't convert v64i1 to i64. So instead split the v64i1 to v32i1 and concat it back together. Each half will then be legalized by bitcasting to i32 which is fine.

The test case is a little indirect. If we have the v64i1 select in IR it will get legalized by legalize vector ops which has a run of type legalization after it. That type legalization run is able to fix this i64 bitcast. So in order to avoid that we need a build_vector of a splat which legalize vector ops will ignore. Legalize DAG will then turn that into a select via LowerBUILD_VECTORvXi1. And the select will get legalized. In this case there is no type legalizer run to cleanup the bitcast.

This fixes pr35972.

llvm-svn: 322724
2018-01-17 18:46:01 +00:00
Simon Pilgrim 3274d35a0d [X86][SSE] Add v4i16 PMULLD tests
llvm-svn: 322723
2018-01-17 18:41:27 +00:00
Zaara Syeda 8e951fd2f6 [PowerPC] Add handling for ColdCC calling convention and a pass to mark
candidates with coldcc attribute.

This patch adds support for the coldcc calling convention for Power.
This changes the set of non-volatile registers. It includes a pass to stress
test the implementation by marking all static directly called functions with
the coldcc attribute through the option -enable-coldcc-stress-test. It also
includes an option, -ppc-enable-coldcc, to add the coldcc attribute to
functions which are cold at all call sites based on BlockFrequencyInfo when
the containing function does not call any non cold functions.

Differential Revision: https://reviews.llvm.org/D38413

llvm-svn: 322721
2018-01-17 18:22:55 +00:00
Simon Pilgrim e01b58f0ed Fix MSVC "not all control paths return a value" warning.
llvm-svn: 322719
2018-01-17 18:16:28 +00:00
Tatyana Krasnukha 8979eea04e [ARC] Add missing condition codes.
Summary: Added VS and VC, required for disassembling.

Reviewers: petecoup

Reviewed By: petecoup

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D42172

llvm-svn: 322718
2018-01-17 17:58:28 +00:00
Jonas Paulsson ef785694f2 [SystemZ] Handle BRCTH branches correctly in SystemZLongBranch.cpp.
BRCTH is capable of a long branch which needs to be recognized during branch
relaxation. This is done by checking for ExtraRelaxSize == 0.

Review: Ulrich Weigand
llvm-svn: 322688
2018-01-17 17:16:07 +00:00
Matt Arsenault 1491ca8911 AMDGPU: Error in SIAnnotateControlFlow instead of assert
This assert typically happens if an unstructured CFG is passed
to the pass. This can happen if the pass is run independently
without the structurizer.

llvm-svn: 322685
2018-01-17 16:30:01 +00:00
Matt Arsenault 0cfebd94c2 Add tests for ConstantFoldTerminator preserving DomTree
With my bad luck I separately implemented the DomTree preservation
for ConstantFoldTerminator before r322401 was committed. Commit the
tests which I think still provide some value.

llvm-svn: 322683
2018-01-17 16:27:17 +00:00
Diana Picus 01bcfd2112 [ARM GlobalISel] Rename local variable. NFC
llvm-svn: 322667
2018-01-17 15:25:37 +00:00
Diana Picus 4652e25030 [ARM GlobalISel] Add instselect tests for G_FPEXT and G_FPTRUNC
G_FPEXT and G_FPTRUNC are handled by TableGen'erated code, just add
tests.

llvm-svn: 322665
2018-01-17 15:01:19 +00:00
Pablo Barrio f2c29571da [AArch64] Fix incorrect LD1 of 16-bit FP vectors in big endian
Summary:
Loading a vector of 4 half-precision FP sometimes results in an LD1
of 2 single-precision FP + a reversal. This results in an incorrect
byte swap due to the conversion from little endian to big endian.

In order to generate the correct byte swap, it is easier to
generate the correct LD1 of 4 half-precision FP, thus avoiding the
subsequent reversal.

Reviewers: craig.topper, jmolloy, olista01

Reviewed By: olista01

Subscribers: efriedma, samparker, SjoerdMeijer, rogfer01, aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D41863

llvm-svn: 322663
2018-01-17 14:39:29 +00:00
Sanjay Patel aa766efd09 [InstCombine] fix demanded-bits propagation for zext/trunc
I was comparing the demanded-bits implementations between InstCombine
and TargetLowering as part of investigating questions in D42088 and
noticed that this was wrong in IR. We were losing all of the prior
known bits when we got back to the 'zext'.

llvm-svn: 322662
2018-01-17 14:39:28 +00:00
Sanjay Patel 178deccb63 [InstCombine] add test to show hole in demanded bits; NFC
llvm-svn: 322660
2018-01-17 14:27:35 +00:00
Alex Bradbury d93f889d89 [RISCV] Allow RISCVAsmBackend::writeNopData to generate c.nop when supported
When the compressed instruction set is enabled, the 16-bit c.nop can be
generated if necessary.

Differential Revision: https://reviews.llvm.org/D41221
Patch by Shiva Chen.

llvm-svn: 322658
2018-01-17 14:17:12 +00:00
Diana Picus c62a16234b [ARM GlobalISel] Map G_FPEXT and G_FPTRUNC to FPR
llvm-svn: 322657
2018-01-17 14:14:14 +00:00
Daniil Fukalov d5fca554e2 [AMDGPU] add LDS f32 intrinsics
added llvm.amdgcn.atomic.{add|min|max}.f32 intrinsics
to allow generate ds_{add|min|max}[_rtn]_f32 instructions
needed for OpenCL float atomics in LDS

Reviewed by: arsenm

Differential Revision: https://reviews.llvm.org/D37985

llvm-svn: 322656
2018-01-17 14:05:05 +00:00
Dmitry Preobrazhensky 6b65f7c380 [AMDGPU][MC][GFX9] Enable inline constants for SDWA operands
See bug 35771: https://bugs.llvm.org/show_bug.cgi?id=35771

Differential Revision: https://reviews.llvm.org/D42058

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 322655
2018-01-17 14:00:48 +00:00
Diana Picus 65ed364fac [ARM GlobalISel] Legalize G_FPEXT and G_FPTRUNC
Mark G_FPEXT and G_FPTRUNC as legal or libcall, depending on hardware
support, but only for conversions between float and double.

Also add the necessary boilerplate so that the LegalizerHelper can
introduce the required libcalls. This also works only for float and
double, but isn't too difficult to extend when the need arises.

llvm-svn: 322651
2018-01-17 13:34:10 +00:00
Ivan A. Kosarev 4d0ff0c74d [Transforms] Support making mutable versions of new-format TBAA access tags
Differential Revision: https://reviews.llvm.org/D41565

llvm-svn: 322650
2018-01-17 13:29:54 +00:00
Benjamin Kramer 8d073a2c2d [X86] Don't mutate shuffle arguments after early-out for AVX512
The match* functions have the annoying behavior of modifying its inputs.
Save and restore the inputs, just in case the early out for AVX512 is
hit. This is still not great and its only a matter of time this kind of
bug happens again, but I couldn't come up with a better pattern without
rewriting significant chunks of this code. Fixes PR35977.

llvm-svn: 322644
2018-01-17 13:01:06 +00:00
Benjamin Kramer 05dc3527de [X86] Constify DebugLoc parameters. No functionality change.
llvm-svn: 322643
2018-01-17 13:00:58 +00:00
Hiroshi Inoue 8f976ba0bf [NFC] fix trivial typos in comments
"the the" -> "the"

llvm-svn: 322636
2018-01-17 12:29:38 +00:00
Pavel Labath 67530e478b Don't emit apple accelerator tables on non-darwin targets
Summary:
Currently -glldb turns on emission of apple tables on all targets, but
lldb is only really capable of consuming them on darwin. Furthermore,
making lldb consume these tables is not straight-forward because of the
differences in how the debug info is distributed on darwin vs. elf
targets.

The darwin debug model assumes that the debug info (along with
accelerator tables) will either remain in the .o files or it will be
linked into a dsym bundle by a linker that knows how to merge these
tables. In the elf world, all present linkers will simply concatenate
these accelerator tables into the shared object. Since the tables are
not self-terminating, this renders the tables unusable, as the debugger
cannot pry the individual tables apart anymore.

It might theoretically be possible to make the tables work with split
dwarf, as that is somewhat similar to the apple .o model, but
unfortunately right now the combination of -glldb and -gsplit-dwarf
produces broken object files.

Until these issues are resolved there is no point in emitting the apple
tables for these targets. At best, it wastes space; at worst, it breaks
compilation and prevents the user from getting other benefits of -glldb.

Reviewers: probinson, aprantl, dblaikie

Subscribers: emaste, dim, llvm-commits, JDevlieghere

Differential Revision: https://reviews.llvm.org/D41986

llvm-svn: 322633
2018-01-17 11:52:13 +00:00
Pavel Labath 7da24de5c0 Rewrite debugger tuning test case to not depend on apple sections
Summary:
In a follow-up commit I'll change the rules for emission of accelerator
tables, which means we won't be able to use them as a litmus test for
the debugger tuning options. Instead of sections, I base the test on the
presence/absence of some debug info attributes and opcodes:
LLDB - prefers DW_OP_form_tls_address and uses DW_AT_APPLE_optimized
GDB - prefers DW_OP_GNU_push_tls_address and does not use the optimized
  attribute
SCE - prefers DW_OP_form_tls_address and does not use the optimized
  attribute

Reviewers: probinson, aprantl, dblaikie

Subscribers: JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D41985

llvm-svn: 322630
2018-01-17 11:11:53 +00:00
Javed Absar 0b05f327d6 [SCEV] fix typo
llvm-svn: 322629
2018-01-17 11:03:06 +00:00
Simon Pilgrim 1bea16f5d2 [X86][AVX] Add extra 'interleaved+lanepermute' shuffle test
Possible missed opportunity to use 64-bit lane permute on AVX1 in lowerShuffleAsRepeatedMaskAndLanePermute

llvm-svn: 322628
2018-01-17 10:56:54 +00:00
George Rimar 2421b6fa5c [ThinLTO] - Remove code duplication. NFC.
Refactors 3 copies of isExpected.
Splitted from D42107.

llvm-svn: 322627
2018-01-17 10:33:05 +00:00
Andrew V. Tischenko f7706994a6 Allow usage of X86-prefixes as separate instrs.
Differential Revision: https://reviews.llvm.org/D42102

llvm-svn: 322623
2018-01-17 10:12:06 +00:00
Sean Eveson 2ae6037dd1 [MC] Fix -stack-size-section on ARM
Change symbol values in the stack_size section from being 8 bytes, to being a target dependent size.

Differential Revision: https://reviews.llvm.org/D42108

llvm-svn: 322619
2018-01-17 09:01:29 +00:00
Craig Topper 77ba1e7c08 [X86] In LowerBUILD_VECTOR, rename ExtVT to EltVT so it makes sense.
llvm-svn: 322616
2018-01-17 03:58:21 +00:00
Craig Topper de1d28e053 [X86] Remove duplicate lines from scheduler models. NFC
llvm-svn: 322615
2018-01-17 03:50:21 +00:00
Aaron Smith daa503bb8f [pdbutil] Replace 0 byte PDB input with correct version to fix failing unit test
llvm-svn: 322614
2018-01-17 03:48:07 +00:00
George Burgess IV 41e646d8ea [Support] Return an enum instead of an unsigned; NFC.
We seem to be (logically) returning ArchExtKinds here in all cases, so
the return type should reflect that.

The static_cast is necessary because `A.ID` is actually an `unsigned`,
presumably since we use `decltype(A)` to represent extended attributes
for both ARM and AArch64, which use distinct `ArchExtKinds`.

We can't trivially make the same change for ARM, because one of the
values it returns is the bitwise-or of two `ARM::ArchExtKind`s.

llvm-svn: 322613
2018-01-17 03:12:06 +00:00
Aaron Smith 620a7f765d Fix build error - 'default label in switch which covers all enumeration values'
llvm-svn: 322610
2018-01-17 01:49:01 +00:00
Aaron Smith 53a1a1616c Fix pretty printing the unspecified param of a variadic function
Summary:
 - Fix a bug in PrettyBuiltinDumper that returns "void" as the name for
  an unspecified builtin type. Since the unspecified param of a variadic
  function is considered a builtin of unspecified type in PDBs, we set
  "..." for its name.

  - Provide a method to determine if a PDBSymbolFunc is variadic in
  PrettyFunctionDumper since PDBSymbolFunc::getArgument() doesn't return the
  last unspecified-type param.

  - Add a pretty-func-dumper.test to test pretty dumping of variadic
  functions.

Reviewers: zturner, llvm-commits

Reviewed By: zturner

Differential Revision: https://reviews.llvm.org/D41801

llvm-svn: 322608
2018-01-17 01:22:03 +00:00
Evgeniy Stepanov c07e0bd533 [hwasan] Rename sized load/store callbacks to be consistent with ASan.
Summary: __hwasan_load is now __hwasan_loadN.

Reviewers: kcc

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D42138

llvm-svn: 322601
2018-01-16 23:15:08 +00:00
Simon Pilgrim a8e6b885bd [X86][BTVER2] Fix scheduling of VCMPSD/VCMPSS instructions
For some reason they don't have a trailing i like the packed equivalents.

llvm-svn: 322600
2018-01-16 22:15:41 +00:00
Florian Hahn c6c89bffdc [CallSiteSplitting] Pass list of (BB, Conditions) pairs to splitCallSite.
This removes some duplication from splitCallSite and makes it easier to
add additional code dealing with each predecessor. It also allows us to
split for more than 2 predecessors, although that is not enabled for
now.

Reviewers: junbuml, mcrosier, davidxl, davide

Reviewed By: junbuml

Differential Revision: https://reviews.llvm.org/D41858

llvm-svn: 322599
2018-01-16 22:13:15 +00:00
Simon Pilgrim 3c66e2c541 [X86][BTVER2] Use instrs instead of instregex for low match counts (PR35955)
llvm-svn: 322598
2018-01-16 22:08:43 +00:00
Simon Pilgrim e9a2832f32 [X86][BTVER2] Use instrs instead of instregex for single use matches (PR35955)
llvm-svn: 322597
2018-01-16 21:44:48 +00:00
Rui Ueyama af4ddd5a6e Specify inline for isWhitespace in CommandLine.cpp
Patch by Takuto Ikuta.

In chromium's component build, there are many directive sections and
commandline parsing takes much time.
This patch is for speed up of lld in RelWithDebInfo build by forcing
inline heavily called isWhitespace function.

10 times link perf stats of blink_core.dll changed like below.

master:
TotalSeconds: 9.8764878
TotalSeconds: 10.1455242
TotalSeconds: 10.075279
TotalSeconds: 10.3397347
TotalSeconds: 9.8361665
TotalSeconds: 9.9544441
TotalSeconds: 9.8960686
TotalSeconds: 9.8877865
TotalSeconds: 10.0551879
TotalSeconds: 10.0492254
Avg: 10.01159047

with this patch:
TotalSeconds: 8.8696762
TotalSeconds: 9.1021585
TotalSeconds: 9.0233893
TotalSeconds: 9.1886175
TotalSeconds: 9.156954
TotalSeconds: 9.0978564
TotalSeconds: 9.1316824
TotalSeconds: 8.8354606
TotalSeconds: 9.2549431
TotalSeconds: 9.4473085
Avg: 9.11080465

llvm-svn: 322595
2018-01-16 20:52:32 +00:00
Lang Hames 4a793c0667 [ExecutionEngine] Rename JITSymbol::isStrongDefinition to isStrong.
For symmetry with isWeak, isCommon.

llvm-svn: 322594
2018-01-16 20:39:51 +00:00
Guozhi Wei e6fb4e1f8a [PPC] Add a new register XER aliased to CARRY
When "xer" is specified as clobbered register in inline assembler, clang can accept it, but llvm simply ignore it when lowered to machine instructions. It may cause problems later in scheduler.

This patch adds a new register XER aliased to CARRY, and adds it to register class CARRYRC. Now PPCTargetLowering::getRegForInlineAsmConstraint can return correct register number for inline asm constraint "{xer}", and scheduler behave correctly.

Differential Revision: https://reviews.llvm.org/D41967

llvm-svn: 322591
2018-01-16 19:28:50 +00:00
Francis Visoiu Mistrih 54a9e7a400 [CodeGen] Skip some instructions that shouldn't affect shrink-wrapping
r320606 checked for MI.isMetaInstruction which skips all DBG_VALUEs.

This also skips IMPLICIT_DEFs and other instructions that may def / read
a register.

Differential Revision: https://reviews.llvm.org/D42119

llvm-svn: 322584
2018-01-16 18:55:26 +00:00
Volkan Keles f7f2568613 [GlobalISel][TableGen] Add support for SDNodeXForm
Summary:
This patch adds CustomRenderer which renders the matched
operands to the specified instruction.

Targets can enable the matching of SDNodeXForm by adding
a definition that inherits from GICustomOperandRenderer and
GISDNodeXFormEquiv as follows.

def gi_imm8 : GICustomOperandRenderer<"renderImm8”>,
                       GISDNodeXFormEquiv<imm8_xform>;

Custom renderer functions should be of the form:
void render(MachineInstrBuilder &MIB, const MachineInstr &I);

Reviewers: dsanders, ab, rovka

Reviewed By: dsanders

Subscribers: kristof.beyls, javed.absar, llvm-commits, mgrang, qcolombet

Differential Revision: https://reviews.llvm.org/D42012

llvm-svn: 322582
2018-01-16 18:44:05 +00:00
Alexey Bataev 6977dbcc7b [SLP] Fix for PR32164: Improve vectorization of reverse order of extract operations.
Summary: Sometimes vectorization of insertelement instructions with extractelement operands may produce an extra shuffle operation, if these operands are in the reverse order. Patch tries to improve this situation by the reordering of the operands to remove this extra shuffle operation.

Reviewers: mkuper, hfinkel, RKSimon, spatel

Subscribers: mzolotukhin, llvm-commits

Differential Revision: https://reviews.llvm.org/D33954

llvm-svn: 322579
2018-01-16 18:17:01 +00:00
Simon Pilgrim 3e0aafbfcc [X86][MMX] Accept UNDEF upper bits for MOVD GR32->MMX
llvm-svn: 322574
2018-01-16 17:01:31 +00:00
Petar Jovanovic 76d619b509 [LiveDebugValues] update kill-after-spill test with target triple
Set target triple to "x86_64-unknown-linux-gnu".

llvm-svn: 322568
2018-01-16 15:57:03 +00:00
Petar Jovanovic 0b464e4f0e [LiveDebugValues] recognize spilled reg killed in instruction after spill
Current condition for spill instruction recognition in LiveDebugValues does
not recognize case when register is spilled and killed in next instruction.

Patch by Nikola Prica.

Differential Revision: https://reviews.llvm.org/D41226

llvm-svn: 322554
2018-01-16 14:46:05 +00:00
Simon Pilgrim 85e6139633 [X86][MMX] Improve MMX constant generation
Extend the MMX zero code to take any constant with zero'd upper 32-bits

llvm-svn: 322553
2018-01-16 14:21:28 +00:00
Hiroshi Inoue 760c0c9ed3 [NFC] fix trivial typos in documents
"the the" -> "the"

llvm-svn: 322552
2018-01-16 13:19:48 +00:00
Gadi Haber 76ce3d9e8d [X86][I86,I186,I286,I386,I486,PPRO, MMX]: Adding full coverage of MC encoding for the I86, I186, I286, I386, I486, PPRO and MMX isa sets.<NFC>
NFC.
 Adding MC regressions tests to cover the I86, I186, I286, I386, I486, PPRO and MMX isa sets.
 This patch is part of a larger task to cover MC encoding of all X86 ISA Sets.
 Started in revision: https://reviews.llvm.org/D39952

Reviewers: zvi, RKSimon, AndreiGrischenko, craig.topper
Differential Revision: https://reviews.llvm.org/D40879

Change-Id: I231a35861611bfd3d23c74cc59507373f021a629
llvm-svn: 322544
2018-01-16 11:33:45 +00:00
Jonas Devlieghere 6f24c8778c [DebugInfo] Unify dumping of address ranges
Summary:
This patch unifies the printing of address ranges as [0x0, 0x1).

rdar://34822059

Reviewers: aprantl, dblaikie

Subscribers: mehdi_amini, llvm-commits

Differential Revision: https://reviews.llvm.org/D42056

llvm-svn: 322543
2018-01-16 11:17:57 +00:00
Francis Visoiu Mistrih 5eaddb3f68 [CodeGen] Remove special case of printing subRegIdx from MachineInstr::print
Support in MachineOperand has been added in r320209. No need to special
case this anymore.

llvm-svn: 322542
2018-01-16 10:53:14 +00:00
Francis Visoiu Mistrih ecd0b83312 [CodeGen][NFC] Correct case for printSubRegIdx
llvm-svn: 322541
2018-01-16 10:53:11 +00:00
Clement Courbet 639a398098 Add a value_type to ArrayRef.
Summary: Not sure this needs a review or not. Erring on the safe side.

Reviewers: dblaikie

Differential Revision: https://reviews.llvm.org/D41666

llvm-svn: 322538
2018-01-16 09:11:20 +00:00
Gadi Haber a6bc5f954c [X86][XSAVE]: Adding full coverage of MC encoding for the XSAVE isa sets.<NFC>
NFC.
 Adding MC regressions tests to cover the XSAVE ISA sets.
 This patch is part of a larger task to cover MC encoding of all X86 ISA Sets started in revision: https://reviews.llvm.org/D39952

Reviewers: zvi, RKSimon, AndreiGrischenko, craig.topper
Differential Revision: https://reviews.llvm.org/D41282

Change-Id: I325bf8f421f78c80179a04fc39033366759cbe45
llvm-svn: 322537
2018-01-16 08:50:29 +00:00
George Rimar 83e63d96a9 [FileCheck] - Fix possible buffer out of bounds access when parsing --check-prefix.
FileCheck tool crashes when trying to parse --check-prefix argument if there is no any
data after it.

For example test like following would crash if there are no symbols and no EOL mark after `boom`:

# REQUIRES: x86
# RUN: <skipped few lines>
# RUN: llvm-readobj -t %t | FileCheck %s --check-prefix=boom

Patch fixes the issue.

Differential revision: https://reviews.llvm.org/D42057

llvm-svn: 322536
2018-01-16 08:09:24 +00:00
Yonghong Song 035dd256d5 [BPF] Mark pseudo insn patterns as isCodeGenOnly
These pseudos are not supposed to be visible to user.

This patch reduced the auto-generated instruction matcher. For example,
the following words are removed from keyword list of LLVM BPF assembler.

-  MCK__35_, // '#'
-  MCK__COLON_, // ':'
-  MCK__63_, // '?'
-  MCK_ADJCALLSTACKDOWN, // 'ADJCALLSTACKDOWN'
-  MCK_ADJCALLSTACKUP, // 'ADJCALLSTACKUP'
-  MCK_PSEUDO, // 'PSEUDO'
-  MCK_Select, // 'Select'

Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Acked-by: Yonghong Song <yhs@fb.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
llvm-svn: 322535
2018-01-16 07:27:20 +00:00
Yonghong Song b42c7c7863 [BPF] Teach DAG2DAG AND elimination about load intrinsics
As commented on the existing code:

  // The Reg operand should be a virtual register, which is defined
  // outside the current basic block. DAG combiner has done a pretty
  // good job in removing truncating inside a single basic block.

However, when the Reg operand comes from bpf_load_[byte | half | word]
intrinsics, the generic optimizer doesn't understand their results are
zero extended, so these single basic block elimination opportunities were
missed.

Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Acked-by: Yonghong Song <yhs@fb.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
llvm-svn: 322534
2018-01-16 07:27:19 +00:00
Hiroshi Inoue 99a8faa615 [SROA] fix assetion failure
This patch fixes the assertion failure in SROA reported in PR35657.
PR35657 reports the assertion failure due to r319522 (splitting for non-whole-alloca slices), but this problem can happen even without r319522.

The problem exists in a check for reusing an existing alloca when rewriting partitions. As the original comment said, we can reuse the existing alloca if the new alloca has the same type and offset with the existing one. But the code checks only type of the alloca and then check the offset using an assert.
In a corner case with out-of-bounds access (e.g. @PR35657 function added in unit test), it is possible that the two allocas have the same type but different offsets.

This patch makes the check of the offset in the if condition, and re-enables the splitting for non-whole-alloca slices.

Differential Revision: https://reviews.llvm.org/D41981

llvm-svn: 322533
2018-01-16 06:23:05 +00:00
Craig Topper 7a0c601f95 [X86] Revisit the fix I made years ago to make 'xchgl %eax, %eax' not encode using the 0x90 encoding in 64-bit mode.
Prior to this we had a separate instruction and register class that excluded eax to prevent matching the instruction that would encode with 0x90.

This patch changes this to just use an InstAlias to force xchgl %eax, %eax to use XCHG32rr instruction in 64-bit mode. This gets rid of the separate instruction and register class.

llvm-svn: 322532
2018-01-16 06:07:16 +00:00
Craig Topper daa385f480 [X86] Make 'xchgq %rax, %rax' an alias for the 0x90 nop encoding to match gas.
Previously we encoded it as 0x48 0x90.

llvm-svn: 322531
2018-01-16 06:07:14 +00:00
Simon Pilgrim e5dad1365c Avoid Wparentheses warning.
llvm-svn: 322526
2018-01-15 22:40:06 +00:00
Simon Pilgrim 85bd9141ca [X86][MMX] Add support for MMX zero vector creation
As mentioned on PR35869, (and came up recently on D41517) we don't create a MMX zero register via the PXOR but instead perform a spill to stack from a XMM zero register.

This patch adds support for direct MMX zero vector creation and should make it easier to add better constant vector creation in the future as well.

Differential Revision: https://reviews.llvm.org/D41908

llvm-svn: 322525
2018-01-15 22:32:40 +00:00
Simon Pilgrim 940eae3cc1 [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873)
Add support for custom execution domain fixing and implement support for BLENDPD/BLENDPS/PBLENDD/PBLENDW.

Differential Revision: https://reviews.llvm.org/D42042

llvm-svn: 322524
2018-01-15 22:18:45 +00:00
Sanjay Patel 30265d0a47 [x86] add tests to show missed constant shrinking (PR35907); NFC
llvm-svn: 322523
2018-01-15 21:57:41 +00:00
Sanjay Patel fc74f71400 [x86] regenerate test checks; NFC
llvm-svn: 322522
2018-01-15 21:32:39 +00:00
Sanjay Patel b885f04695 [x86] regenerate test checks; NFC
llvm-svn: 322521
2018-01-15 21:28:52 +00:00
Brian Gesiak 17dfa193a5 [docs] Only LLVM IR bitstreams begin with 'BC'
Summary:
The LLVM Bitcode File Format documentation states that all bitstreams
begin with the magic number 'BC', and that generic bitstream analyzer
tools may check for this number in order to determine whether the
stream is a bitstream.

However, in practice:

* Only LLVM IR bitcode begins with 'BC'. Other bitstreams -- Clang
  AST files and precompiled headers, Clang serialized diagnostics,
  Swift modules -- do not start with 'BC'. A tool that actually checked
  for 'BC' would only be able to recognize LLVM IR.
* The `llvm-bcanalyzer`, arguably the most used generic bitstream
  analyzer tool, does not check for a magic number 'BC' (except to
  determine whether the file is LLVM IR).

Update the bitcode format documentation to make it clear that not all
bitstreams begin with 'BC', and that tools should not rely on that
particular magic number value.

Test Plan:
Build the `docs-llvm-html` target and confirm the changes render in
a Safari web browser.

Reviewers: harlanhaskins, eugenis, mehdi_amini, pcc, angerman

Reviewed By: angerman

Subscribers: angerman, llvm-commits

Differential Revision: https://reviews.llvm.org/D42002

llvm-svn: 322520
2018-01-15 21:23:32 +00:00
Sanjay Patel 0d0cec879b [x86] regenerate test checks; NFC
llvm-svn: 322519
2018-01-15 21:22:46 +00:00
Craig Topper 1393ccf949 [X86] Use MVT::getVectorVT instead of EVT::getVectorVT when splitting 256/512 bit build_vectors. NFC
We must be creating a legal type here which means it can be an MVT.

llvm-svn: 322512
2018-01-15 20:33:53 +00:00
Craig Topper aacc622564 [X86] Generalize some code in LowerBUILD_VECTOR. NFC
llvm-svn: 322511
2018-01-15 20:33:52 +00:00
Craig Topper 4f7fadd029 [X86] Remove unnecessary if statement from LowerBUILD_VECTOR. NFCI
We were checking for 128, 256, or 512 bit vectors, but those are the only types that can get here.

llvm-svn: 322510
2018-01-15 20:33:50 +00:00
Dan Gohman 7aa1fcdf3e [WebAssembly] Update README.txt.
Describe more of the current status, mention Rust as another easy
way to use this backend, and add more documentation links.

llvm-svn: 322508
2018-01-15 20:08:14 +00:00
Stanislav Mekhanoshin 62875fcd6c [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32
Differential Revision: https://reviews.llvm.org/D41617

llvm-svn: 322500
2018-01-15 18:49:15 +00:00
Krzysztof Parzyszek 7fb738ab71 [Hexagon] Implement signed and unsigned multiply-high for vectors
llvm-svn: 322499
2018-01-15 18:43:55 +00:00
Krzysztof Parzyszek b8f2a1e7b7 [Hexagon] Rewrite LowerVECTOR_SHUFFLE for 32-/64-bit vectors
The old implementation was not always correct. The new one recognizes
more shuffles that match specific instructions.

llvm-svn: 322498
2018-01-15 18:33:33 +00:00
Stanislav Mekhanoshin f630047ef6 [AMDGPU] Copy impdefs from pseudo to real instructions
In some cases we do not copy implicit defs from pseudo to real
VOP instructions. It has no visible impact at the moment thus no
tests are affected or added.

Differential Revision: https://reviews.llvm.org/D41783

llvm-svn: 322496
2018-01-15 17:55:35 +00:00
Simon Pilgrim 79add5f155 [X86] Fix typos in WriteVMOVNTDQSt and WriteVMOVNTPYSt pattern names. NFCI.
llvm-svn: 322495
2018-01-15 17:55:21 +00:00
Jan Korous 8a3735c006 [docs] Fix mention of GCC frontend
llvm-svn: 322491
2018-01-15 17:11:22 +00:00
Dan Gohman 0917c9e413 [WebAssembly] Make WasmObjectWriter's destructor public; NFC
This fixes the FIXME introduced in r315327.

llvm-svn: 322490
2018-01-15 17:06:23 +00:00
Jonas Paulsson 776a81a483 [SystemZ] Check for legality before doing LOAD AND TEST transformations.
Since a load and test instruction treat its operands as signed, it can only
replace a logical compare for EQ/NE uses.

Review: Ulrich Weigand
https://bugs.llvm.org/show_bug.cgi?id=35662

llvm-svn: 322488
2018-01-15 15:41:26 +00:00
Sam McCall 264a683ec8 Allow function_ref(nullptr) like std::function, since it's nullable already
llvm-svn: 322487
2018-01-15 14:43:04 +00:00
Clement Courbet da1fad3ec6 [X86] Add missing predicates for VRNDSCALES{D,S}{m,r}
Summary: This is similar to https://reviews.llvm.org/D41983.

Reviewers: gchatelet

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D42069

llvm-svn: 322486
2018-01-15 14:24:07 +00:00
Andrew V. Tischenko e58c0c96b2 Update BTVER2 sched numbers for some AVX instructions (xmm version).
Differential Revision: https://reviews.llvm.org/D40067

llvm-svn: 322485
2018-01-15 14:21:11 +00:00
Clement Courbet 36c7be664f [X86]Add missing predicates for VMOVDQUYrm,VMOVDQUYmr.
Summary:
Due to missing parentheses.

This is similar to https://reviews.llvm.org/D41983.

Reviewers: gchatelet

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D42062

llvm-svn: 322483
2018-01-15 13:37:05 +00:00
Sander de Smalen 5aa809db79 [AArch64][AsmParser] Cleanup isSImm7s4, isSImm7s8, (etc) functions.
Reviewers: fhahn, rengolin, t.p.northover, echristo, olista01, samparker

Reviewed By: fhahn, samparker

Subscribers: samparker, aemerson, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D41899

llvm-svn: 322481
2018-01-15 12:47:17 +00:00
Clement Courbet 41a13740c5 [X86] Fix missing predicates HasAVX512 Predicates in avx512_sqrt_scalar.
Summary:
For example, VSQRTSDZr and VSQRTSSZr were missing the predicate.
Also fix braces indentation and braces for consistency.

Reviewers: craig.topper, RKSimon

Suscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41983

llvm-svn: 322478
2018-01-15 12:05:33 +00:00
Pavel Labath e04f8ab3fb [Support] Remove MemoryBuffer::getNewMemBuffer
all callers have been switched the the Writable version (which does not
require const_casting to be useful).

llvm-svn: 322475
2018-01-15 11:03:30 +00:00
Benjamin Kramer 736a343e97 Revert "[DAG] Elide overlapping stores"
This reverts commit r322085. Internal PPC testing is still showing the
same symptoms as when this patch landed the last time.

llvm-svn: 322474
2018-01-15 10:57:24 +00:00
Andrei Elovikov 7457aa0bce [LV] Don't call recordVectorLoopValueForInductionCast for newly-created IV from a trunc.
Summary:
This method is supposed to be called for IVs that have casts in their use-def
chains that are completely ignored after vectorization under PSE. However, for
truncates of such IVs the same InductionDescriptor is used during
creation/widening of both original IV based on PHINode and new IV based on
TruncInst.

This leads to unintended second call to recordVectorLoopValueForInductionCast
with a VectorLoopVal set to the newly created IV for a trunc and causes an
assert due to attempt to store new information for already existing entry in the
map. This is wrong and should not be done.

Fixes PR35773.

Reviewers: dorit, Ayal, mssimpso

Reviewed By: dorit

Subscribers: RKSimon, dim, dcaballe, hsaito, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D41913

llvm-svn: 322473
2018-01-15 10:56:07 +00:00
Gadi Haber fb64e018eb [X86][AVX512F_512]: Adding full coverage of MC encoding for the AVX512F 512 bits isa sets.<NFC>
NFC.
 Adding MC regressions tests to cover the AVX512F_512 isa sets both 32 and 64 bit.
 This patch is part of a larger task to cover MC encoding of all X86 ISA Sets.
 started in revision: https://reviews.llvm.org/D39952

Reviewers: zvi, craig.topper, RKSimon, AndreiGrischenko
Differential Revision: https://reviews.llvm.org/D41172

Change-Id: I46aa33dd967d63d33f67d1988ad42d8df2081e39
llvm-svn: 322471
2018-01-15 09:39:08 +00:00
Mikael Holmen 4653b1a4f1 [GlobalsAA] Don't let dbg intrinsics affect analysis result
Summary:
This fixes PR35899.

Debug info intrinsics shouldn't affect code generation so ignore them
in GlobalsAA.

Reviewers: hfinkel, aprantl

Reviewed By: aprantl

Subscribers: aprantl, llvm-commits

Differential Revision: https://reviews.llvm.org/D41984

llvm-svn: 322470
2018-01-15 07:05:51 +00:00
Max Kazantsev d0fe502385 [NFC] Fix comment to adjust to reality
llvm-svn: 322468
2018-01-15 05:44:43 +00:00
Davide Italiano 7ccd4619e4 [BasicAA] Stop crashing when dealing with pointers > 64 bits.
An alternative (and probably better) fix would be that of
making `Scale` an APInt, and there's a patch floating around
to do this. As we're still discussing it, at least stop crashing
in the meanwhile (added bonus, we now have a regression test for
this situation).

Fixes PR35843.

Thanks to Eli for suggesting the fix and Simon for reporting and
reducing the bug.

llvm-svn: 322467
2018-01-15 01:40:18 +00:00
Amara Emerson 5eccf52e12 [GlobalISel][Legalizer] Convert some typedefs to using. NFC.
llvm-svn: 322466
2018-01-15 00:44:20 +00:00
Simon Pilgrim 700552dd78 [X86][SSE] Tag PR21137 test case
The test was added ages ago, but we didn't comment where it came from.

llvm-svn: 322465
2018-01-14 21:59:43 +00:00
Craig Topper 6c2dee0c8e [X86] Add test cases for D41794.
llvm-svn: 322464
2018-01-14 20:53:49 +00:00
Simon Pilgrim 1b6440ff22 [X86][SSE] Add PR22391 test case
llvm-svn: 322463
2018-01-14 19:57:50 +00:00
Craig Topper 7197a452fc [X86] Autoupgrade kunpck intrinsics using vector operations instead of scalar operations
Summary: This patch changes the kunpck intrinsic autoupgrade to use vXi1 shufflevector operations to perform vector extracts and concats. This more closely matches the definition of the kunpck instructions. Currently we rely on a DAG combine to turn the scalar shift/and/or code into a concat vectors operation. By doing it in the IR we get this for free.

Reviewers: spatel, RKSimon, zvi, jina.nahias

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D42018

llvm-svn: 322462
2018-01-14 19:24:10 +00:00
Simon Pilgrim 7c3088e5c0 [X86] Regenerate fp128 test
llvm-svn: 322460
2018-01-14 19:07:41 +00:00
Simon Pilgrim 9904fe77a0 [X86][SSE] Support combining MOVLHPS undef inputs
llvm-svn: 322459
2018-01-14 18:50:34 +00:00
Simon Pilgrim 73cebe807b [X86][SSE] Add v2f64 3u shuffle test
Shows a missed opportunity to remove a unnecessary move compared to 31 shuffle mask.

llvm-svn: 322458
2018-01-14 18:38:21 +00:00
Sanjay Patel 527bf920c6 [x86] auto-generate complete checks; NFC
llvm-svn: 322457
2018-01-14 17:47:40 +00:00
Sanjay Patel 9568f42a7a [InstSimplify] fix code comments; NFC
llvm-svn: 322456
2018-01-14 15:58:18 +00:00
Craig Topper b2868233b7 [X86] Use ISD::TRUNCATE instead of X86ISD::VTRUNC when input and output types have the same number of elements.
llvm-svn: 322455
2018-01-14 08:11:36 +00:00
Craig Topper 57d58051bb [X86] Add X86ISD::VTRUNC to computeKnownBitsForTargetNode.
We have to take special care to avoid the cases where the result of the truncate would be padded with zero elements.

Ideally we'd just use ISD::TRUNCATE for these cases instead.

llvm-svn: 322454
2018-01-14 08:11:33 +00:00
Craig Topper e9fc0cd920 [X86] Improve legalization of vXi16/vXi8 selects.
Extend vXi1 conditions of vXi8/vXi16 selects even before type legalization gets a chance to split wide vectors. Previously we would only extend 128 and 256 bit vectors. But if we start with a 512 bit vector or wider that needs to be split we wouldn't extend until after the split had taken place. By extending early we improve the results of type legalization.

Don't widen condition of 128/256 bit vXi16/vXi8 selects when we have BWI but not VLX. We can still use a mask register by widening the select to 512-bits instead. This is similar to what we do for compares already.

llvm-svn: 322450
2018-01-14 02:05:51 +00:00
Craig Topper 7a3b10184b [X86] Add an avx512bw command line to the avx512-vec-cmp.ll test. Add some additional test cases.
Additional test cases cover selects with i16/i8 conditions that are only 128/256-bits wide, but the compares are 512-bits wide and can only produce k-registers. We should be able to artificially widen the selects to avoid moving the k-register to an xmm/ymm register.

llvm-svn: 322449
2018-01-14 02:05:49 +00:00
Zvi Rackover 652f9a1896 X86: Add pattern matching for PMADDWD
In addition to the existing match as part of a loop-reduction, add a
straightforward pattern match for DAG-contained patterns.

Reviewers: RKSimon, craig.topper

Subscribers: llvm-commits

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D41811

llvm-svn: 322446
2018-01-13 17:42:19 +00:00
Simon Pilgrim f408745306 [X86] Regenerate double shift tests
llvm-svn: 322444
2018-01-13 16:55:28 +00:00
Sanjay Patel 4158eff0f8 [InstSimplify] fold implied null ptr check (PR35790)
This extends rL322327 to handle the pointer cast and should solve:
https://bugs.llvm.org/show_bug.cgi?id=35790

Name: or_eq_zero
  %isnull = icmp eq i64* %p, null
  %x = ptrtoint i64* %p to i64
  %somebits = and i64 %x, %y
  %somebits_are_zero = icmp eq i64 %somebits, 0
  %or = or i1 %somebits_are_zero, %isnull
  =>
  %or = %somebits_are_zero

Name: and_ne_zero
  %isnotnull = icmp ne i64* %p, null
  %x = ptrtoint i64* %p to i64
  %somebits = and i64 %x, %y
  %somebits_are_not_zero = icmp ne i64 %somebits, 0
  %and = and i1 %somebits_are_not_zero, %isnotnull
  =>
  %and = %somebits_are_not_zero

https://rise4fun.com/Alive/CQ3

llvm-svn: 322439
2018-01-13 15:44:44 +00:00
Simon Pilgrim 20acf939ef [X86][MMX] Add test for MMX zero folding
As discussed in D41908

llvm-svn: 322436
2018-01-13 12:29:06 +00:00
Zvi Rackover 63f1f322c9 X86 Tests: add more pamddwd cases. NFC
Improve coverage of D41811

llvm-svn: 322434
2018-01-13 08:21:29 +00:00
Craig Topper 6f109f8c6c [X86] Add DAG combine to promote vXi1 result of a vXi8/vXi16 setcc when we have AVX512 but not BWI.
This avoids having the result type stick around until lowering where we have to extend the setcc and insert a truncate. If we get the types converted early we can do more to optimize it.

llvm-svn: 322432
2018-01-13 06:24:46 +00:00
Paul Robinson b22d170caf XFAIL a test on Darwin, line-table stuck on DWARF 2
llvm-svn: 322430
2018-01-13 01:39:30 +00:00
Evgeniy Stepanov 080e0d40b9 [hwasan] An LLVM flag to disable stack tag randomization.
Summary: Necessary to achieve consistent test results.

Reviewers: kcc, alekseyshl

Subscribers: kubamracek, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D42023

llvm-svn: 322429
2018-01-13 01:32:15 +00:00
Jessica Paquette 757e120379 [MachineOutliner] Move hasAddressTaken check to MachineOutliner.cpp
*Mostly* NFC. Still updating the test though just for completeness.

This moves the hasAddressTaken check to MachineOutliner.cpp and replaces it
with a per-basic block test rather than a per-function test. The old test was
too conservative and was preventing functions in C programs from being
outlined even though they were safe to outline.

This was mostly a problem in C sources.

llvm-svn: 322425
2018-01-13 00:42:28 +00:00
Tim Renouf 75ced9d5b8 [AMDGPU] stop image_store being moved illegally
Summary:
A recent change
321556: AMDGPU: Remove mayLoad/hasSideEffects from MIMG stores
can allow the machine instruction scheduler to move an image store past
an image load using the same descriptor.

V2: Fixed by marking image ops as mayAlias and isAliased. This may be
overly conservative, and we may need to revisit.
V3: Reverted test change done on 321556.

Reviewers: arsenm, nhaehnle, dstuttard

Subscribers: llvm-commits, t-tye, yaxunl, wdng, kzhuravl

Differential Revision: https://reviews.llvm.org/D41969

llvm-svn: 322419
2018-01-12 22:57:24 +00:00
Sanjay Patel 6691e40980 [InstSimplify] add tests for implied ptr cmp with null (PR35790); NFC
llvm-svn: 322411
2018-01-12 22:16:26 +00:00
Rui Ueyama 6371180cd4 Allow unaligned access to ELF file data structures.
The ELF specification says that all ELF data structures are aligned to
their natural alignments both in memory and file. That means when we
access mmap'ed ELF files, we could assume that all data structures are
aligned properly.

However, in reality, we assume that the data structures are aligned only
to two bytes because .a files only guarantee that their member files are
aligned to two bytes in archive files. So the data access is already
unaligned.

This patch relaxes the alignment requirement even more, so that we
accept unaligned access to all ELF data structures.

This patch in particular makes lld bug-compatible with icc. Intel C
compiler doesn't seem to care about data alignment and generates unaligned
relocation sections (https://bugs.llvm.org/show_bug.cgi?id=35854).
I also saw another instance of compatibility issues with our internal tool
which creates unaligned section headers.

Because GNU linkers are not picky about alignment, looks like it is
not uncommon that ELF-generating tools create unaligned files.

There is a performance penalty with this patch on host machines on which
unaligned access is expensive. x86 and AArch64 are fine. ARMv6 is a
problem, but I don't think using ARMv6 machines as hosts is common, so I
believe it's not a real problem.

Differential Revision: https://reviews.llvm.org/D41978

llvm-svn: 322407
2018-01-12 22:09:19 +00:00
Zachary Turner 89d0889bf4 Update MSF File Documentation.
This adds some more detail about the PDB container format,
specifically surrounding the layout of the Free Page Map.

Patch by Colden Cullen
Differential Revision: https://reviews.llvm.org/D41825

llvm-svn: 322404
2018-01-12 21:42:39 +00:00
Daniel Neilson 2409d24201 [NFC] Change MemIntrinsicInst::setAlignment() to take an unsigned instead of a Constant
Summary:
 In preparation for https://reviews.llvm.org/D41675 this NFC changes this
prototype of MemIntrinsicInst::setAlignment() to accept an unsigned instead
of a Constant.

llvm-svn: 322403
2018-01-12 21:33:37 +00:00
Changpeng Fang 44dfa1de3b AMDGPU/SI: Add d16 support for buffer intrinsics.
Differential Revision:
  https://reviews.llvm.org/D38906

Reviewers:
  Matt and Brian.

llvm-svn: 322402
2018-01-12 21:12:19 +00:00
Brian M. Rzycki 9b7ae23256 [JumpThreading] Preservation of DT and LVI across the pass
Summary:
See D37528 for a previous (non-deferred) version of this
patch and its description.

Preserves dominance in a deferred manner using a new class
DeferredDominance. This reduces the performance impact of
updating the DominatorTree at every edge insertion and
deletion. A user may call DDT->flush() within JumpThreading
for an up-to-date DT. This patch currently has one flush()
at the end of runImpl() to ensure DT is preserved across
the pass.

LVI is also preserved to help subsequent passes such as
CorrelatedValuePropagation. LVI is simpler to maintain and
is done immediately (not deferred). The code to perform the
preversation was minimally altered and simply marked as
preserved for the PassManager to be informed.

This extends the analysis available to JumpThreading for
future enhancements such as threading across loop headers.

Reviewers: dberlin, kuhar, sebpop

Reviewed By: kuhar, sebpop

Subscribers: mgorny, dmgreen, kuba, rnk, rsmith, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D40146

llvm-svn: 322401
2018-01-12 21:06:48 +00:00
Paul Robinson 1879cb0b42 Try to fix more bots after r322391
llvm-svn: 322400
2018-01-12 20:54:45 +00:00
Florian Hahn 6a684b2593 Silence GCC 7 warning by using an enum class.
This silences the following GCC7 warning:

    lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp:142:30: warning:
    enumeral and non-enumeral type in conditional expression [-Wextra]
         return F != Colors.end() ? F->second : None;
                    ~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~

Reviewers: amharc, RKSimon, davide

Reviewed By: RKSimon, davide

Differential Revision: https://reviews.llvm.org/D41003

llvm-svn: 322398
2018-01-12 20:35:45 +00:00
Max Moroz 6242cac18e [llvm-cov] Skip unnecessary coverage computations for "export -summary-only".
Summary:
This speeds up export "summary-only" execution by an order of magnitude or two,
depending on number of threads used for prepareFileReports execution.

Also includes minor refactoring for splitting render of summary and detailed data
in two independent methods.

Reviewers: vsk, morehouse

Reviewed By: vsk

Subscribers: llvm-commits, kcc

Differential Revision: https://reviews.llvm.org/D42000

llvm-svn: 322397
2018-01-12 20:31:32 +00:00
Rui Ueyama fc63551082 Remove ELFDataTypeTypedefHelper class.
Differential Revision: https://reviews.llvm.org/D41973

llvm-svn: 322395
2018-01-12 19:59:43 +00:00
Paul Robinson d138088c2f Add toothpicks to test from r322391
llvm-svn: 322394
2018-01-12 19:58:35 +00:00
Evandro Menezes 2e05279399 [AArch64] Fix scheduling resources for post indexed loads and stores
Fix typos in the default scheduling resources when using the post indexed
addressing modes.

Differential revision: https://reviews.llvm.org/D40511

llvm-svn: 322392
2018-01-12 19:20:11 +00:00
Paul Robinson 612e89d74f [DWARFv5] CodeGen support for MD5 file checksums
Pass MD5 checksums through from IR to assembly/object files.
After this, getting Clang to compute the MD5 should be the last step
to supporting MD5 in the DWARF v5 line table header.

Differential Revision: https://reviews.llvm.org/D41926

llvm-svn: 322391
2018-01-12 19:17:50 +00:00
Sam Clegg 5e102eeee6 MC: Remove redundant `SetUsed` arguments in MCSymbol methods
We can probably take this a step further since the only
user of the isUsed flag is AsmParser it should probably
be doing this explicitly. For now this is a step in the
right direction though.

Differential Revision: https://reviews.llvm.org/D41971

llvm-svn: 322386
2018-01-12 18:05:40 +00:00
Simon Pilgrim edff13b9de [X86][SSE] Force blend domains on stack folding tests
llvm-svn: 322385
2018-01-12 18:05:29 +00:00
Simon Pilgrim b8bc537923 [X86][AVX] Regenerate element insertion tests
llvm-svn: 322384
2018-01-12 18:02:52 +00:00
Craig Topper cb09bd1227 [X86] Remove unused isel pattern for zero extend from v16i1/v8i1 to v16i32/v8i64.
We have custom lowering on vzext that produces a vselect and a build vector. So zext never gets to isel.

llvm-svn: 322381
2018-01-12 17:34:09 +00:00
Rafael Espindola 3b9843f0ff Allow dso_local on ifunc.
It was never fully disallowed. We were rejecting it in the asm parser,
but not in the verifier.

Currently TargetMachine::shouldAssumeDSOLocal returns true for hidden
ifuncs. I considered changing it and moving the check from the asm
parser to the verifier.

The reason for deciding to allow it instead is that all linkers handle
a direct reference just fine. They use the plt address as the address
of the function. In fact doing that means that clang doesn't have the
same bug as gcc: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83782.

This patch then removes the check from the asm parser and updates the
bitcode reader and writer.

llvm-svn: 322378
2018-01-12 17:03:43 +00:00
Ben Hamilton e0d2f7678d [docs] Tweak update to Phabricator docs about setting repository for diffs uploaded via web
Summary:
In D41919, I missed that there was a *second* step when uploading
diffs via web where the repository should be specified.

Reviewers: asb, probinson

Reviewed By: asb

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41956

llvm-svn: 322375
2018-01-12 15:44:35 +00:00
Ben Hamilton e7c8361974 [llvm] Set up .arcconfig to point to Diffusion L repository
Summary:
Thanks to probinson for noticing this in his review of D41956.

Now that we have repository callsigns set in all the other
LLVM/Clang projects' .arcconfig files, we can set the top-level
LLVM .arcconfig repository callsign to "L".

This will correctly Cc: llvm-commits@ on all review requests
sent out from the LLVM repo directory, using Herald rule H270.

Reviewers: klimek, sammccall

Reviewed By: sammccall

Subscribers: llvm-commits, probinson, asb

Differential Revision: https://reviews.llvm.org/D41964

llvm-svn: 322374
2018-01-12 15:37:41 +00:00
Benjamin Kramer 309124e0b1 [PowerPC] Don't miscompile rotate+mask into an ANDIo if it can't recreate the immediate
I'm not even sure if this transform is ever worth it, but this at least
stops the bleeding.

llvm-svn: 322373
2018-01-12 15:03:24 +00:00
Nemanja Ivanovic ebb23078e9 [PowerPC] Zero-extend the compare operand for ATOMIC_CMP_SWAP
Part of the fix for https://bugs.llvm.org/show_bug.cgi?id=35812.
This patch ensures that the compare operand for the atomic compare and swap
is properly zero-extended to 32 bits if applicable.
A follow-up commit will fix the extension for the SETCC node generated when
expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS. That will complete the bug fix.

Differential Revision: https://reviews.llvm.org/D41856

llvm-svn: 322372
2018-01-12 14:58:41 +00:00
Stefan Pintilie 70bfe66111 Revert "[PowerPC] Manually schedule the prologue and epilogue"
This reverts commit r322124 since some tests were broken by that patch.
Will recommmit once the patch is fixed.

llvm-svn: 322369
2018-01-12 13:12:49 +00:00
Diana Picus cf044647c4 [ARM GlobalISel] Add inst selector tests for G_FMA
We don't yet match all the patterns involving G_FMA. Add tests for some
of the ones that we do match.

llvm-svn: 322368
2018-01-12 12:44:36 +00:00
Diana Picus 2dc5405693 [ARM GlobalISel] Map G_FMA to FPR
llvm-svn: 322367
2018-01-12 12:06:01 +00:00
Diana Picus e74243d473 [ARM GlobalISel] Legalize G_FMA
For hard float with VFP4, it is legal. Otherwise, we use libcalls.

This needs a bit of support in the LegalizerHelper for soft float
because we didn't handle G_FMA libcalls yet. The support is trivial, as
the only difference between G_FMA and other libcalls that we already
handle is that it has 3 input operands rather than just 2.

llvm-svn: 322366
2018-01-12 11:30:45 +00:00
Max Kazantsev ef0576000c [IRCE][NFC] Make range check's End a non-null SCEV
Currently, IRC contains `Begin` and `Step` as SCEVs and `End` as value.
Aside from that, `End` can also be `nullptr` which can be later conditionally
converted into a non-null SCEV.

To make this logic more transparent, this patch makes `End` a SCEV and
calculates it early, so that it is never a null.

Differential Revision: https://reviews.llvm.org/D39590

llvm-svn: 322364
2018-01-12 10:00:26 +00:00
Andre Vieira 5627c218e1 [ARM] Add codegen for SMMULR, SMMLAR and SMMLSR
This patch teaches the Arm back-end to generate the SMMULR, SMMLAR and SMMLSR
instructions from equivalent IR patterns.

Differential Revision: https://reviews.llvm.org/D41775

llvm-svn: 322361
2018-01-12 09:24:41 +00:00
Andre Vieira 26b9de9ebb [ARM] Fix erroneous availability of SMMLS for Armv7-M
Differential Revision: https://reviews.llvm.org/D41855

llvm-svn: 322360
2018-01-12 09:21:09 +00:00
Serguei Katkov 76a1de3cd5 [CGP] Re-enable Select in complex addressing mode
Re-enable Select after a couple of fixes.

Differential Revision: https://reviews.llvm.org/D40634

llvm-svn: 322358
2018-01-12 08:33:34 +00:00
Serguei Katkov a757d65cec [LoopDeletion] Handle users in unreachable block
This is a fix for PR35884.

When we want to delete dead loop we must clean uses in unreachable blocks
otherwise we'll get an assert during deletion of instructions from the loop.

Reviewers: anna, davide
Reviewed By: anna
Subscribers: llvm-commits, lebedev.ri
Differential Revision: https://reviews.llvm.org/D41943

llvm-svn: 322357
2018-01-12 07:24:43 +00:00
Craig Topper 72001f4647 [X86] Don't allow lods/stos/scas/cmps/movs to be parsed without a suffix and only memory operand in at&t syntax.
Without a register with a size being mentioned the instruction is ambiguous in at&t syntax. With Intel syntax the memory operation caries a size that can be used to disambiguate.

llvm-svn: 322356
2018-01-12 06:48:26 +00:00
Craig Topper 29ccb5c87d [X86] Don't require suffix on 'clr' mnemonic in intel syntax
llvm-svn: 322355
2018-01-12 06:48:24 +00:00
Craig Topper b1623321af [X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics.
While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler.

llvm-svn: 322354
2018-01-12 06:21:36 +00:00
Craig Topper 0ccbbf3f3b [X86] Disable sldtq parsing in 64-bit mode.
llvm-svn: 322353
2018-01-12 05:38:15 +00:00
Craig Topper 3554a71cf1 [X86] Disable movsq/stosq/scasqcmpsq/lodsq parsing in 64-bit mode.
llvm-svn: 322352
2018-01-12 05:38:14 +00:00
Eric Fiselier 64a0db76f9 [CMake] Add LLVM_ENABLE_IDE option to better process sources for IDE's
Summary:
Currently LLVM has no way to support configuring for IDE's like CLion. Like XCode and MSVC's IDE, CLion needs to see all of the headers and tablegen files in order to properly parse the sources.

This patch adds an `LLVM_ENABLE_IDE` option which can be used to configure for IDE's in general. It is used by `LLVMProcessSources.cmake` to determine if the extra source files should be added to the target.

Unfortunately because of the low level of `LLVMProcessSources.cmake`, I'm not sure where the `LLVM_ENABLE_IDE` option should live. I choose `HandleLLVMOptions.cmake` so that out-of-tree Clang builds would correctly configure the option by default.



Reviewers: beanz, mgorny, lebedev.ri

Reviewed By: beanz

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D40219

llvm-svn: 322349
2018-01-12 04:01:41 +00:00
Rui Ueyama 478d635156 Instead of ELFFile<ELFT>::Type, use ELFT::Type. NFC.
llvm-svn: 322346
2018-01-12 02:28:31 +00:00
Ana Pazos e3d248361e [RISCV] Pass MCSubtargetInfo to print methods.
Summary:

This change allows checking for ISA extensions in print methods.

Reviewers: asb, niosHD

Reviewed By: asb, niosHD

Subscribers: llvm-commits, niosHD, asb, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal

Differential Revision: https://reviews.llvm.org/D41503

llvm-svn: 322345
2018-01-12 02:27:00 +00:00
Rui Ueyama d7f96d0b91 Fix typo.
llvm-svn: 322344
2018-01-12 02:15:41 +00:00
Sam Clegg 4710ed7a8c [WebAssembly] Don't allow functions to be named twice
The spec doesn't allow this.

Differential Revision: https://reviews.llvm.org/D41974

llvm-svn: 322343
2018-01-12 02:11:31 +00:00
Rui Ueyama 1b31eb9414 Use ELF{32,64}{LE,BE} instead of ELFType<{little,big}, {true,false}>. NFC.
llvm-svn: 322342
2018-01-12 01:40:32 +00:00
Lang Hames 4628880167 [ORC] Add a stub ExecutionSession and VModuleKey type.
ExecutionSession will represent a running JIT program.

VModuleKey is a unique key assigned to each module added as part of
an ExecutionSession. The Layer concept will be updated in future to
require a VModuleKey when a module is added.

llvm-svn: 322336
2018-01-12 00:22:05 +00:00
David L. Jones 8c87213c26 Revert r322279 due to Skylake miscompile.
Summary:
This revision causes Skylake (and apparently, only Skylake) codegen to fail in
certain cases. Details: https://bugs.llvm.org/show_bug.cgi?id=35918

Subscribers: sanjoy, llvm-commits

Differential Revision: https://reviews.llvm.org/D41972

llvm-svn: 322335
2018-01-12 00:17:38 +00:00
Sam Clegg cd65f69808 [WebAssembly] MC: Remove SetUsed argument when calling MCSymbol::isDefined et al
Summary:
This argument (the isUsed flag) seems to only be relevant
when parsing.  Other calls sites such as these don't seem
to ever use it.

Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish

Differential Revision: https://reviews.llvm.org/D41970

llvm-svn: 322332
2018-01-11 23:59:16 +00:00
Sanjay Patel 6ef6aa987c [InstSimplify] fold implied cmp with zero (PR35790)
This doesn't handle the more complicated case in the bug report yet:
https://bugs.llvm.org/show_bug.cgi?id=35790

For that, we have to match / look through a cast.

llvm-svn: 322327
2018-01-11 23:27:37 +00:00
Matthias Braun bfd9c4a462 PeepholeOpt cleanup/refactor; NFC
- Less unnecessary use of `auto`
- Add early `using RegSubRegPair(AndIdx) =` to avoid countless
  `TargetInstrInfo::` qualifications.
- Use references instead of pointers where possible.
- Remove unused parameters.
- Rewrite the CopyRewriter class hierarchy:
   - Pull out uncoalescable copy rewriting functionality into
     PeepholeOptimizer class.
   - Use an abstract base class to make it clear that rewriters are
     independent.
- Remove unnecessary \brief in doxygen comments.
- Remove unused constructor and method from ValueTracker.
- Replace UseAdvancedTracking of ValueTracker with DisableAdvCopyOpt use.

llvm-svn: 322325
2018-01-11 22:59:33 +00:00
Evgeniy Stepanov 99fa3e774d [hwasan] Stack instrumentation.
Summary:
Very basic stack instrumentation using tagged pointers.
Tag for N'th alloca in a function is built as XOR of:
 * base tag for the function, which is just some bits of SP (poor
   man's random)
 * small constant which is a function of N.

Allocas are aligned to 16 bytes. On every ReturnInst allocas are
re-tagged to catch use-after-return.

This implementation has a bunch of issues that will be taken care of
later:
1. lifetime intrinsics referring to tagged pointers are not
   recognized in SDAG. This effectively disables stack coloring.
2. Generated code is quite inefficient. There is one extra
   instruction at each memory access that adds the base tag to the
   untagged alloca address. It would be better to keep tagged SP in a
   callee-saved register and address allocas as an offset of that XOR
   retag, but that needs better coordination between hwasan
   instrumentation pass and prologue/epilogue insertion.
3. Lifetime instrinsics are ignored and use-after-scope is not
   implemented. This would be harder to do than in ASan, because we
   need to use a differently tagged pointer depending on which
   lifetime.start / lifetime.end the current instruction is dominated
   / post-dominated.

Reviewers: kcc, alekseyshl

Subscribers: srhines, kubamracek, javed.absar, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D41602

llvm-svn: 322324
2018-01-11 22:53:30 +00:00
Sanjay Patel ac0edcb3f3 [InstSimplify] add tests for implied cmp with zero (PR35790); NFC
llvm-svn: 322323
2018-01-11 22:48:07 +00:00
Matthias Braun ea4359e922 PeepholeOptimizer: Fix for vregs without defs
The PeepholeOptimizer would fail for vregs without a definition. If this
was caused by an undef operand abort to keep the code simple (so we
don't need to add logic everywhere to replicate the undef flag).

Differential Revision: https://reviews.llvm.org/D40763

llvm-svn: 322319
2018-01-11 22:30:43 +00:00
Rafael Espindola e4b0231c63 Make internal/private GVs implicitly dso_local.
While updating clang tests for having clang set dso_local I noticed
that:

- There are *a lot* of tests to update.
- Many of the updates are redundant.

They are redundant because a GV is "obviously dso_local". This patch
starts formalizing that a bit by requiring that internal and private
GVs be dso_local too. Since they all are, we don't have to print
dso_local to the textual representation, making it a bit more compact
and easier to read.

llvm-svn: 322317
2018-01-11 22:15:05 +00:00
Paul Robinson cc9c8b95bd Tighten up DIFile verifier for checksums
Differential Revision: https://reviews.llvm.org/D41965

llvm-svn: 322314
2018-01-11 22:03:43 +00:00
Matthias Braun 08abcac9dc PeepholeOptimizer: Do not form PHI with subreg arguments
When replacing a PHI the PeepholeOptimizer currently takes the register
class of the register at the first operand. This however is not correct
if this argument has a subregister index.

As there is currently no API to query the register class resulting from
applying a subregister index to all registers in a class, we can only
abort in these cases and not perform the transformation.

This changes findNextSource() to require the end of all copy chains to
not use a subregister if there is any PHI in the chain. I had to rewrite
the overly complicated inner loop there to have a good place to insert
the new check.

This fixes https://llvm.org/PR33071 (aka rdar://32262041)

Differential Revision: https://reviews.llvm.org/D40758

llvm-svn: 322313
2018-01-11 21:57:03 +00:00
Evgeniy Stepanov 5223b5d9d6 [arm] Implement Target Operand Flag MIR serialization.
Reviewers: efriedma, pcc

Subscribers: aemerson, javed.absar, kristof.beyls, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D39975

llvm-svn: 322312
2018-01-11 21:37:58 +00:00
Fiona Glaser efe6a84e5b [Sink] Really really fix predicate in legality check
LoadInst isn't enough; we need to include intrinsics that perform loads too.

All side-effecting intrinsics and such are already covered by the isSafe
check, so we just need to care about things that read from memory.

D41960, originally from D33179.

llvm-svn: 322311
2018-01-11 21:28:57 +00:00
Sam Clegg d423f0d290 [WebAssemlby] MC: Don't write COMDAT symbols as global imports
This was causing undefined references at link time in lld.

Differential Revision: https://reviews.llvm.org/D41959

llvm-svn: 322309
2018-01-11 20:35:17 +00:00
Craig Topper 2aac3ee5bc [X86] Legalize 128/256 gathers/scatters on KNL by using widening rather than sign extending the index.
We can just widen the vectors with undef and zero extend the mask.

llvm-svn: 322308
2018-01-11 19:38:30 +00:00
Sam Clegg 0ce22ef799 [WebAssemly] Rename and improve formatting for ctor/dtor test
llvm-svn: 322307
2018-01-11 19:37:03 +00:00
Aaron Ballman aac638eb1e Use size_t to represent the size of a StringMapEntry length and alignment rather than unsigned.
Patch by Matt Davis.

llvm-svn: 322305
2018-01-11 18:47:15 +00:00
Adrian Prantl 29102b3002 dag-combine: Transfer debug information when folding (zext (truncate x))
-> (zext (truncate x))

This patch adds debug info support to the dagcombine rule (zext
(truncate x)) -> (zext (truncate x)).

Differential Revision: https://reviews.llvm.org/D41924

llvm-svn: 322304
2018-01-11 18:35:12 +00:00
Krzysztof Parzyszek 240df6faa4 [Hexagon] Fix building 64-bit vector from constant values
The constants were aggregated in a reverse order.

llvm-svn: 322303
2018-01-11 18:30:41 +00:00
Krzysztof Parzyszek 4ef6cfff6a [Hexagon] Cast elements to correct type when creating constant vector
llvm-svn: 322301
2018-01-11 18:03:23 +00:00
Zvi Rackover 999e6c2967 DAGCombine: Let truncates negate extension through extract-subvector
Summary:
Fold cases such as:
(v8i8 truncate (v8i32 extract_subvector (v16i32 sext (v16i8 V), Idx)))
->
(v8i8 extract_subvector (v16i8 V), Idx)

This can be generalized to cases where the truncate and extend do not
fully cancel each other out, but it may require querying the target
about profitability.

Reviewers: RKSimon, craig.topper, spatel, efriedma

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41927

llvm-svn: 322300
2018-01-11 18:02:33 +00:00
Krzysztof Parzyszek be6fa82ee5 [Hexagon] Impose limits on container sizes in HexagonGenInsert
With over 300k virtual registers, the size of the data exceeded 12GB.
Impose limits on how much information is collected.

llvm-svn: 322299
2018-01-11 18:02:13 +00:00
Krzysztof Parzyszek e156e9ba0f [Hexagon] Use SetVector when queuing nodes to scan in selectVectorConstants
llvm-svn: 322298
2018-01-11 17:59:34 +00:00