6c5c6aa9d8
[AVR] Remove the instrumentation pass
...
I have a much better way of running integration tests now.
https://github.com/dylanmckay/avr-test-suite
llvm-svn: 308857
2017-07-23 23:39:11 +00:00
94c636b7aa
[AVR] Improve the 'icall-func-pointer-correct-addr-space.ll' test
...
Patch by Carl Peto.
llvm-svn: 308856
2017-07-23 23:00:55 +00:00
2c59215ae3
[AVR] Fix a typo in the tests
...
llvm-svn: 308148
2017-07-16 22:31:07 +00:00
9fb04071a2
[AVR] Fix indirect calls to function pointers
...
Patch by Carl Peto.
llvm-svn: 307888
2017-07-13 08:09:36 +00:00
9cf1dc1e0f
[AVR] Use the generic branch relaxer
...
llvm-svn: 307617
2017-07-11 04:17:13 +00:00
448c56e2a5
[AVR] Fix test errors due to tied operands not matching
...
Broken due to r307259.
llvm-svn: 307503
2017-07-09 16:36:35 +00:00
a24aa19900
Revert "[AVR] Add the branch selection pass from the GitHub repository"
...
This reverts commit 602ef067c1d58ecb425d061f35f2bc4c7e92f4f3.
llvm-svn: 307111
2017-07-05 00:50:56 +00:00
f115c7f917
[AVR] Add the branch selection pass from the GitHub repository
...
We should rewrite this using the generic branch relaxation pass, but for
the moment having this pass is better than hitting an assertion error.
llvm-svn: 307109
2017-07-05 00:41:19 +00:00
b224d98594
[AVR] Fix bug which caused assertion errors for some FRMIDX instructions
...
Previously, if a basic block ended with a FRMIDX instruction, we would
end up doing something like this.
*std::next(MBB.end())
Which would hit an error:
"Assertion `!NodePtr->isKnownSentinel()' failed."
llvm-svn: 307057
2017-07-04 04:40:06 +00:00
043fa4b3d6
[AVR] Fix a big in shift operator lowering; Authored by Dr. Gergo Erdi
...
When generating code for a shift loop, check the shift
amount against the literal value 0, not R0
llvm-svn: 304284
2017-05-31 06:27:46 +00:00
0c4debc123
[AVR] When lowering Select8/Select16, put newly generated MBBs in the same spot
...
Contributed by Dr. Gergő Érdi.
Fixes a bug.
Raised from (https://github.com/avr-rust/rust/issues/49 ).
llvm-svn: 302973
2017-05-13 00:22:34 +00:00
4aedb8a6b7
[AVR] Reserve the Y register in all functions
...
llvm-svn: 302017
2017-05-03 11:56:01 +00:00
28355efdad
[AVR] Save/restore the frame pointer for all functions
...
A recent commit I made made it so that we only did this for signal or
interrupt handlers. This broke normal functions.
llvm-svn: 301893
2017-05-02 01:57:48 +00:00
59e7fe3da8
[AVR] Implement non-constant bit rotations
...
This lets us do bit rotations of variable amount.
llvm-svn: 301794
2017-05-01 09:48:55 +00:00
8f515b1ef7
[AVR] Support the LDWRdPtr instruction with the same Src+Dst register
...
llvm-svn: 301313
2017-04-25 15:09:04 +00:00
da2d74642a
[AVR] Remove the 'multibyte' asm test
...
It tests registers which are not actually used on AVR.
llvm-svn: 300684
2017-04-19 12:13:45 +00:00
7838104382
[AVR] Fix the test suite
...
A bunch of tests failed because memory operations have been reordered.
I am unsure which commit changed this behaviour as the AVR build was
failing at that point with an unrelated error.
This commit just reoders some of the CHECK lines in some tests to suit
current llc output.
llvm-svn: 300682
2017-04-19 12:02:52 +00:00
19d9533496
[AVR] Disable integrated assembler for a few tests
...
Fixes the build.
llvm-svn: 295895
2017-02-22 22:41:13 +00:00
f1141285eb
MIRTests: Remove unnecessary 2>&1 redirection
...
llc mir output goes to stdout nowadays, so the 2>&1 is not necessary
anymore for most tests.
llvm-svn: 295859
2017-02-22 18:47:41 +00:00
ccd819ad94
[AVR] Implement stacksave/stackrestore by expanding (PR31342)
...
Summary:
Authored by Florian Zeitz.
This implements the missing stacksave/stackrestore intrinsics via expansion.
Output of `llc -O0 -march=avr ~/devel/llvm/test/CodeGen/Generic/stacksave-restore.ll` for sanity checking (comments mine):
```
.text
.file ".../llvm/test/CodeGen/Generic/stacksave-restore.ll"
.globl test
.p2align 1
.type test,@function
test: ; @test
; BB#0:
push r28
push r29
in r28, 61
in r29, 62
sbiw r28, 4
in r0, 63
cli
out 62, r29
out 63, r0
out 61, r28
in r18, 61
in r19, 62
mov r20, r22
mov r21, r23
in r30, 61
in r31, 62
lsl r22
rol r23
lsl r22
rol r23
in r26, 61
in r27, 62
sub r26, r22
sbc r27, r23
andi r26, 252
in r0, 63
cli
out 62, r27
out 63, r0
out 61, r26
in r0, 63
cli
out 62, r31
out 63, r0
out 61, r30
in r30, 61
in r31, 62
sub r30, r22
sbc r31, r23
andi r30, 252
in r0, 63
cli
out 62, r31
out 63, r0
out 61, r30
std Y+3, r24 ; 2-byte Folded Spill
std Y+4, r25 ; 2-byte Folded Spill
mov r24, r26
mov r25, r27
in r0, 63
cli
out 62, r19
out 63, r0
out 61, r18
std Y+1, r20 ; 2-byte Folded Spill
std Y+2, r21 ; 2-byte Folded Spill
adiw r28, 4
in r0, 63
cli
out 62, r29
out 63, r0
out 61, r28
pop r29
pop r28
ret
.Lfunc_end0:
.size test, .Lfunc_end0-test
```
Reviewers: dylanmckay
Reviewed By: dylanmckay
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D29553
llvm-svn: 294146
2017-02-05 21:35:45 +00:00
7653d91afa
[AVR] Marm MIR test functions as tracking liveness information
...
This fixes an assertion error that broke three tests.
llvm-svn: 294140
2017-02-05 20:25:34 +00:00
b78f36657e
[AVR] Fix a bug where asm operands are printed twice
...
We would unconditionally call printOperand, even if PrintAsmOperand
already printed the immediate.
llvm-svn: 294121
2017-02-05 10:42:49 +00:00
8fa6d8db9c
[AVR] Implement TargetLoweing::getRegisterByName
...
This allows the use of the 'read_register' intrinsics used by clang's
named register globals features.
llvm-svn: 291375
2017-01-07 23:39:47 +00:00
97cf837b46
[AVR] Optimize 16-bit ANDs with '1'
...
Summary: Fixes PR 31345
Reviewers: dylanmckay
Subscribers: fhahn, llvm-commits
Differential Revision: https://reviews.llvm.org/D28186
llvm-svn: 290778
2016-12-31 01:07:14 +00:00
453d042969
[AVR] Optimize 16-bit ORs with '0'
...
Summary: Fixes PR 31344
Authored by Anmol P. Paralkar
Reviewers: dylanmckay
Subscribers: fhahn, llvm-commits
Differential Revision: https://reviews.llvm.org/D28121
llvm-svn: 290732
2016-12-30 00:21:56 +00:00
90b6b5074a
[CodeGenPrep] Skip merging empty case blocks
...
This is recommit of r287553 after fixing the invalid loop info after eliminating an empty block and unit test failures in AVR and WebAssembly :
Summary: Merging an empty case block into the header block of switch could cause ISel to add COPY instructions in the header of switch, instead of the case block, if the case block is used as an incoming block of a PHI. This could potentially increase dynamic instructions, especially when the switch is in a loop. I added a test case which was reduced from the benchmark I was targetting.
Reviewers: t.p.northover, mcrosier, manmanren, wmi, joerg, davidxl
Subscribers: joerg, qcolombet, danielcdh, hfinkel, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D22696
llvm-svn: 289988
2016-12-16 20:38:39 +00:00
a81719fbfc
[AVR] Add a test for 64-bit left shifts
...
llvm-svn: 289936
2016-12-16 11:40:00 +00:00
4f590f28e7
[AVR] Support floats in the instrumention pass
...
This also refactors some common code into the 'GetTypeName' method.
llvm-svn: 289803
2016-12-15 11:02:41 +00:00
3abd1d3e12
[AVR] Add a function instrumentation pass
...
This will be used for an on-chip test suite.
llvm-svn: 289641
2016-12-14 10:15:00 +00:00
1e57fa487b
[AVR] Add an 'relax memory operation' pass
...
Summary:
This pass will be used to relax instructions which use out of bounds
memory accesses to equivalent operations that can work with the
addresses.
The pass currently implements relaxation for the STDWPtrQRr instruction.
Without this pass, an assertion error would be hit in the pseudo expansion pass.
In the future, we will need to add more instructions to this pass. We can do
that on a case-by-case basic.
Reviewers: arsenm, kparzysz
Subscribers: wdng, llvm-commits, mgorny
Differential Revision: https://reviews.llvm.org/D27650
llvm-svn: 289517
2016-12-13 05:53:14 +00:00
bf1d2edab2
[AVR] Add calling convention CodeGen tests
...
This adds CodeGen tests for the AVR C calling convention.
llvm-svn: 289369
2016-12-11 07:09:45 +00:00
72967a56e1
[AVR] Add a test to validate a simple 'blinking led' program
...
llvm-svn: 289362
2016-12-11 04:59:39 +00:00
d8a603c23b
[AVR] Fix and clean up the inline assembly tests
...
There was a bug where we would hit an assertion if 'Q' was used as a
constraint.
I also removed hardcoded register names to prefer regexes so the tests
don't break when the register allocator changes.
llvm-svn: 289325
2016-12-10 11:49:07 +00:00
a7e0548722
[AVR] Explicitly set the target in all CodeGen tests
...
This seems to have caused failures on the buildbot.
llvm-svn: 289324
2016-12-10 11:23:16 +00:00
5c90b8cb4f
[AVR] Use the register scavenger when expanding 'LDDW' instructions
...
Summary: This gets rid of the hardcoded 'r0' that was used previously.
Reviewers: asl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D27567
llvm-svn: 289322
2016-12-10 10:51:55 +00:00
5d0233bea2
[AVR] Support stores to undefined pointers
...
This would previously trigger an assertion error in AVRISelDAGToDAG.
llvm-svn: 289321
2016-12-10 10:16:13 +00:00
1cdbf42a33
[AVR] Remove a set of redundant tests
...
This fixes the build.
llvm-svn: 289201
2016-12-09 11:22:26 +00:00
a5d49dfbb3
[AVR] Add tests for a large number of pseudo instructions
...
This adds MIR tests for 24 pseudo instructions.
llvm-svn: 289191
2016-12-09 07:49:04 +00:00
371117e7a5
[AVR] Add MIR tests for pseudo instruction expansions
...
This adds tests for 13 pseudo instruction expansions.
llvm-svn: 289039
2016-12-08 10:52:13 +00:00
0cc0446ad2
[AVR] Add MIR tests for a few pseudo instructions
...
llvm-svn: 289031
2016-12-08 08:54:41 +00:00
99b756eb40
[AVR] Expand 'SELECT_CC' nodes whereever possible
...
llvm-svn: 288905
2016-12-07 12:34:47 +00:00
6dbc8d5a0c
[AVR] Move a pseudo expansion test into a folder
...
llvm-svn: 288899
2016-12-07 11:21:45 +00:00
8cec7eb6dd
[AVR] Allow loading from stack slots where src and dest registers are identical
...
Fixes PR 31256
llvm-svn: 288897
2016-12-07 11:08:56 +00:00
6e8c2b1b65
[AVR] Remove 'XFAIL' from a CodeGen test
...
This seems to be fixed as of r288052.
llvm-svn: 288618
2016-12-04 09:50:42 +00:00
656c1fa544
Un-XFAIL an AVR CodeGen test
...
llvm-svn: 287958
2016-11-26 01:07:32 +00:00
c2de8e8ec3
[AVR] Mark the 'select-must-add-unconditional-jump' test as 'XFAIL'
...
llvm-svn: 287871
2016-11-24 12:38:54 +00:00
48c26b2b12
[AVR] Remove some accidentally-commited code that broke the bots
...
This is a remnant of an on-chip unit testing tool that has since been
moved out-of-tree.
It was accidentally committed in r287162.
llvm-svn: 287180
2016-11-17 00:09:38 +00:00
6dd69032c9
[AVR] Fix basic block naming in ctlz and cttz tests
...
The branch selector would change the names.
llvm-svn: 287174
2016-11-16 22:48:38 +00:00
9701c42de9
[AVR] Add tests for counting leading/trailing zeros
...
This adds two test files that verify the 'cttz' and 'ctlz' operations.
llvm-svn: 287172
2016-11-16 22:38:43 +00:00
a789f40002
[AVR] Add the pseudo instruction expansion pass
...
Summary:
A lot of the pseudo instructions are required because LLVM assumes that
all integers of the same size as the pointer size are legal. This means
that it will not currently expand 16-bit instructions to their 8-bit
variants because it thinks 16-bit types are legal for the operations.
This also adds all of the CodeGen tests that required the pass to run.
Reviewers: arsenm, kparzysz
Subscribers: wdng, mgorny, modocache, llvm-commits
Differential Revision: https://reviews.llvm.org/D26577
llvm-svn: 287162
2016-11-16 21:58:04 +00:00
Dylan McKay