67a16e2564
tblgen: add preprocessor as a separate mode
...
This patch adds a preprocessor that can expand nested for-loops for
saving some copy-n-paste in *.td files.
The preprocessor is not yet integrated with TGParser, and so it has
no direct effect on *.td inputs. However, you may preprocess an td
input (and only preprocess it).
To test the proprecessor, type:
tblgen -E -o $@ $<
llvm-svn: 141079
2011-10-04 15:14:51 +00:00
3b309efe38
Set operation actions to legal types only.
...
llvm-svn: 141075
2011-10-04 12:05:35 +00:00
04001625e4
Operations should be custom lowered only if their type is legal.
...
Test: CellSPU/v2i32.ll when running with -promote-elements
llvm-svn: 141074
2011-10-04 10:03:32 +00:00
287682ead1
The product of two chrec's can always be represented as a chrec.
...
llvm-svn: 141066
2011-10-04 06:51:26 +00:00
f18c896337
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
...
llvm-svn: 141065
2011-10-04 06:30:42 +00:00
8de329a9fc
LSR should avoid redundant edge splitting.
...
This handles the case in which LSR rewrites an IV user that is a phi and
splits critical edges originating from a switch.
Fixes <rdar://problem/6453893> LSR is not splitting edges "nicely"
llvm-svn: 141059
2011-10-04 03:50:44 +00:00
411842f98f
whitespace
...
llvm-svn: 141058
2011-10-04 03:34:49 +00:00
74e5a2a712
Remove last references to hotpatch.
...
llvm-svn: 141057
2011-10-04 03:08:43 +00:00
b3334f9f43
Exclude libLLVMTableGen.a from the shared library
...
Unbreaks tools for --enable-shared build.
llvm-svn: 141052
2011-10-04 00:30:34 +00:00
ac3fb4c078
Generic cleanup.
...
llvm-svn: 141050
2011-10-04 00:16:40 +00:00
bf51f97c28
Unit test for r140919, loop unroll heuristics.
...
llvm-svn: 141049
2011-10-04 00:07:02 +00:00
b85400aa58
Tidy up. These tests are covered in the .s file tests now.
...
llvm-svn: 141047
2011-10-03 23:40:13 +00:00
e7fbce7acb
ARM assembly parsing and encoding for VMOV immediate.
...
llvm-svn: 141046
2011-10-03 23:38:36 +00:00
69e6f90eb2
Tidy up. 80 columns.
...
llvm-svn: 141043
2011-10-03 23:03:26 +00:00
1eab54f8ba
Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it.
...
llvm-svn: 141042
2011-10-03 22:44:15 +00:00
97a8695fff
Don't carry over the dispatchsetup hack from the old system.
...
llvm-svn: 141040
2011-10-03 22:42:40 +00:00
46b6646059
ARM parsing/encoding for VCMP/VCMPE.
...
llvm-svn: 141038
2011-10-03 22:30:24 +00:00
f66daac2f5
Fix typo in comments.
...
llvm-svn: 141032
2011-10-03 21:30:08 +00:00
374ee194f2
Check-pointing the new SjLj EH lowering.
...
This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.
llvm-svn: 141031
2011-10-03 21:25:38 +00:00
6c71ef32be
Move CHECK after entry label.
...
llvm-svn: 141030
2011-10-03 21:24:30 +00:00
c3a6357ee3
Add support for 64-bit logical NOR.
...
llvm-svn: 141029
2011-10-03 21:23:18 +00:00
48a72ca0cb
Add support for 64-bit count leading ones and zeros instructions.
...
llvm-svn: 141028
2011-10-03 21:16:50 +00:00
6f3e73d6ad
Move the grabbing of the jump buffer into the caller function, eliminating the need for returning a std::pair.
...
llvm-svn: 141026
2011-10-03 21:15:28 +00:00
4ab23b5273
ARM assembly parsing and encoding for VMRS/FMSTAT.
...
llvm-svn: 141025
2011-10-03 21:12:43 +00:00
b1538f91dc
Add support for 64-bit divide instructions.
...
llvm-svn: 141024
2011-10-03 21:06:13 +00:00
dbebc6f3f9
Add C api for Instruction->eraseFromParent().
...
llvm-svn: 141023
2011-10-03 20:59:18 +00:00
c3fc62b492
Update test for 141010.
...
llvm-svn: 141022
2011-10-03 20:58:08 +00:00
5dd3425b77
Thumb2 ADD/SUB can take SP as a destination register.
...
It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.
llvm-svn: 141020
2011-10-03 20:51:59 +00:00
3caf8cb310
Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integer
...
registers.
llvm-svn: 141019
2011-10-03 20:38:08 +00:00
a279d9bd6a
Add support for 64-bit integer multiply instructions.
...
llvm-svn: 141017
2011-10-03 20:01:11 +00:00
cdcc74563c
Add definitions of instructions which move values between 64-bit integer
...
registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.
llvm-svn: 141015
2011-10-03 19:28:44 +00:00
7f6f12405d
Find the strip tool that works with the specified SDKROOT. rdar://10165908
...
llvm-svn: 141013
2011-10-03 18:48:16 +00:00
b817655b77
Tidy up a bit. Formatting.
...
llvm-svn: 141010
2011-10-03 17:59:31 +00:00
786bdb9e14
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
...
llvm-svn: 141007
2011-10-03 17:28:23 +00:00
cead033ced
Whitespace.
...
llvm-svn: 141005
2011-10-03 15:49:20 +00:00
f84354bfb1
Typo.
...
llvm-svn: 141004
2011-10-03 15:49:16 +00:00
cc349c8dd8
Add the returns_twice attribute to LLVM.
...
llvm-svn: 141001
2011-10-03 14:45:37 +00:00
0d0be47d03
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.
...
llvm-svn: 140997
2011-10-03 08:14:29 +00:00
285bc34089
Test updates that were supposed to go with r140993.
...
llvm-svn: 140994
2011-10-03 07:53:59 +00:00
31854ba017
Fix VEX disassembling to ignore REX.RXBW bits in 32-bit mode.
...
llvm-svn: 140993
2011-10-03 07:51:09 +00:00
3155552461
Reapply r140979 with fix! We never did get a testcase, but careful review of the
...
logic by David Meyer revealed this bug.
llvm-svn: 140992
2011-10-03 07:10:45 +00:00
0038e0632c
attempt to fix ocaml bindings: landing pads
...
llvm-svn: 140991
2011-10-03 06:41:46 +00:00
b1dbce1406
Revert r140979 due to reports of bootstrap failure.
...
llvm-svn: 140980
2011-10-03 05:14:59 +00:00
3c624b8d0d
Add one more case we compute a max trip count.
...
llvm-svn: 140979
2011-10-03 01:03:57 +00:00
7aea69d949
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
...
llvm-svn: 140974
2011-10-02 21:08:12 +00:00
21c33657d6
Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344.
...
llvm-svn: 140971
2011-10-02 16:56:09 +00:00
99fb091f65
Add a new icmp+select optz'n. Also shows off the load(cst) folding added in
...
r140966.
llvm-svn: 140969
2011-10-02 10:37:37 +00:00
40a34dd9a3
Enhance a couple places where we were doing constant folding of instructions,
...
but not load instructions. Noticed by inspection.
llvm-svn: 140966
2011-10-02 09:12:55 +00:00
56ff34f7c5
Fix typo in r140954.
...
llvm-svn: 140962
2011-10-02 04:54:26 +00:00
539801f8bc
Make canonicalization of ImmutableSetRef::asImmutableSet() semi-explicit.
...
llvm-svn: 140959
2011-10-02 01:47:07 +00:00
d07a59f288
Fix disassembling of INVEPT and INVVPID to take operands
...
llvm-svn: 140955
2011-10-01 21:20:14 +00:00
88cb33e0d4
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
...
llvm-svn: 140954
2011-10-01 19:54:56 +00:00
a88cb23da7
Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."
...
to appease nightly testers. Not quite there yet.
llvm-svn: 140953
2011-10-01 19:30:36 +00:00
52e8ed9214
Moved type construction out of the loop and added an assert on the legality of the type. Formatted lines to the 80 char limit.
...
llvm-svn: 140952
2011-10-01 18:39:28 +00:00
84c287e33c
Move TableGen's parser and entry point into a library
...
This is the first step towards splitting LLVM and Clang's tblgen executables.
llvm-svn: 140951
2011-10-01 16:41:13 +00:00
d072b73d78
No one should be using the method directly. Assert if they do.
...
llvm-svn: 140947
2011-10-01 12:47:34 +00:00
f977ff5fb5
Add a convenience method to tell if two things are equal.
...
llvm-svn: 140946
2011-10-01 12:44:28 +00:00
4a4772fae2
Use the ARMConstantPoolMBB class to handle the MBB values.
...
llvm-svn: 140943
2011-10-01 09:30:42 +00:00
6dbc9fe82b
Add ARMConstantPoolMBB to hold an MBB value in the constant pool.
...
llvm-svn: 140942
2011-10-01 09:19:10 +00:00
c5a86069ca
Remove dead code.
...
llvm-svn: 140941
2011-10-01 09:05:12 +00:00
9ff05f740f
Remove now dead methods and ivar.
...
llvm-svn: 140940
2011-10-01 09:04:18 +00:00
c214cb055d
Use the new ARMConstantPoolSymbol class to handle external symbols.
...
llvm-svn: 140939
2011-10-01 08:58:29 +00:00
d7fa016720
Add an ARMConstantPool class for external symbols. This will split out the support for external symbols from the base class.
...
llvm-svn: 140938
2011-10-01 08:36:59 +00:00
d115c4d300
Remove now dead methods and ivar from ARMConstantPoolValue.
...
llvm-svn: 140937
2011-10-01 08:02:05 +00:00
7753d66468
Switch over to using ARMConstantPoolConstant for global variables, functions,
...
and block addresses.
llvm-svn: 140936
2011-10-01 08:00:54 +00:00
f117a35de0
Some more refactoring.
...
* Add a couple of Create methods to the ARMConstantPoolConstant class,
* Add its own version of getExistingMachineCPValue, and
* Modify hasSameValue to return false if the object isn't an ARMConstantPoolConstant.
llvm-svn: 140935
2011-10-01 07:52:37 +00:00
6722556380
Add a Create method that accepts 'kind' and 'pcadj' arguments.
...
llvm-svn: 140934
2011-10-01 06:44:24 +00:00
396c211ae1
Refactoring: Separate out the ARM constant pool Constant from the ARM constant
...
pool value.
It's not used right now, but will be soon.
llvm-svn: 140933
2011-10-01 06:40:33 +00:00
ce29158bc4
Subtarget getFeatureBits() returns a uint64_t, not unsigned.
...
llvm-svn: 140928
2011-10-01 02:47:54 +00:00
21360a4949
Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact
...
useful if an optimization assumes the stack has been realigned. Credit to
Eli for his assistance.
rdar://10043857
llvm-svn: 140924
2011-10-01 02:03:18 +00:00
f7656015fc
Inlining and unrolling heuristics should be aware of free truncs.
...
We want heuristics to be based on accurate data, but more importantly
we don't want llvm to behave randomly. A benign trunc inserted by an
upstream pass should not cause a wild swings in optimization
level. See PR11034. It's a general problem with threshold-based
heuristics, but we can make it less bad.
llvm-svn: 140919
2011-10-01 01:39:05 +00:00
caa500bf93
whitespace
...
llvm-svn: 140916
2011-10-01 01:27:56 +00:00
44a36c872e
Add Windows x64 stack walking support. Patch by Aaron Ballman!
...
llvm-svn: 140906
2011-10-01 00:05:20 +00:00
6417395d67
Use precomputed BitVector for CodeGenRegisterClass::hasSubClass().
...
All the sub-class bit vectors are computed when first creating the
register bank.
llvm-svn: 140905
2011-09-30 23:47:05 +00:00
b34639de75
Filecheck-ize.
...
llvm-svn: 140904
2011-09-30 23:40:29 +00:00
24b6b8d16a
Add new line at end of file.
...
llvm-svn: 140903
2011-09-30 23:21:11 +00:00
9925f197cc
When inferring the pointer alignment, if the global doesn't have an initializer
...
and the alignment is 0 (i.e., it's defined globally in one file and declared in
another file) it could get an alignment which is larger than the ABI allows for
that type, resulting in aligned moves being used for unaligned loads.
For instance, in file A.c:
struct S s;
In file B.c:
struct {
// something long
};
extern S s;
void foo() {
struct S p = s;
// ...
}
this copy is a 'memcpy' which is turned into a series of 'movaps' instructions
on X86. But this is wrong, because 'struct S' has alignment of 4, not 16.
llvm-svn: 140902
2011-09-30 23:19:55 +00:00
f40df1d46c
Promote comment to doxycomment. Adjust whitespace. No functionality change.
...
llvm-svn: 140899
2011-09-30 22:19:53 +00:00
237dceff90
Store sub-class lists as a bit vector.
...
This uses less memory and it reduces the complexity of sub-class
operations:
- hasSubClassEq() and friends become O(1) instead of O(N).
- getCommonSubClass() becomes O(N) instead of O(N^2).
In the future, TableGen will infer register classes. This makes it
cheap to add them.
llvm-svn: 140898
2011-09-30 22:19:07 +00:00
8153f6c39f
Extract a slightly more general BitVector printer.
...
This one can also print 32-bit groups.
llvm-svn: 140897
2011-09-30 22:18:54 +00:00
1352be2bd3
Move getCommonSubClass() into TRI.
...
It will soon need the context.
llvm-svn: 140896
2011-09-30 22:18:51 +00:00
b15fad9df4
Compute lists of super-classes in CodeGenRegisterClass.
...
Use these lists instead of computing them on the fly in
RegisterInfoEmitter.
llvm-svn: 140895
2011-09-30 22:18:45 +00:00
d76f43e18c
Correct for my over-eager delete finger.
...
llvm-svn: 140892
2011-09-30 22:02:45 +00:00
e67a10d54d
Add definition of MipsELFObjectWriter.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140891
2011-09-30 21:55:40 +00:00
ee09394644
Register the MC object streamer.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140887
2011-09-30 21:29:38 +00:00
44220ca045
Register Asm backend. Add functions to MipsAsmBackend.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140886
2011-09-30 21:23:45 +00:00
587fe6cd52
Add MCELFObjectTargetWriter and MCAsmBackend classes.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140885
2011-09-30 21:04:02 +00:00
dc221dd649
Test More Complicated Lists
...
Test of indexing lists of lists of lists works. This also exercises
some operators.
llvm-svn: 140884
2011-09-30 20:59:52 +00:00
0c3a2b48e7
Test VarListElementInit:: resolveListElementReference
...
Add a TableGen test to check if indexing lists of lists works.
llvm-svn: 140883
2011-09-30 20:59:51 +00:00
74ce80f34e
Implement VarListElementInit:: resolveListElementReference
...
Implement VarListElementInit:: resolveListElementReference so that
lists of lists can be indexed.
llvm-svn: 140882
2011-09-30 20:59:49 +00:00
3bad73a900
Update CMake build.
...
llvm-svn: 140879
2011-09-30 20:44:33 +00:00
750ecec7d5
Initial implementation of MipsMCCodeEmitter.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140878
2011-09-30 20:40:03 +00:00
011dafba61
Don't modify constant in-place.
...
llvm-svn: 140875
2011-09-30 19:58:46 +00:00
2f0cbf6a99
Tracing or debug-printing a newly formed instruction should not crash.
...
llvm-svn: 140874
2011-09-30 19:50:40 +00:00
ec4b6e7fe5
whitespace
...
llvm-svn: 140873
2011-09-30 19:48:58 +00:00
1fef284cf9
Remove unnecessary checking of register operands.
...
llvm-svn: 140872
2011-09-30 19:18:24 +00:00
7ba8a8d656
Add definitions of Mips64 rotate instructions.
...
llvm-svn: 140870
2011-09-30 18:51:46 +00:00
24ff834671
float comparison to double 'zero' constant can just be a float 'zero.'
...
InstCombine was incorrectly considering the conversion of the constant
zero to be unsafe.
We want to transform:
define float @bar(float %x) nounwind readnone optsize ssp {
%conv = fpext float %x to double
%cmp = fcmp olt double %conv, 0.000000e+00
%conv1 = zext i1 %cmp to i32
%conv2 = sitofp i32 %conv1 to float
ret float %conv2
}
Into:
define float @bar(float %x) nounwind readnone optsize ssp {
%cmp = fcmp olt float %x, 0.000000e+00 ; <---- This
%conv1 = zext i1 %cmp to i32
%conv2 = sitofp i32 %conv1 to float
ret float %conv2
}
rdar://10215914
llvm-svn: 140869
2011-09-30 18:45:50 +00:00
e8e4dbf468
Constify 'isLSDA' and move a method out-of-line.
...
llvm-svn: 140868
2011-09-30 18:42:06 +00:00
129c52af18
Tidy up. Trailing whitespace.
...
llvm-svn: 140865
2011-09-30 18:09:53 +00:00
4e0dbee62b
ARM Darwin default relocation model is PIC.
...
This matches clang, so default options in llc and friends are now closer to
clang's defaults.
llvm-svn: 140863
2011-09-30 17:41:35 +00:00
9727af7657
isCommutable should be 0 for DSUBu.
...
llvm-svn: 140862
2011-09-30 17:26:36 +00:00
d2222c386c
ARM Fixup valus for movt/movw are for the whole value.
...
Remove an assert that was expecting only the relevant 16bit portion for
the fixup being handled. Also kill some dead code in the T2 portion.
rdar://9653509
llvm-svn: 140861
2011-09-30 17:23:05 +00:00
b381129095
Check values of immediate operands.
...
llvm-svn: 140860
2011-09-30 17:19:21 +00:00
c874e2d8fb
Fix a bug in compare_numeric().
...
Thanks to Alexandru Dura and Jonas Paulsson for finding it.
llvm-svn: 140859
2011-09-30 17:03:55 +00:00
d6c0011d92
Add forgotten tests that the cleanup flag is cleared if there
...
is a catch-all landingpad clause.
llvm-svn: 140858
2011-09-30 17:00:34 +00:00
64b1aad4e3
MCJIT initialization TargetData
...
llvm-svn: 140856
2011-09-30 16:40:10 +00:00
ea3f90ae40
PTX: Various stylistic and code readability changes recommended by Jim Grosbach.
...
llvm-svn: 140855
2011-09-30 14:36:36 +00:00
957a6d5c51
PTX: Add programmable rounding mode specifier for int <-> fp conversion instrs.
...
Also take this opportunity to clean up the rounding mode pass.
llvm-svn: 140854
2011-09-30 13:46:52 +00:00
5c05579f94
Inlining often produces landingpad instructions with repeated
...
catch or repeated filter clauses. Teach instcombine a bunch
of tricks for simplifying landingpad clauses. Currently the
code only recognizes the GNU C++ and Ada personality functions,
but that doesn't stop it doing a bunch of "generic" transforms
which are hopefully fine for any real-world personality function.
If these "generic" transforms turn out not to be generic, they
can always be conditioned on the personality function. Probably
someone should add the ObjC++ personality function. I didn't as
I don't know anything about it.
llvm-svn: 140852
2011-09-30 13:12:16 +00:00
52cac090c4
some 3.0 API notes
...
llvm-svn: 140851
2011-09-30 13:07:52 +00:00
be5020eb95
Comment grammar fixes.
...
thanks to Duncan.
llvm-svn: 140850
2011-09-30 13:07:47 +00:00
3111d11f23
PTX: Attempt to cleanup/unify the handling of FP rounding modes. This requires
...
us to manually provide Pat<> definitions for all FP instruction patterns.
llvm-svn: 140849
2011-09-30 12:54:43 +00:00
319a1415b8
Instead of crashing when MCAsmInfo is NULL, add an assert.
...
This helps with porting code from 2.9 to 3.0 as TargetSelect.h changed location,
and if you include the old one by accident you will trigger this assert.
llvm-svn: 140848
2011-09-30 12:31:57 +00:00
61e256aa69
Mips64 shift instructions.
...
llvm-svn: 140841
2011-09-30 03:18:46 +00:00
7769a77710
Mips64 arithmetic and logical instructions with one source register and
...
immediate.
llvm-svn: 140839
2011-09-30 02:08:54 +00:00
efc761a1eb
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
...
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
llvm-svn: 140834
2011-09-30 00:50:06 +00:00
2c024b2d6a
Precompute a bit vector of register sub-classes.
...
llvm-svn: 140827
2011-09-30 00:10:40 +00:00
c0fc173da0
Order register classes topologically.
...
All register classes are given a lower ID than their sub-classes.
Cliques are ordered alphabetically.
This will be used to simplify some sub-class operations.
llvm-svn: 140826
2011-09-30 00:10:36 +00:00
f2619ee3ff
Fill delay slot with useful instructions. Modified from Sparc's version of delay
...
slot filler.
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140825
2011-09-29 23:52:13 +00:00
69bc3de4fc
Create a machine basic block in the constant pool and retrieve the symbol for an MBB.
...
llvm-svn: 140824
2011-09-29 23:50:42 +00:00
a1127b2fa2
Support creating a constant pool value for a machine basic block.
...
This is used when we want to take the address of a machine basic block, but it's
not associated with a BB in LLVM IR.
llvm-svn: 140823
2011-09-29 23:48:44 +00:00
a3e7ffdae8
Fold two identical set lookups into one. No functionality change.
...
llvm-svn: 140821
2011-09-29 23:40:12 +00:00
19be2ab320
Switch to ArrayRef<CodeGenRegisterClass*>.
...
This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.
llvm-svn: 140816
2011-09-29 22:28:37 +00:00
4ac148dcbc
When eliminating unnecessary retain+autorelease on return values,
...
handle the case where the retain is in a different basic block.
rdar://10210274.
llvm-svn: 140815
2011-09-29 22:27:34 +00:00
2053a5dd64
Don't eliminate objc_retainBlock calls on stack objects if the
...
objc_retainBlock call is potentially responsible for copying
the block to the heap to extend its lifetime. rdar://10209613.
llvm-svn: 140814
2011-09-29 22:25:23 +00:00
3f030ff016
Tidy up. Formatting.
...
llvm-svn: 140810
2011-09-29 21:43:01 +00:00
8574cbfd58
Fix typo.
...
llvm-svn: 140807
2011-09-29 21:07:46 +00:00
36036412e2
Mips64 arithmetic and logical instructions with two source registers.
...
llvm-svn: 140806
2011-09-29 20:37:56 +00:00
95031ed837
Clean up uses of switch instructions so they are not dependent on the operand ordering. Patch by Stepan Dyatkovskiy.
...
llvm-svn: 140803
2011-09-29 20:21:17 +00:00
e5a8f2f9f3
Simplify.
...
llvm-svn: 140789
2011-09-29 17:06:40 +00:00
eec5c5bf6e
Clarify comments.
...
llvm-svn: 140787
2011-09-29 16:52:53 +00:00
1e6ee351fc
Remove unnecessary and unused data member.
...
llvm-svn: 140786
2011-09-29 16:48:44 +00:00
a9e8a2504c
Cosmetic changes, as per Nick's review.
...
llvm-svn: 140785
2011-09-29 16:46:47 +00:00
cac86805bf
Place this bracket according to the LLVM style.
...
llvm-svn: 140784
2011-09-29 16:01:46 +00:00
abcc57669d
PTX: Fix broken shared library build
...
llvm-svn: 140783
2011-09-29 14:25:48 +00:00
dd1904e7a6
Expand the x86 V_SET0* pseudos right after register allocation.
...
This also makes it possible to reduce the number of pseudo instructions
and get rid of the encoding information.
llvm-svn: 140776
2011-09-29 05:10:54 +00:00
15b3c9c684
Target/ARM: Unbreak! CMake! Build!
...
llvm-svn: 140774
2011-09-29 03:32:49 +00:00
bf64024a39
Delete NEONMoveFix, now unused.
...
llvm-svn: 140773
2011-09-29 02:56:45 +00:00
f7ad189033
Use ExecutionDepsFix instead of NEONMoveFix.
...
This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.
llvm-svn: 140772
2011-09-29 02:48:41 +00:00
168dfffdb8
typo + pasto
...
llvm-svn: 140769
2011-09-29 01:53:08 +00:00
463b05a2d0
Remove NumImplicitOps which is now unused.
...
llvm-svn: 140767
2011-09-29 01:47:36 +00:00
bc6de90a5f
LSR: rewrite inner loops only.
...
Rewriting the entire loop nest now requires -enable-lsr-nested.
See PR11035 for some performance data.
A few unit tests specifically test nested LSR, and are now under a flag.
llvm-svn: 140762
2011-09-29 01:33:38 +00:00
37470d5bde
whitespace
...
llvm-svn: 140761
2011-09-29 01:31:48 +00:00
7dc278dc52
Fix build failures better.
...
llvm-svn: 140758
2011-09-29 01:22:31 +00:00
9a6fa7cf3d
Fix build failure.
...
llvm-svn: 140755
2011-09-29 01:14:42 +00:00
a0d5f268a9
Move to ISelLowering.
...
llvm-svn: 140754
2011-09-29 01:13:55 +00:00
fd47d8af8b
PTX: Add new patterns for bitconvert and any_extend
...
llvm-svn: 140753
2011-09-29 01:13:12 +00:00
cc5f8d4517
llvm-size: Apply Chris's code review fixes.
...
This doesn't use formated_raw_ostream because it doesn't support the
functionality needed.
llvm-svn: 140751
2011-09-29 00:59:18 +00:00
d299dccf91
Use the local we already set up.
...
llvm-svn: 140745
2011-09-29 00:50:59 +00:00
2318d1e0e9
Rewrite MachineInstr::addOperand() to avoid NumImplicitOps.
...
The function needs to scan the implicit operands anyway, so no
performance is won by caching the number of implicit operands added to
an instruction.
This also fixes a bug when adding operands after an implicit operand has
been added manually. The NumImplicitOps count wasn't kept up to date.
MachineInstr::addOperand() will now consistently place all explicit
operands before all the implicit operands, regardless of the order they
are added. It is possible to change an MI opcode and add additional
explicit operands. They will be inserted before any existing implicit
operands.
The only exception is inline asm instructions where operands are never
reordered. This is because of a hack that marks explicit clobber regs
on inline asm as <implicit-def> to please the fast register allocator.
This hack can go away when InstrEmitter and FastIsel can add exact
<dead> flags to physreg defs.
llvm-svn: 140744
2011-09-29 00:40:51 +00:00
9c248ac29e
tblgen/ClangDiagnostics: Add support for split default warning "no-werror" and
...
"show-in-system-header" bits, which I will be adding in Clang shortly.
llvm-svn: 140741
2011-09-29 00:29:04 +00:00
6728958279
Revert r140731, "Define classes for unary and binary FP instructions and use them to define"
...
It broke the unit tests. Please reapply with tests fixed.
llvm-svn: 140735
2011-09-28 23:59:28 +00:00
8156376aa9
Tighten a ARM dag combine condition to avoid an identity transformation, which
...
ends up introducing a cycle in the DAG.
rdar://10196296
llvm-svn: 140733
2011-09-28 23:16:31 +00:00
5a1b4a80c3
Define classes for unary and binary FP instructions and use them to define
...
multiclasses.
llvm-svn: 140731
2011-09-28 21:58:01 +00:00
899da52d60
Have the SjLjEHPrepare pass do some more heavy lifting.
...
Upon further review, most of the EH code should remain written at the IR
level. The part which breaks SSA form is the dispatch table, so that part will
be moved to the back-end.
llvm-svn: 140730
2011-09-28 21:56:53 +00:00
7f168777e5
Fix cast.
...
llvm-svn: 140726
2011-09-28 21:24:44 +00:00
2fb357a5b0
PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU does not support them.
...
llvm-svn: 140723
2011-09-28 21:00:25 +00:00
c4ad46605e
Add llvm-size.
...
llvm-svn: 140722
2011-09-28 20:57:46 +00:00
800619f2bb
Object: Add isSection{Data,BSS}.
...
llvm-svn: 140721
2011-09-28 20:57:30 +00:00
c7a710f61e
NULL cannot be portably used as the last argument to a function with __attribute((sentinel)), even though it usually works. Use (void*)0 instead. PR11002.
...
llvm-svn: 140720
2011-09-28 20:41:50 +00:00
315b9573c6
Perform the lowering only if there are invokes.
...
llvm-svn: 140719
2011-09-28 20:29:45 +00:00
dfe5acd34e
Ahem...actually *add* the ARMSjLjLowering pass to the pass manager.
...
llvm-svn: 140718
2011-09-28 20:29:28 +00:00
508503b473
Add a note on removing LLVMC.
...
llvm-svn: 140715
2011-09-28 19:47:28 +00:00
3714065a94
Introduce llvm-cov.
...
Add llvm-cov skeleton. It has initial support to read coverage info generated by GCOVProfiling.cpp.
Today, you can do
prompt> clang a.c -ftest-coverage -fprofile-arcs -o a
prompt> ./a
prompt> llvm-cov -gcno a.gcno -gcda a.gcda
a.c
: #include "a.h"
:
: int main() {
: int i = 0;
: if (i) {
1: int j = 0;
1: j = 1;
1: } else {
: int k = 1;
: k = 2;
: }
1: return 0;
: }
:
:
llvm-svn: 140712
2011-09-28 18:50:00 +00:00
933d51682f
PTX: Fix alignment logic
...
llvm-svn: 140709
2011-09-28 18:24:58 +00:00
6f37b4a5a5
Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit.
...
llvm-svn: 140705
2011-09-28 18:11:19 +00:00
edc172d4cc
Remove definitions of branch-on-FP-likely instructions. They are deprecated.
...
llvm-svn: 140704
2011-09-28 17:56:55 +00:00
c117967b19
Mips64 predicate definitions. Patch by Liu.
...
llvm-svn: 140703
2011-09-28 17:50:27 +00:00
ef8e4efff8
indvars: generalize SCEV getPreStartForSignExtend.
...
Handle general Add expressions to avoid leaving around redundant
32-bit IVs.
llvm-svn: 140701
2011-09-28 17:02:54 +00:00
f3d1d4eb4b
PTX: MC-ize the PTX backend (patch 2 of N)
...
Get rid of some of the no-longer-needed parts of PTXAsmPrinter.
llvm-svn: 140698
2011-09-28 14:32:06 +00:00
5e18b14ee2
PTX: MC-ize the PTX back-end (patch 1 of N)
...
Lay some groundwork for converting to MC-based asm printer. This is the first
of probably many patches to bring the back-end back up-to-date with all of the
recent MC changes.
llvm-svn: 140697
2011-09-28 14:32:04 +00:00
21efa7d6e1
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
...
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
llvm-svn: 140696
2011-09-28 14:21:38 +00:00
56c58ce3d6
Changed comments on foreign C++ exceptions (generated with type info 7),
...
handling with references to
http://sourcery.mentor.com/public/cxx-abi/abi-eh.html (r 1.22).
llvm-svn: 140695
2011-09-28 10:53:56 +00:00
2e67937f76
A typeid of zero means a cleanup, not a catch. This case occurs
...
when there is both a catch and a cleanup. Correct the comment.
llvm-svn: 140686
2011-09-28 09:13:02 +00:00
8747e3e7ea
PTX: Simplify code. No functionality change.
...
llvm-svn: 140680
2011-09-28 04:32:36 +00:00
5d7a73fa8c
PTX: Pass param name strings per const reference.
...
The copies caused use-after-free bugs on std::string implementations without COW (i.e. anything but libstdc++)
llvm-svn: 140679
2011-09-28 04:08:02 +00:00
baf3941fde
Strip off pointer casts when looking at the eh.sjlj.functioncontext's argument.
...
llvm-svn: 140678
2011-09-28 03:52:41 +00:00
225e8481b0
Bitcast the alloca to an i8* to match the intrinsic's signature.
...
llvm-svn: 140677
2011-09-28 03:47:11 +00:00
66b110f571
Create and use an llvm.eh.sjlj.functioncontext intrinsic.
...
This intrinsic is used to pass the index of the function context to the back-end
for further processing. The back-end is in charge of filling in the rest of the
entries.
llvm-svn: 140676
2011-09-28 03:36:43 +00:00
2e76ca9d9a
In the new EH model, setup the function context and the call site info.
...
The DWARF exception pass uses the call site information, which is set up here. A
pre-RA pass is too late for it to use this information. So create and setup the
function context here, and then insert the call site values here (and map the
call sites for the DWARF EH pass). This is simpler than the original pass, and
doesn't make the CFG lose its SSA-ness.
It's a win-win-win-win-lose-win-win situation.
llvm-svn: 140675
2011-09-28 03:14:05 +00:00
e6138e3ad1
Don't conditionalize execution of the SjLj EH prepare pass.
...
We may need an SjLj EH preparation pass for some call site information, at least
in the short term.
llvm-svn: 140674
2011-09-28 03:07:34 +00:00
8c219ecd1a
Test case for r140670: indvars should hoist sext.
...
llvm-svn: 140671
2011-09-28 02:13:32 +00:00
e0e30532a5
indvars should hoist [sz]ext because licm is not rerun.
...
llvm-svn: 140670
2011-09-28 01:35:36 +00:00
5f476dc3ef
PR10628: Fix getModRefInfo so it queries the underlying alias() implementation correctly while checking nocapture calls.
...
llvm-svn: 140666
2011-09-28 00:34:27 +00:00
bd5109f14d
Rename class and clean up source.
...
No functional change intended.
llvm-svn: 140664
2011-09-28 00:01:56 +00:00
934b7d7645
Rename SSEDomainFix -> lib/CodeGen/ExecutionDepsFix.
...
I'll clean up the source in the next commit.
llvm-svn: 140663
2011-09-28 00:01:54 +00:00
ae40dc735d
Remove MipsFPRound. Mips1 is no longer supported.
...
llvm-svn: 140661
2011-09-27 23:55:37 +00:00
30c811246f
Remove X86-dependent stuff from SSEDomainFix.
...
This also enables domain swizzling for AVX code which required a few
trivial test changes.
The pass will be moved to lib/CodeGen shortly.
llvm-svn: 140659
2011-09-27 23:50:46 +00:00
e3e36f80f5
Unbreak CMake build.
...
llvm-svn: 140655
2011-09-27 23:29:59 +00:00
f9b71a2e01
Implement TII::get/setExecutionDomain() for ARM.
...
llvm-svn: 140653
2011-09-27 22:57:21 +00:00
b48c994cc0
Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo.
...
I am going to unify the SSEDomainFix and NEONMoveFix passes into a
single target independent pass. They are essentially doing the same
thing.
llvm-svn: 140652
2011-09-27 22:57:18 +00:00
c63af1b7b6
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
...
Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
llvm-svn: 140647
2011-09-27 22:18:54 +00:00
354ff9e348
This is the start of the new SjLj EH preparation pass, which will replace the
...
current IR-level pass.
The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).
Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.
llvm-svn: 140646
2011-09-27 22:14:12 +00:00
a5d18f2d7e
Embed patterns in definitions of MFC1 and MTC1 instead of defining them outside
...
of the instruction definitions using Pat<>.
llvm-svn: 140644
2011-09-27 22:01:01 +00:00
7a6e8f2c5d
Remove an invalid assert that is really just asserting when the scheduler emits
...
a suboptimal schedule.
llvm-svn: 140643
2011-09-27 21:59:16 +00:00
6a2eb5c1c8
test/CMakeLists.txt: Depend on llvm-objdump. "make check" is expected to resolve test-dependent targets on CMake build.
...
llvm-svn: 140641
2011-09-27 21:54:50 +00:00
af136f71ec
Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().
...
Naming conventions consistency. No functional change.
llvm-svn: 140636
2011-09-27 20:59:33 +00:00
547b6c5ecd
Stop emitting instructions with the name "tmp" they eat up memory and have to be uniqued, without any benefit.
...
If someone prefers %tmp42 to %42, run instnamer.
llvm-svn: 140634
2011-09-27 20:39:19 +00:00
b762df5840
Remove incorrect passage.
...
llvm-svn: 140631
2011-09-27 20:16:57 +00:00
bf415251df
These symbols appear to be visible by SearchForAddressOfSymbol and no longer
...
require special case handling.
rdar://10117377
llvm-svn: 140629
2011-09-27 20:01:41 +00:00
2bc774ac1a
Add binary archive support to llvm-nm.
...
llvm-svn: 140627
2011-09-27 19:37:18 +00:00
d3b7b12618
Object: Add archive support.
...
llvm-svn: 140626
2011-09-27 19:36:55 +00:00
68ba81346e
Check that catch clauses have pointer type.
...
llvm-svn: 140625
2011-09-27 19:34:22 +00:00
4f7054e56e
PTX: Fix case where printed alignment could be 0
...
llvm-svn: 140624
2011-09-27 19:25:49 +00:00
554a012eb5
Unbreak tests.
...
llvm-svn: 140622
2011-09-27 19:06:37 +00:00
d9f23c4f6b
Add FCA to the lexicon.
...
llvm-svn: 140619
2011-09-27 18:44:01 +00:00
e074593498
PTX: Use external symbols to keep track of params and locals. This also fixes
...
a couple of outstanding issues with frame objects occuring as instruction
operands.
llvm-svn: 140616
2011-09-27 18:12:55 +00:00
1c7597693c
Use existing function.
...
llvm-svn: 140615
2011-09-27 17:55:08 +00:00
e41b1d59f0
Fix function MipsRegisterInfo::getRegisterNumbering.
...
Return numbers of 64-bit registers.
llvm-svn: 140609
2011-09-27 17:15:27 +00:00
ff5d0965b0
Do not add the pass that restores $gp if target is Mips64.
...
llvm-svn: 140607
2011-09-27 16:58:43 +00:00
86de1a666d
Have the verifier check that all landingpad operands are constants.
...
llvm-svn: 140606
2011-09-27 16:43:19 +00:00
38b3b83362
Cleanup PromoteIntOp_EXTRACT_VECTOR_ELT and PromoteIntRes_SETCC.
...
Add a new method: getAnyExtOrTrunc and use it to replace the manual check.
llvm-svn: 140603
2011-09-27 11:16:47 +00:00
1b857d2762
Revert r140463; The patch assumes that <4 x i1> is saved to memory as 4 x i8,
...
while the decision is to bit-pack small values.
llvm-svn: 140601
2011-09-27 10:48:29 +00:00
614c8e5146
Remove some not-really-correct wording.
...
llvm-svn: 140600
2011-09-27 10:37:28 +00:00
bb050745e7
Mark MipsPseudo isPseudo.
...
llvm-svn: 140598
2011-09-27 04:57:54 +00:00
9f01f89386
PTX: Add support for sitofp in backend
...
llvm-svn: 140593
2011-09-27 01:04:47 +00:00
90f90da156
Split the landing pad basic block with the correct function. Also merge the
...
split landingpad instructions into a PHI node.
PR11016
llvm-svn: 140592
2011-09-27 00:59:31 +00:00
581243919d
Disable LSR retry by default.
...
Disabling aggressive LSR saves compilation time, and with the new
indvars behavior usually improves performance.
llvm-svn: 140590
2011-09-27 00:44:14 +00:00
f6fbfd3f83
Last batch of test conversions to new atomic instructions.
...
llvm-svn: 140585
2011-09-27 00:17:29 +00:00
8868faec63
LSR, one of the new Cost::isLoser() checks did not get merged in the previous checkin.
...
llvm-svn: 140583
2011-09-26 23:35:25 +00:00
a486cb972f
Convert a bunch more tests over to the new atomic instructions.
...
llvm-svn: 140582
2011-09-26 23:15:09 +00:00
b1a9f65487
Remove extraneous commit garbage.
...
llvm-svn: 140581
2011-09-26 23:14:02 +00:00
784729d408
LSR cost metric minor fix and verification.
...
The minor bug heuristic was noticed by inspection. I added the
isLoser/isValid helpers because they will become more
important with subsequent checkins.
llvm-svn: 140580
2011-09-26 23:11:04 +00:00
287d6ef088
Fix an incorrect decoder test.
...
llvm-svn: 140579
2011-09-26 23:08:34 +00:00
02bb7573fb
Remove old hack for compiling with gcc-4.0.
...
llvm-svn: 140573
2011-09-26 22:30:57 +00:00
d20cd25c69
Remove incorrect testcases.
...
llvm-svn: 140572
2011-09-26 22:13:55 +00:00
a6a9c20c23
Set register class of a register according to value of HasMips64.
...
llvm-svn: 140570
2011-09-26 21:55:17 +00:00
7b502920ef
Define variable HasMips64 in MipsTargetLowering.
...
llvm-svn: 140569
2011-09-26 21:47:02 +00:00
e5ce709022
In single float mode, double precision FP arguments are passed in integer
...
registers, so there is no need to check here.
llvm-svn: 140568
2011-09-26 21:37:50 +00:00
ab7b99ab9c
Convert more tests to new atomic instructions.
...
llvm-svn: 140567
2011-09-26 21:36:10 +00:00
6fb0c1e474
Convert more tests over to the new atomic instructions.
...
I did not convert Atomics-32.ll and Atomics-64.ll by hand; the diff is autoupgrade output.
The wmb test is gone because there isn't any way to express wmb with the new atomic instructions; if someone really needs a non-asm way to write a wmb on Alpha, a platform-specific intrisic could be added.
llvm-svn: 140566
2011-09-26 21:30:17 +00:00
878a67397d
Fix grammar.
...
llvm-svn: 140564
2011-09-26 21:10:31 +00:00
dec0ee3237
Remove dead table entry.
...
llvm-svn: 140563
2011-09-26 21:08:28 +00:00
58c80f886c
Some minor (and more involved) cleanups. No real context changes.
...
llvm-svn: 140561
2011-09-26 21:06:33 +00:00
f01e2de5e6
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
...
llvm-svn: 140560
2011-09-26 21:06:22 +00:00
c064f2c33e
Convert more tests over to the new atomic instructions.
...
llvm-svn: 140559
2011-09-26 20:27:49 +00:00
bda9e7af58
Upgrade a couple more tests to the new atomic instructions.
...
llvm-svn: 140558
2011-09-26 20:15:56 +00:00
5c91891cf3
Enhance alias analysis for atomic instructions a bit. Upgrade a couple alias-analysis tests to the new atomic instructions.
...
llvm-svn: 140557
2011-09-26 20:15:28 +00:00
da2919dbd8
PTX: Fix memcpy intrinsic to handle 64-bit pointers
...
llvm-svn: 140556
2011-09-26 19:19:48 +00:00
67d33b3bf2
Fix this test so it doesn't fail on Mac.
...
llvm-svn: 140553
2011-09-26 19:13:47 +00:00
b40da7f956
PTX: Implement PTXSelectionDAGInfo
...
llvm-svn: 140549
2011-09-26 18:57:27 +00:00
c3edaddfea
PTX: Implement ISD::ANY_EXTEND
...
llvm-svn: 140548
2011-09-26 18:57:24 +00:00
1395cf8423
PTX: Fix detection of stack load/store vs. global load/store, as well as fix the
...
printing of local offsets
llvm-svn: 140547
2011-09-26 18:57:22 +00:00
0ceb8cadd2
Fix emission of debug data for global variables. getContext() on DIGlobalVariables is not valid any more.
...
llvm-svn: 140539
2011-09-26 17:40:42 +00:00
55f340eb62
PTX: Add .align tests to stack object test file
...
llvm-svn: 140537
2011-09-26 16:20:38 +00:00
f8dd701bf9
PTX: SM > 2.0 implies +double
...
llvm-svn: 140536
2011-09-26 16:20:36 +00:00
14defde057
PTX: Fix some lingering issues with stack allocation
...
llvm-svn: 140535
2011-09-26 16:20:34 +00:00
37fd87675f
PTX: Split up the TableGen instruction definitions into logical units
...
llvm-svn: 140534
2011-09-26 16:20:31 +00:00
d40f5ababf
PTX: Unify handling of loads/stores
...
llvm-svn: 140533
2011-09-26 16:20:28 +00:00
Che-Liang Chiou