b58a9665bd
Change C++ style comments to C style comments in X86 disassembler. Patch from Joe Abbey.
...
llvm-svn: 141162
2011-10-05 03:29:32 +00:00
3a86ba767c
Avoid exponential recursion in SCEV getConstantEvolvingPHI and EvaluateExpression.
...
Note to compiler writers: never recurse on multiple instruction
operands without memoization.
Fixes rdar://10187945. Was taking 45s, now taking 5ms.
llvm-svn: 141161
2011-10-05 03:25:31 +00:00
02e760add3
Insert space.
...
llvm-svn: 141158
2011-10-05 02:22:49 +00:00
8e532eb92f
Do not examine variadic or implicit operands if instruction is a return (jr).
...
llvm-svn: 141157
2011-10-05 02:21:58 +00:00
0d7dfc0b1f
Clean up function Filler::delayHasHazard.
...
llvm-svn: 141156
2011-10-05 02:18:58 +00:00
7b204688e7
Remove function Filler::insertCallUses.
...
Record the registers used and defined by a call in Filler::insertDefsUses.
llvm-svn: 141154
2011-10-05 02:04:17 +00:00
d9c8aab894
Clean up Filler::findDelayInstr.
...
llvm-svn: 141152
2011-10-05 01:57:46 +00:00
e7b0697412
Remove function Filler::isDelayFiller. Check if I is the same instruction that
...
filled the last delay slot visited.
llvm-svn: 141151
2011-10-05 01:30:09 +00:00
5d4e4ea3d5
Clean up Filler::runOnMachineBasicBlock. Change interface of
...
Filler::findDelayInstr.
llvm-svn: 141150
2011-10-05 01:23:39 +00:00
9e6034444a
Define a statistic for the number of slots that were filled with useful
...
instructions (instructions that are not NOP).
llvm-svn: 141149
2011-10-05 01:19:13 +00:00
8b3666af1b
Remove unnecessary check. isDelayFiller(MBB, I) will evaluate to true before
...
I->getDesc().hasDelaySlot() does.
llvm-svn: 141148
2011-10-05 01:15:31 +00:00
7d398636a2
Add comments and move assignment statement. If sawStore is true, sawLoad does
...
not have to be set.
llvm-svn: 141147
2011-10-05 01:09:37 +00:00
b345b5c424
Correct description string of enable-mips-delay-filler.
...
llvm-svn: 141146
2011-10-05 01:06:57 +00:00
324be98a3c
Look at the number of entries in the jump table and jump to a 'trap' block if
...
the value exceeds that number.
llvm-svn: 141143
2011-10-05 00:39:32 +00:00
3a541b046a
Add TRI::getSubClassWithSubReg(RC, Idx) function.
...
This function is used to constrain a register class to a sub-class that
supports the given sub-register index.
For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD.
The function will be used to compute register classes when emitting
INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation
of sub-register operations.
The version provided by TableGen is usually adequate, but targets can
override.
llvm-svn: 141142
2011-10-05 00:35:49 +00:00
202803e39c
Checkpoint for SJLJ EH code.
...
This is a first pass at generating the jump table for the sjlj dispatch. It
currently generates something plausible, but hasn't been tested thoroughly.
llvm-svn: 141140
2011-10-05 00:02:33 +00:00
d5d39bb098
Also add <imp-use,kill> flags for redefined super-registers.
...
For example:
%vreg10:dsub_0<def,undef> = COPY %vreg1
%vreg10:dsub_1<def> = COPY %vreg2
is rewritten as:
%D2<def> = COPY %D0, %Q1<imp-def>
%D3<def> = COPY %D1, %Q1<imp-use,kill>, %Q1<imp-def>
The first COPY doesn't care about the previous value of %Q1, so it
doesn't read that register.
The second COPY is a partial redefinition of %Q1, so it implicitly kills
and redefines that register.
This makes it possible to recognize instructions that can harmlessly
clobber the full super-register. The write and don't read the
super-register.
llvm-svn: 141139
2011-10-05 00:01:48 +00:00
9d5bda9be1
Also add <def,undef> flags when coalescing sub-registers.
...
RegisterCoalescer can create sub-register defs when it is joining a
register with a sub-register. Add <undef> flags to these new
sub-register defs where appropriate.
llvm-svn: 141138
2011-10-05 00:01:46 +00:00
0ca562ec4c
Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
...
llvm-svn: 141135
2011-10-04 23:26:17 +00:00
5dcda64338
Adding back support for printing operands symbolically to ARM's new disassembler
...
using llvm's public 'C' disassembler API now including annotations.
Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
llvm-svn: 141129
2011-10-04 22:44:48 +00:00
3d11aa7e75
Create a mapping between the landing pad basic block and the call site index for later use.
...
llvm-svn: 141125
2011-10-04 22:00:35 +00:00
10f2de3261
Allow <undef> flags on def operands as well as uses.
...
The <undef> flag says that a MachineOperand doesn't read its register,
or doesn't depend on the previous value of its register.
A full register def never depends on the previous register value. A
partial register def may depend on the previous value if it is intended
to update part of a register.
For example:
%vreg10:dsub_0<def,undef> = COPY %vreg1
%vreg10:dsub_1<def> = COPY %vreg2
The first copy instruction defines the full %vreg10 register with the
bits not covered by dsub_0 defined as <undef>. It is not considered a
read of %vreg10.
The second copy modifies part of %vreg10 while preserving the rest. It
has an implicit read of %vreg10.
This patch adds a MachineOperand::readsReg() method to determine if an
operand reads its register.
Previously, this was modelled by adding a full-register <imp-def>
operand to the instruction. This approach makes it possible to
determine directly from a MachineOperand if it reads its register. No
scanning of MI operands is required.
llvm-svn: 141124
2011-10-04 21:49:33 +00:00
28a0bc5562
Tidy up formatting.
...
llvm-svn: 141123
2011-10-04 21:43:51 +00:00
0f7efaf956
Doxygen-ize comments. No functionality change.
...
llvm-svn: 141122
2011-10-04 21:25:01 +00:00
4dfad843e3
Remove unused web page.
...
llvm-svn: 141118
2011-10-04 21:17:19 +00:00
4879f70ab9
Un-XFAIL file. Comment out individual failing instructions.
...
llvm-svn: 141117
2011-10-04 21:16:42 +00:00
aec9739e16
Replace snprintf with raw_string_ostream.
...
llvm-svn: 141116
2011-10-04 21:08:56 +00:00
f3e1fc3f86
Tidy up formatting.
...
llvm-svn: 141115
2011-10-04 20:52:57 +00:00
8a829e8ecb
Un-XFAIL file. Fix incorrect CHECK lines. General format cleanup.
...
llvm-svn: 141114
2011-10-04 20:50:05 +00:00
8bc8bfdcad
Un-XFAIL file. Fix incorrect CHECK line. General format cleanup.
...
llvm-svn: 141113
2011-10-04 20:46:49 +00:00
610aa62edc
Tidy up formatting.
...
llvm-svn: 141111
2011-10-04 20:42:35 +00:00
388c0f61e8
Un-XFAIL file. Fix incorrect CHECK line.
...
llvm-svn: 141110
2011-10-04 20:42:09 +00:00
2644375abe
Un-XFAIL the file. Disable only the individual tests that aren't working yet.
...
llvm-svn: 141108
2011-10-04 20:34:11 +00:00
c56fe5e9bb
Add method to determine if a begin label has a call site number associated with it.
...
llvm-svn: 141107
2011-10-04 20:31:56 +00:00
b1147c4660
Properly use const_iterator.
...
This should unbreak the Windows build.
llvm-svn: 141105
2011-10-04 20:18:39 +00:00
0a2fd00de5
Update cmake list.
...
llvm-svn: 141104
2011-10-04 19:38:16 +00:00
b24263ec49
Tell people using the tutorial how to make it actually work.
...
llvm-svn: 141103
2011-10-04 19:36:30 +00:00
979697b630
Test Operand Arguments
...
Add a test to do list manipulation and pass the result as arguments.
This tests the new list element operator resolve code and provides an
example of using list manipulation to do instruction pattern
substitution.
llvm-svn: 141102
2011-10-04 18:55:40 +00:00
a8b8ab6b20
Allow Operator Arguments
...
When resolving an operator list element reference, resolve all
operator operands and try to fold the operator first. This allows the
operator to collapse to a list which may then be indexed.
Before, it was not possible to do this:
class D<int a, int b> { ... }
class C<list<int> A> : D<A[0], A[1]>;
class B<list<int> b> : C<!foreach(...,b)>;
Now it is.
llvm-svn: 141101
2011-10-04 18:55:36 +00:00
83e84faa8f
Un-XFAIL the file. Disable only the individual tests that aren't working yet.
...
llvm-svn: 141099
2011-10-04 18:43:15 +00:00
539f7b0493
Unbreak CMake build.
...
llvm-svn: 141097
2011-10-04 18:22:24 +00:00
2d9eb707af
Tidy up. Formatting.
...
llvm-svn: 141096
2011-10-04 17:49:45 +00:00
8dfb65516b
Put GCOVFile and other related interface in a common header so that llvm-cov tool can share it with GCOV writer.
...
llvm-svn: 141095
2011-10-04 17:24:48 +00:00
b26b49ca63
Unbreak MSVC build.
...
llvm-svn: 141093
2011-10-04 16:28:07 +00:00
41090ed753
Fix PR9833/PR11054 (patch provided by Patrik Hägglund)
...
llvm-svn: 141092
2011-10-04 16:26:41 +00:00
03efe84d0a
Teach TableGen to infer missing register classes.
...
The set of register classes should be closed under sub-register
operations and intersections. That will allow the register allocator to
model combinations of constraints accurately.
This patch implements the easiest form of register class inference: For
every register class, and for every sub-register SubIdx, the subset of
registers in RC that have a SubIdx sub-register should also be a register
class.
This does create some new register classes for the targets in the tree:
ARM gets a new QQQQPR_with_ssub_0. This class was omitted from the .td
file on purpose because it only has two registers. InstrEmitter and
RegisterCoalescer have safeguards against selecting too small register
classes, so it is harmless.
PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32
sub-register of LR8. I think that might be an omission?
X86 puts RIP in the GR64 class, and since that register doesn't have
8-bit sub-registers, we get:
GR64_with_sub_8bit
GR64_TC_with_sub_8bit
GR64_NOREX_with_sub_8bit
GR64_TC_with_sub_8bit_hi
The various CodeGen classes have already been fixed so adding new
register classes should not affect compile time.
llvm-svn: 141084
2011-10-04 15:28:49 +00:00
e25602696e
Teach PPCInstrInfo to handle sub-classes.
...
This has already been done for most other targets.
llvm-svn: 141083
2011-10-04 15:28:47 +00:00
331534e5bb
TableGen: Store all allocation orders together.
...
There is no need to keep the primary order separate.
llvm-svn: 141082
2011-10-04 15:28:44 +00:00
bd92dc608d
TableGen: Privatize CodeGenRegisterClass::TheDef and Name.
...
When TableGen starts creating its own register classes, the synthesized
classes won't have a Record reference. All register classes must have a
name, though.
llvm-svn: 141081
2011-10-04 15:28:08 +00:00
54dd16240c
TableGen: Don't add synthetic Records to the RecordKeeper.
...
The RecordKeeper could be shared by multiple target instances, causing
duplicate record errors.
llvm-svn: 141080
2011-10-04 15:27:53 +00:00
67a16e2564
tblgen: add preprocessor as a separate mode
...
This patch adds a preprocessor that can expand nested for-loops for
saving some copy-n-paste in *.td files.
The preprocessor is not yet integrated with TGParser, and so it has
no direct effect on *.td inputs. However, you may preprocess an td
input (and only preprocess it).
To test the proprecessor, type:
tblgen -E -o $@ $<
llvm-svn: 141079
2011-10-04 15:14:51 +00:00
3b309efe38
Set operation actions to legal types only.
...
llvm-svn: 141075
2011-10-04 12:05:35 +00:00
04001625e4
Operations should be custom lowered only if their type is legal.
...
Test: CellSPU/v2i32.ll when running with -promote-elements
llvm-svn: 141074
2011-10-04 10:03:32 +00:00
287682ead1
The product of two chrec's can always be represented as a chrec.
...
llvm-svn: 141066
2011-10-04 06:51:26 +00:00
f18c896337
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
...
llvm-svn: 141065
2011-10-04 06:30:42 +00:00
8de329a9fc
LSR should avoid redundant edge splitting.
...
This handles the case in which LSR rewrites an IV user that is a phi and
splits critical edges originating from a switch.
Fixes <rdar://problem/6453893> LSR is not splitting edges "nicely"
llvm-svn: 141059
2011-10-04 03:50:44 +00:00
411842f98f
whitespace
...
llvm-svn: 141058
2011-10-04 03:34:49 +00:00
74e5a2a712
Remove last references to hotpatch.
...
llvm-svn: 141057
2011-10-04 03:08:43 +00:00
b3334f9f43
Exclude libLLVMTableGen.a from the shared library
...
Unbreaks tools for --enable-shared build.
llvm-svn: 141052
2011-10-04 00:30:34 +00:00
ac3fb4c078
Generic cleanup.
...
llvm-svn: 141050
2011-10-04 00:16:40 +00:00
bf51f97c28
Unit test for r140919, loop unroll heuristics.
...
llvm-svn: 141049
2011-10-04 00:07:02 +00:00
b85400aa58
Tidy up. These tests are covered in the .s file tests now.
...
llvm-svn: 141047
2011-10-03 23:40:13 +00:00
e7fbce7acb
ARM assembly parsing and encoding for VMOV immediate.
...
llvm-svn: 141046
2011-10-03 23:38:36 +00:00
69e6f90eb2
Tidy up. 80 columns.
...
llvm-svn: 141043
2011-10-03 23:03:26 +00:00
1eab54f8ba
Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it.
...
llvm-svn: 141042
2011-10-03 22:44:15 +00:00
97a8695fff
Don't carry over the dispatchsetup hack from the old system.
...
llvm-svn: 141040
2011-10-03 22:42:40 +00:00
46b6646059
ARM parsing/encoding for VCMP/VCMPE.
...
llvm-svn: 141038
2011-10-03 22:30:24 +00:00
f66daac2f5
Fix typo in comments.
...
llvm-svn: 141032
2011-10-03 21:30:08 +00:00
374ee194f2
Check-pointing the new SjLj EH lowering.
...
This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.
llvm-svn: 141031
2011-10-03 21:25:38 +00:00
6c71ef32be
Move CHECK after entry label.
...
llvm-svn: 141030
2011-10-03 21:24:30 +00:00
c3a6357ee3
Add support for 64-bit logical NOR.
...
llvm-svn: 141029
2011-10-03 21:23:18 +00:00
48a72ca0cb
Add support for 64-bit count leading ones and zeros instructions.
...
llvm-svn: 141028
2011-10-03 21:16:50 +00:00
6f3e73d6ad
Move the grabbing of the jump buffer into the caller function, eliminating the need for returning a std::pair.
...
llvm-svn: 141026
2011-10-03 21:15:28 +00:00
4ab23b5273
ARM assembly parsing and encoding for VMRS/FMSTAT.
...
llvm-svn: 141025
2011-10-03 21:12:43 +00:00
b1538f91dc
Add support for 64-bit divide instructions.
...
llvm-svn: 141024
2011-10-03 21:06:13 +00:00
dbebc6f3f9
Add C api for Instruction->eraseFromParent().
...
llvm-svn: 141023
2011-10-03 20:59:18 +00:00
c3fc62b492
Update test for 141010.
...
llvm-svn: 141022
2011-10-03 20:58:08 +00:00
5dd3425b77
Thumb2 ADD/SUB can take SP as a destination register.
...
It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.
llvm-svn: 141020
2011-10-03 20:51:59 +00:00
3caf8cb310
Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integer
...
registers.
llvm-svn: 141019
2011-10-03 20:38:08 +00:00
a279d9bd6a
Add support for 64-bit integer multiply instructions.
...
llvm-svn: 141017
2011-10-03 20:01:11 +00:00
cdcc74563c
Add definitions of instructions which move values between 64-bit integer
...
registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.
llvm-svn: 141015
2011-10-03 19:28:44 +00:00
7f6f12405d
Find the strip tool that works with the specified SDKROOT. rdar://10165908
...
llvm-svn: 141013
2011-10-03 18:48:16 +00:00
b817655b77
Tidy up a bit. Formatting.
...
llvm-svn: 141010
2011-10-03 17:59:31 +00:00
786bdb9e14
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
...
llvm-svn: 141007
2011-10-03 17:28:23 +00:00
cead033ced
Whitespace.
...
llvm-svn: 141005
2011-10-03 15:49:20 +00:00
f84354bfb1
Typo.
...
llvm-svn: 141004
2011-10-03 15:49:16 +00:00
cc349c8dd8
Add the returns_twice attribute to LLVM.
...
llvm-svn: 141001
2011-10-03 14:45:37 +00:00
0d0be47d03
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.
...
llvm-svn: 140997
2011-10-03 08:14:29 +00:00
285bc34089
Test updates that were supposed to go with r140993.
...
llvm-svn: 140994
2011-10-03 07:53:59 +00:00
31854ba017
Fix VEX disassembling to ignore REX.RXBW bits in 32-bit mode.
...
llvm-svn: 140993
2011-10-03 07:51:09 +00:00
3155552461
Reapply r140979 with fix! We never did get a testcase, but careful review of the
...
logic by David Meyer revealed this bug.
llvm-svn: 140992
2011-10-03 07:10:45 +00:00
0038e0632c
attempt to fix ocaml bindings: landing pads
...
llvm-svn: 140991
2011-10-03 06:41:46 +00:00
b1dbce1406
Revert r140979 due to reports of bootstrap failure.
...
llvm-svn: 140980
2011-10-03 05:14:59 +00:00
3c624b8d0d
Add one more case we compute a max trip count.
...
llvm-svn: 140979
2011-10-03 01:03:57 +00:00
7aea69d949
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
...
llvm-svn: 140974
2011-10-02 21:08:12 +00:00
21c33657d6
Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344.
...
llvm-svn: 140971
2011-10-02 16:56:09 +00:00
99fb091f65
Add a new icmp+select optz'n. Also shows off the load(cst) folding added in
...
r140966.
llvm-svn: 140969
2011-10-02 10:37:37 +00:00
40a34dd9a3
Enhance a couple places where we were doing constant folding of instructions,
...
but not load instructions. Noticed by inspection.
llvm-svn: 140966
2011-10-02 09:12:55 +00:00
56ff34f7c5
Fix typo in r140954.
...
llvm-svn: 140962
2011-10-02 04:54:26 +00:00
539801f8bc
Make canonicalization of ImmutableSetRef::asImmutableSet() semi-explicit.
...
llvm-svn: 140959
2011-10-02 01:47:07 +00:00
d07a59f288
Fix disassembling of INVEPT and INVVPID to take operands
...
llvm-svn: 140955
2011-10-01 21:20:14 +00:00
88cb33e0d4
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
...
llvm-svn: 140954
2011-10-01 19:54:56 +00:00
a88cb23da7
Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."
...
to appease nightly testers. Not quite there yet.
llvm-svn: 140953
2011-10-01 19:30:36 +00:00
52e8ed9214
Moved type construction out of the loop and added an assert on the legality of the type. Formatted lines to the 80 char limit.
...
llvm-svn: 140952
2011-10-01 18:39:28 +00:00
84c287e33c
Move TableGen's parser and entry point into a library
...
This is the first step towards splitting LLVM and Clang's tblgen executables.
llvm-svn: 140951
2011-10-01 16:41:13 +00:00
d072b73d78
No one should be using the method directly. Assert if they do.
...
llvm-svn: 140947
2011-10-01 12:47:34 +00:00
f977ff5fb5
Add a convenience method to tell if two things are equal.
...
llvm-svn: 140946
2011-10-01 12:44:28 +00:00
4a4772fae2
Use the ARMConstantPoolMBB class to handle the MBB values.
...
llvm-svn: 140943
2011-10-01 09:30:42 +00:00
6dbc9fe82b
Add ARMConstantPoolMBB to hold an MBB value in the constant pool.
...
llvm-svn: 140942
2011-10-01 09:19:10 +00:00
c5a86069ca
Remove dead code.
...
llvm-svn: 140941
2011-10-01 09:05:12 +00:00
9ff05f740f
Remove now dead methods and ivar.
...
llvm-svn: 140940
2011-10-01 09:04:18 +00:00
c214cb055d
Use the new ARMConstantPoolSymbol class to handle external symbols.
...
llvm-svn: 140939
2011-10-01 08:58:29 +00:00
d7fa016720
Add an ARMConstantPool class for external symbols. This will split out the support for external symbols from the base class.
...
llvm-svn: 140938
2011-10-01 08:36:59 +00:00
d115c4d300
Remove now dead methods and ivar from ARMConstantPoolValue.
...
llvm-svn: 140937
2011-10-01 08:02:05 +00:00
7753d66468
Switch over to using ARMConstantPoolConstant for global variables, functions,
...
and block addresses.
llvm-svn: 140936
2011-10-01 08:00:54 +00:00
f117a35de0
Some more refactoring.
...
* Add a couple of Create methods to the ARMConstantPoolConstant class,
* Add its own version of getExistingMachineCPValue, and
* Modify hasSameValue to return false if the object isn't an ARMConstantPoolConstant.
llvm-svn: 140935
2011-10-01 07:52:37 +00:00
6722556380
Add a Create method that accepts 'kind' and 'pcadj' arguments.
...
llvm-svn: 140934
2011-10-01 06:44:24 +00:00
396c211ae1
Refactoring: Separate out the ARM constant pool Constant from the ARM constant
...
pool value.
It's not used right now, but will be soon.
llvm-svn: 140933
2011-10-01 06:40:33 +00:00
ce29158bc4
Subtarget getFeatureBits() returns a uint64_t, not unsigned.
...
llvm-svn: 140928
2011-10-01 02:47:54 +00:00
21360a4949
Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact
...
useful if an optimization assumes the stack has been realigned. Credit to
Eli for his assistance.
rdar://10043857
llvm-svn: 140924
2011-10-01 02:03:18 +00:00
f7656015fc
Inlining and unrolling heuristics should be aware of free truncs.
...
We want heuristics to be based on accurate data, but more importantly
we don't want llvm to behave randomly. A benign trunc inserted by an
upstream pass should not cause a wild swings in optimization
level. See PR11034. It's a general problem with threshold-based
heuristics, but we can make it less bad.
llvm-svn: 140919
2011-10-01 01:39:05 +00:00
caa500bf93
whitespace
...
llvm-svn: 140916
2011-10-01 01:27:56 +00:00
44a36c872e
Add Windows x64 stack walking support. Patch by Aaron Ballman!
...
llvm-svn: 140906
2011-10-01 00:05:20 +00:00
6417395d67
Use precomputed BitVector for CodeGenRegisterClass::hasSubClass().
...
All the sub-class bit vectors are computed when first creating the
register bank.
llvm-svn: 140905
2011-09-30 23:47:05 +00:00
b34639de75
Filecheck-ize.
...
llvm-svn: 140904
2011-09-30 23:40:29 +00:00
24b6b8d16a
Add new line at end of file.
...
llvm-svn: 140903
2011-09-30 23:21:11 +00:00
9925f197cc
When inferring the pointer alignment, if the global doesn't have an initializer
...
and the alignment is 0 (i.e., it's defined globally in one file and declared in
another file) it could get an alignment which is larger than the ABI allows for
that type, resulting in aligned moves being used for unaligned loads.
For instance, in file A.c:
struct S s;
In file B.c:
struct {
// something long
};
extern S s;
void foo() {
struct S p = s;
// ...
}
this copy is a 'memcpy' which is turned into a series of 'movaps' instructions
on X86. But this is wrong, because 'struct S' has alignment of 4, not 16.
llvm-svn: 140902
2011-09-30 23:19:55 +00:00
f40df1d46c
Promote comment to doxycomment. Adjust whitespace. No functionality change.
...
llvm-svn: 140899
2011-09-30 22:19:53 +00:00
237dceff90
Store sub-class lists as a bit vector.
...
This uses less memory and it reduces the complexity of sub-class
operations:
- hasSubClassEq() and friends become O(1) instead of O(N).
- getCommonSubClass() becomes O(N) instead of O(N^2).
In the future, TableGen will infer register classes. This makes it
cheap to add them.
llvm-svn: 140898
2011-09-30 22:19:07 +00:00
8153f6c39f
Extract a slightly more general BitVector printer.
...
This one can also print 32-bit groups.
llvm-svn: 140897
2011-09-30 22:18:54 +00:00
1352be2bd3
Move getCommonSubClass() into TRI.
...
It will soon need the context.
llvm-svn: 140896
2011-09-30 22:18:51 +00:00
b15fad9df4
Compute lists of super-classes in CodeGenRegisterClass.
...
Use these lists instead of computing them on the fly in
RegisterInfoEmitter.
llvm-svn: 140895
2011-09-30 22:18:45 +00:00
d76f43e18c
Correct for my over-eager delete finger.
...
llvm-svn: 140892
2011-09-30 22:02:45 +00:00
e67a10d54d
Add definition of MipsELFObjectWriter.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140891
2011-09-30 21:55:40 +00:00
ee09394644
Register the MC object streamer.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140887
2011-09-30 21:29:38 +00:00
44220ca045
Register Asm backend. Add functions to MipsAsmBackend.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140886
2011-09-30 21:23:45 +00:00
587fe6cd52
Add MCELFObjectTargetWriter and MCAsmBackend classes.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140885
2011-09-30 21:04:02 +00:00
dc221dd649
Test More Complicated Lists
...
Test of indexing lists of lists of lists works. This also exercises
some operators.
llvm-svn: 140884
2011-09-30 20:59:52 +00:00
0c3a2b48e7
Test VarListElementInit:: resolveListElementReference
...
Add a TableGen test to check if indexing lists of lists works.
llvm-svn: 140883
2011-09-30 20:59:51 +00:00
74ce80f34e
Implement VarListElementInit:: resolveListElementReference
...
Implement VarListElementInit:: resolveListElementReference so that
lists of lists can be indexed.
llvm-svn: 140882
2011-09-30 20:59:49 +00:00
3bad73a900
Update CMake build.
...
llvm-svn: 140879
2011-09-30 20:44:33 +00:00
750ecec7d5
Initial implementation of MipsMCCodeEmitter.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140878
2011-09-30 20:40:03 +00:00
011dafba61
Don't modify constant in-place.
...
llvm-svn: 140875
2011-09-30 19:58:46 +00:00
2f0cbf6a99
Tracing or debug-printing a newly formed instruction should not crash.
...
llvm-svn: 140874
2011-09-30 19:50:40 +00:00
ec4b6e7fe5
whitespace
...
llvm-svn: 140873
2011-09-30 19:48:58 +00:00
1fef284cf9
Remove unnecessary checking of register operands.
...
llvm-svn: 140872
2011-09-30 19:18:24 +00:00
7ba8a8d656
Add definitions of Mips64 rotate instructions.
...
llvm-svn: 140870
2011-09-30 18:51:46 +00:00
24ff834671
float comparison to double 'zero' constant can just be a float 'zero.'
...
InstCombine was incorrectly considering the conversion of the constant
zero to be unsafe.
We want to transform:
define float @bar(float %x) nounwind readnone optsize ssp {
%conv = fpext float %x to double
%cmp = fcmp olt double %conv, 0.000000e+00
%conv1 = zext i1 %cmp to i32
%conv2 = sitofp i32 %conv1 to float
ret float %conv2
}
Into:
define float @bar(float %x) nounwind readnone optsize ssp {
%cmp = fcmp olt float %x, 0.000000e+00 ; <---- This
%conv1 = zext i1 %cmp to i32
%conv2 = sitofp i32 %conv1 to float
ret float %conv2
}
rdar://10215914
llvm-svn: 140869
2011-09-30 18:45:50 +00:00
e8e4dbf468
Constify 'isLSDA' and move a method out-of-line.
...
llvm-svn: 140868
2011-09-30 18:42:06 +00:00
129c52af18
Tidy up. Trailing whitespace.
...
llvm-svn: 140865
2011-09-30 18:09:53 +00:00
4e0dbee62b
ARM Darwin default relocation model is PIC.
...
This matches clang, so default options in llc and friends are now closer to
clang's defaults.
llvm-svn: 140863
2011-09-30 17:41:35 +00:00
9727af7657
isCommutable should be 0 for DSUBu.
...
llvm-svn: 140862
2011-09-30 17:26:36 +00:00
d2222c386c
ARM Fixup valus for movt/movw are for the whole value.
...
Remove an assert that was expecting only the relevant 16bit portion for
the fixup being handled. Also kill some dead code in the T2 portion.
rdar://9653509
llvm-svn: 140861
2011-09-30 17:23:05 +00:00
b381129095
Check values of immediate operands.
...
llvm-svn: 140860
2011-09-30 17:19:21 +00:00
c874e2d8fb
Fix a bug in compare_numeric().
...
Thanks to Alexandru Dura and Jonas Paulsson for finding it.
llvm-svn: 140859
2011-09-30 17:03:55 +00:00
d6c0011d92
Add forgotten tests that the cleanup flag is cleared if there
...
is a catch-all landingpad clause.
llvm-svn: 140858
2011-09-30 17:00:34 +00:00
64b1aad4e3
MCJIT initialization TargetData
...
llvm-svn: 140856
2011-09-30 16:40:10 +00:00
ea3f90ae40
PTX: Various stylistic and code readability changes recommended by Jim Grosbach.
...
llvm-svn: 140855
2011-09-30 14:36:36 +00:00
957a6d5c51
PTX: Add programmable rounding mode specifier for int <-> fp conversion instrs.
...
Also take this opportunity to clean up the rounding mode pass.
llvm-svn: 140854
2011-09-30 13:46:52 +00:00
5c05579f94
Inlining often produces landingpad instructions with repeated
...
catch or repeated filter clauses. Teach instcombine a bunch
of tricks for simplifying landingpad clauses. Currently the
code only recognizes the GNU C++ and Ada personality functions,
but that doesn't stop it doing a bunch of "generic" transforms
which are hopefully fine for any real-world personality function.
If these "generic" transforms turn out not to be generic, they
can always be conditioned on the personality function. Probably
someone should add the ObjC++ personality function. I didn't as
I don't know anything about it.
llvm-svn: 140852
2011-09-30 13:12:16 +00:00
52cac090c4
some 3.0 API notes
...
llvm-svn: 140851
2011-09-30 13:07:52 +00:00
be5020eb95
Comment grammar fixes.
...
thanks to Duncan.
llvm-svn: 140850
2011-09-30 13:07:47 +00:00
3111d11f23
PTX: Attempt to cleanup/unify the handling of FP rounding modes. This requires
...
us to manually provide Pat<> definitions for all FP instruction patterns.
llvm-svn: 140849
2011-09-30 12:54:43 +00:00
319a1415b8
Instead of crashing when MCAsmInfo is NULL, add an assert.
...
This helps with porting code from 2.9 to 3.0 as TargetSelect.h changed location,
and if you include the old one by accident you will trigger this assert.
llvm-svn: 140848
2011-09-30 12:31:57 +00:00
61e256aa69
Mips64 shift instructions.
...
llvm-svn: 140841
2011-09-30 03:18:46 +00:00
7769a77710
Mips64 arithmetic and logical instructions with one source register and
...
immediate.
llvm-svn: 140839
2011-09-30 02:08:54 +00:00
efc761a1eb
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
...
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
llvm-svn: 140834
2011-09-30 00:50:06 +00:00
2c024b2d6a
Precompute a bit vector of register sub-classes.
...
llvm-svn: 140827
2011-09-30 00:10:40 +00:00
c0fc173da0
Order register classes topologically.
...
All register classes are given a lower ID than their sub-classes.
Cliques are ordered alphabetically.
This will be used to simplify some sub-class operations.
llvm-svn: 140826
2011-09-30 00:10:36 +00:00
f2619ee3ff
Fill delay slot with useful instructions. Modified from Sparc's version of delay
...
slot filler.
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140825
2011-09-29 23:52:13 +00:00
69bc3de4fc
Create a machine basic block in the constant pool and retrieve the symbol for an MBB.
...
llvm-svn: 140824
2011-09-29 23:50:42 +00:00
a1127b2fa2
Support creating a constant pool value for a machine basic block.
...
This is used when we want to take the address of a machine basic block, but it's
not associated with a BB in LLVM IR.
llvm-svn: 140823
2011-09-29 23:48:44 +00:00
a3e7ffdae8
Fold two identical set lookups into one. No functionality change.
...
llvm-svn: 140821
2011-09-29 23:40:12 +00:00
19be2ab320
Switch to ArrayRef<CodeGenRegisterClass*>.
...
This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.
llvm-svn: 140816
2011-09-29 22:28:37 +00:00
4ac148dcbc
When eliminating unnecessary retain+autorelease on return values,
...
handle the case where the retain is in a different basic block.
rdar://10210274.
llvm-svn: 140815
2011-09-29 22:27:34 +00:00
2053a5dd64
Don't eliminate objc_retainBlock calls on stack objects if the
...
objc_retainBlock call is potentially responsible for copying
the block to the heap to extend its lifetime. rdar://10209613.
llvm-svn: 140814
2011-09-29 22:25:23 +00:00
3f030ff016
Tidy up. Formatting.
...
llvm-svn: 140810
2011-09-29 21:43:01 +00:00
8574cbfd58
Fix typo.
...
llvm-svn: 140807
2011-09-29 21:07:46 +00:00
36036412e2
Mips64 arithmetic and logical instructions with two source registers.
...
llvm-svn: 140806
2011-09-29 20:37:56 +00:00
95031ed837
Clean up uses of switch instructions so they are not dependent on the operand ordering. Patch by Stepan Dyatkovskiy.
...
llvm-svn: 140803
2011-09-29 20:21:17 +00:00
e5a8f2f9f3
Simplify.
...
llvm-svn: 140789
2011-09-29 17:06:40 +00:00
eec5c5bf6e
Clarify comments.
...
llvm-svn: 140787
2011-09-29 16:52:53 +00:00
1e6ee351fc
Remove unnecessary and unused data member.
...
llvm-svn: 140786
2011-09-29 16:48:44 +00:00
a9e8a2504c
Cosmetic changes, as per Nick's review.
...
llvm-svn: 140785
2011-09-29 16:46:47 +00:00
cac86805bf
Place this bracket according to the LLVM style.
...
llvm-svn: 140784
2011-09-29 16:01:46 +00:00
abcc57669d
PTX: Fix broken shared library build
...
llvm-svn: 140783
2011-09-29 14:25:48 +00:00
dd1904e7a6
Expand the x86 V_SET0* pseudos right after register allocation.
...
This also makes it possible to reduce the number of pseudo instructions
and get rid of the encoding information.
llvm-svn: 140776
2011-09-29 05:10:54 +00:00
15b3c9c684
Target/ARM: Unbreak! CMake! Build!
...
llvm-svn: 140774
2011-09-29 03:32:49 +00:00
bf64024a39
Delete NEONMoveFix, now unused.
...
llvm-svn: 140773
2011-09-29 02:56:45 +00:00
f7ad189033
Use ExecutionDepsFix instead of NEONMoveFix.
...
This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.
llvm-svn: 140772
2011-09-29 02:48:41 +00:00
168dfffdb8
typo + pasto
...
llvm-svn: 140769
2011-09-29 01:53:08 +00:00
463b05a2d0
Remove NumImplicitOps which is now unused.
...
llvm-svn: 140767
2011-09-29 01:47:36 +00:00
bc6de90a5f
LSR: rewrite inner loops only.
...
Rewriting the entire loop nest now requires -enable-lsr-nested.
See PR11035 for some performance data.
A few unit tests specifically test nested LSR, and are now under a flag.
llvm-svn: 140762
2011-09-29 01:33:38 +00:00
37470d5bde
whitespace
...
llvm-svn: 140761
2011-09-29 01:31:48 +00:00
7dc278dc52
Fix build failures better.
...
llvm-svn: 140758
2011-09-29 01:22:31 +00:00
9a6fa7cf3d
Fix build failure.
...
llvm-svn: 140755
2011-09-29 01:14:42 +00:00
a0d5f268a9
Move to ISelLowering.
...
llvm-svn: 140754
2011-09-29 01:13:55 +00:00
fd47d8af8b
PTX: Add new patterns for bitconvert and any_extend
...
llvm-svn: 140753
2011-09-29 01:13:12 +00:00
cc5f8d4517
llvm-size: Apply Chris's code review fixes.
...
This doesn't use formated_raw_ostream because it doesn't support the
functionality needed.
llvm-svn: 140751
2011-09-29 00:59:18 +00:00
d299dccf91
Use the local we already set up.
...
llvm-svn: 140745
2011-09-29 00:50:59 +00:00
Craig Topper