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4 Commits

Author SHA1 Message Date
Jack Carter 2ad73da02b Mips assembler: Explicit floating point condition register recognition. 
This patch allows the assembler to recognize $fcc0 
as a valid register for conditional move instructions. 

Corresponding test cases have been added.

Contributer: Vladimir Medic
llvm-svn: 179567
 2013-04-15 22:21:55 +00:00
Nico Rieck 334c7bc7eb Use object file specific section type for initial text section 
llvm-svn: 179494
 2013-04-14 21:18:36 +00:00
Jack Carter e948ec52d1 Adding support for instructions mfc0, mfc2, mtc0, mtc2 
move from and to coprocessors 0 and 2.

Contributer: Vladimir Medic
llvm-svn: 165351
 2012-10-06 01:17:37 +00:00
Jack Carter a63b16ac1e The Mips standalone assembler fpu instruction support. 
Test cases included

Contributer: Vladimir Medic
llvm-svn: 163363
 2012-09-07 00:23:42 +00:00