122a6304ef
Add disassembly test cases for:
...
A8.6.292 VCMPE
llvm-svn: 128120
2011-03-22 23:08:56 +00:00
30350cdbdf
LDRT and LDRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
...
We now tag them as IndexModePost.
This fixed http://llvm.org/bugs/show_bug.cgi?id=9530 .
llvm-svn: 128113
2011-03-22 22:28:49 +00:00
0cf62f5045
Add one more test case for VFP Load/Store Multiple (vpop).
...
llvm-svn: 128106
2011-03-22 20:21:08 +00:00
230268261b
A8.6.399 VSTM:
...
VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the
MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD
are two instructions. Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm()
to reflect the change.
Also add a test case.
llvm-svn: 128103
2011-03-22 20:00:10 +00:00
1557fd6d39
Write the section table and the section data in the same order that
...
gun as does. This makes it a lot easier to compare the output of both
as the addresses are now a lot closer.
llvm-svn: 127972
2011-03-20 18:44:20 +00:00
0c5f670fe7
Fixed an assert by the ARM disassembler for LDRD_PRE/POST.
...
The relevant instruction table entries were changed sometime ago to no longer take
<Rt2> as an operand. Modify ARMDisassemblerCore.cpp to accomodate the change and
add a test case.
llvm-svn: 127935
2011-03-19 01:16:20 +00:00
1d2f5cebe4
Add support to the ARM asm parser for the register-shifted-register forms of basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA.
...
llvm-svn: 127917
2011-03-18 22:50:18 +00:00
3fbfcc0e1e
Support explicit argument forms for the X86 string instructions.
...
For now, only the default segments are supported.
llvm-svn: 127875
2011-03-18 11:59:40 +00:00
e387f8a5e9
The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset.
...
Remove the offending logic and update the test cases.
llvm-svn: 127843
2011-03-18 00:38:03 +00:00
221a014ea3
It used to be that t_addrmode_s4 was used for both:
...
o A8.6.195 STR (register) -- Encoding T1
o A8.6.193 STR (immediate, Thumb) -- Encoding T1
It has been changed so that now they use different addressing modes
and thus different MC representation (Operand Infos). Modify the
disassembler to reflect the change, and add relevant tests.
llvm-svn: 127833
2011-03-17 22:04:05 +00:00
f1d62cfc8f
MC/Mach-O: Fix regression introduced in r126127, this assignment shouldn't have
...
been removed.
llvm-svn: 127812
2011-03-17 16:25:24 +00:00
07de07eeea
Fix handling of @IDNTPOFF relocations, they need to get STT_TLS.
...
While here, add VK_ARM_TPOFF and VK_ARM_GOTTPOFF, too.
llvm-svn: 127780
2011-03-17 00:35:10 +00:00
a4c3154fca
There were two issues fixed:
...
1. The ARM Darwin *r9 call instructions were pseudo-ized recently.
Modify the ARMDisassemblerCore.cpp file to accomodate the change.
2. The disassembler was unnecessarily adding 8 to the sign-extended imm24:
imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate)
// Encoding A1
It has no business doing such. Removed the offending logic.
Add test cases to arm-tests.txt.
llvm-svn: 127707
2011-03-15 22:27:33 +00:00
f2f4837de3
Basic sanity checks to ensure that 2- and 3-byte
...
VEX prefixes are working for triadic AVX
instructions. This concludes the patch set to
enable AVX support for the X86 disassebler.
llvm-svn: 127647
2011-03-15 01:32:46 +00:00
7a2873dfbe
Fixed an ARM disassembler bug where it does not handle STRi12 correctly because an extra
...
register operand was erroneously added. Remove an incorrect assert which triggers the bug.
rdar://problem/9131529
llvm-svn: 127642
2011-03-15 01:13:17 +00:00
338d362200
Roll r127459 back in:
...
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.
This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.
llvm-svn: 127498
2011-03-11 21:52:04 +00:00
94ccb27b43
Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get
...
created from the", it broke some GCC test suite tests.
llvm-svn: 127477
2011-03-11 19:30:30 +00:00
cc27b3acc4
Optimize trivial branches in CodeGenPrepare, which often get created from the
...
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.
This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.
llvm-svn: 127459
2011-03-11 04:54:27 +00:00
9363d41f14
LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.
...
The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16. Add extra logic to recover from that.
Fixed an assert reported by Sean Callanan
llvm-svn: 127354
2011-03-09 20:01:14 +00:00
5e57137e87
* Correct encoding for VSRI.
...
* Add tests for VSRI and VSLI.
llvm-svn: 127297
2011-03-09 00:33:17 +00:00
a7f303de71
Correct the encoding for VRSRA and VSRA instructions.
...
llvm-svn: 127294
2011-03-09 00:00:35 +00:00
e313f16ad9
* Fix VRSHR and VSHR to have the correct encoding for the immediate.
...
* Update the NEON shift instruction test to expect what 'as' produces.
llvm-svn: 127293
2011-03-08 23:48:09 +00:00
a259686db1
A few more tests for instruction encodings.
...
llvm-svn: 127209
2011-03-08 02:51:48 +00:00
77ad1dc56d
Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
...
expand the testing of the narrowing shift right instructions.
No functionality change.
llvm-svn: 127193
2011-03-07 23:38:41 +00:00
62f759791a
Be nice to Xcore and the XMOS assembler and avoid quoting section names
...
that contain only letters, digits and the characters "_" and ".".
llvm-svn: 127028
2011-03-04 20:03:14 +00:00
5aa4c68eca
Followup to r126970: add 64-bit encoding tests for str with reg operand.
...
llvm-svn: 126987
2011-03-04 04:06:47 +00:00
f63614a982
PR9377: Handle x86 str with register operand in a way consistent with gas.
...
llvm-svn: 126970
2011-03-04 00:10:17 +00:00
852ab890b5
Bug#9033: For the ELF assembler output, always quote the section name.
...
llvm-svn: 126963
2011-03-03 22:31:08 +00:00
d92d17bf67
PR9352: Always emit a relocation for weak symbols. Not emitting relocations
...
for calls to weak symbols with a definition has the appearance of working
with LLVM-generated code because weak symbol definitions are put in their
own sections.
llvm-svn: 126933
2011-03-03 07:24:36 +00:00
6f6d739b6e
TableGen should not ignore BX instructions for the ARM disassembler. pr9368.
...
llvm-svn: 126931
2011-03-03 07:19:52 +00:00
ec84568904
pr9367: Add missing predicated BLX instructions.
...
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.
llvm-svn: 126915
2011-03-03 01:41:01 +00:00
b8b6041734
Fixes an assertion failure while disassembling ARM rsbs reg/reg form.
...
Patch by Ted Kremenek!
llvm-svn: 126895
2011-03-02 23:08:33 +00:00
3b1459b810
Narrow right shifts need to encode their immediates differently from a normal
...
shift.
16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>
llvm-svn: 126723
2011-03-01 01:00:59 +00:00
58775fea6f
Fix the arm's disassembler for blx that was building an MCInst without the
...
needed two predicate operands before the imm operand.
llvm-svn: 126662
2011-02-28 18:46:31 +00:00
78178749e9
split this test into arch specific pieces, so the ARM
...
test isn't run when the arm backend isn't built. This
fixes PR9327
llvm-svn: 126500
2011-02-25 19:06:35 +00:00
afb36fad99
Restore r125595 (reverted in r126336) with modifications:
...
Introduce a variable in the AsmParserExtension whether [] is valid in an
expression. If it is true, parse them like (). Enable this for ELF only.
llvm-svn: 126443
2011-02-24 21:59:22 +00:00
b52040da17
Move arch specific tests in arch specific directories.
...
llvm-svn: 126401
2011-02-24 19:06:27 +00:00
fe4858f269
Remove file. Previous commit deleted content, but left the file around.
...
llvm-svn: 126337
2011-02-23 21:43:31 +00:00
0c03a3a146
Revert r125595, which is an X86-only undocumented assembly syntax extension
...
enabled for all targets. Non-X86 targets should not have this behavior
enabled by default.
Joerg, if you would like to resubmit with the behavior conditionalized to be
X86-ELF only, that's fine.
llvm-svn: 126336
2011-02-23 21:26:51 +00:00
9e18e96264
Put in the symbol table symbols only used in a .globl statement.
...
Fixes PR9292.
llvm-svn: 126330
2011-02-23 20:22:07 +00:00
34770edf43
Fixed a bug in the enhanced disassembler that caused
...
it to ignore valid uses of FS and GS as additional
base registers in address computations. Added a test
case for this.
llvm-svn: 126302
2011-02-23 03:31:28 +00:00
b7e635dcad
Use the same (%dx) hack for in[bwl] as for out[bwl].
...
llvm-svn: 126244
2011-02-22 20:40:09 +00:00
c1b7775e0f
Added a testcase for the enhanced disassembly bug
...
fixed in r126147, where a field in the X86 decode
structure was being read as bits, not bytes.
llvm-svn: 126182
2011-02-22 02:19:18 +00:00
60e7629258
Recognize loopz and loopnz as aliases for loope and loopne.
...
From Dimitry Andric.
llvm-svn: 126168
2011-02-22 00:43:07 +00:00
e39062199e
Implement xgetbv and xsetbv.
...
Patch by Jai Menon.
llvm-svn: 126165
2011-02-22 00:35:18 +00:00
37d5484d18
Handle FK_PCRel_1 and add a test case for this and FK_PCRel_4.
...
llvm-svn: 126157
2011-02-21 23:25:41 +00:00
f849bf81bd
Add some limited support for labels in org directives. Hopefully enough to fix
...
PR9245.
llvm-svn: 126091
2011-02-20 20:20:07 +00:00
47ffd35bea
implement PR9264: disambiguating 'bt mem, imm' as a btl.
...
This is reasonable to do since all bt-mem forms do the
same thing.
llvm-svn: 126047
2011-02-19 21:06:36 +00:00
9cd43977c3
Add assembly parsing support for "msr" and also fix its encoding. Also add
...
testcases for the disassembler to make sure it still works for "msr".
llvm-svn: 125948
2011-02-18 19:45:59 +00:00
f69c80bac2
Recognize monitor/mwait with explicit register arguments
...
llvm-svn: 125805
2011-02-18 00:48:11 +00:00
889a508157
Recognize leavel and leaveq aliases for leave.
...
Validate encoding of leave in 64bit mode.
llvm-svn: 125795
2011-02-17 23:36:39 +00:00
490d02a334
Gas is very inconsistent about when a relaxation/relocation is needed. Do
...
the right thing and stop trying to copy it. Fixes PR8944.
llvm-svn: 125648
2011-02-16 03:25:55 +00:00
58ac6e1677
Add support for pushsection and popsection. Patch by Joerg Sonnenberger.
...
llvm-svn: 125629
2011-02-16 01:08:29 +00:00
4e0f4957bc
Add support for parsing [expr].
...
This is submitted by Joerg Sonnenberger and fixes his PR8685.
llvm-svn: 125595
2011-02-15 20:43:39 +00:00
90d1dfe4c6
Fix encoding and add parsing support for the arm/thumb CPS instruction:
...
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.
llvm-svn: 125489
2011-02-14 13:09:44 +00:00
2406b7d179
Add encodings and mnemonics for FXSAVE64 and FXRSTOR64.
...
These are just FXSAVE and FXRSTOR with REX.W prefixes. These versions use
64-bit pointer values instead of 32-bit pointer values in the memory map they
dump and restore.
llvm-svn: 125446
2011-02-12 23:24:13 +00:00
6e2e29bd11
Do AsmMatcher operand classification per-opcode.
...
When matching operands for a candidate opcode match in the auto-generated
AsmMatcher, check each operand against the expected operand match class.
Previously, operands were classified independently of the opcode being
handled, which led to difficulties when operand match classes were
more complicated than simple subclass relationships.
llvm-svn: 125245
2011-02-10 00:08:28 +00:00
4ebf471c9b
Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being.
...
llvm-svn: 125127
2011-02-08 22:39:40 +00:00
7b7caf51e9
Support for .ifdef / .ifndef in the assembler parser. Patch by Joerg Sonnenberger.
...
llvm-svn: 125120
2011-02-08 22:29:56 +00:00
36dd43fda6
Add support for parsing dmb/dsb instructions
...
llvm-svn: 125055
2011-02-07 22:09:15 +00:00
202630c6ee
Teach ARM/MC/ELF about gcc compatible reloc output to get past odd linkage
...
failures with relocations.
The code committed is a first cut at compatibility for emitted relocations in
ELF .o.
Why do this? because existing ARM tools like emitting relocs symbols as
explicit relocations, not as section-offset relocs.
Result is that with these changes,
1) relocs are now substantially identical what to gcc outputs.
2) larger apps (including many spec2k tests) compile, cross-link, and pass
Added reminder fixme to tests for future conversion to .s form.
llvm-svn: 124996
2011-02-07 01:11:15 +00:00
4761fba833
Teach ARM/MC/ELF about EF_ARM_EABI_VERSION. The magic number is set to
...
5 to match the current doc.
Added FIXME reminder Make it really configurable later.
llvm-svn: 124899
2011-02-04 21:41:11 +00:00
d2e2f56c36
Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.
...
(yes, this is different from R_ARM_CALL)
- Adds a new method getARMBranchTargetOpValue() which handles the
necessary distinction between the conditional and unconditional br/bl
needed for ARM/ELF
At least for ARM mode, the needed fixup for conditional versus unconditional
br/bl is identical, but the ARM docs and existing ARM tools expect this
reloc type...
Added a few FIXME's for future naming fixups in ARMInstrInfo.td
llvm-svn: 124895
2011-02-04 19:47:15 +00:00
2ea68db927
Fix test for non-darwin targets.
...
llvm-svn: 124640
2011-02-01 01:16:18 +00:00
775eec2280
PR9030: Fix disassembly of ARM "mov pc, lr" instruction.
...
Patch by Jyun-Yan You.
llvm-svn: 124492
2011-01-28 17:50:30 +00:00
7e9e290952
Add support for parsing .float
...
llvm-svn: 124485
2011-01-28 14:20:32 +00:00
4ada0d9164
PR8951: Support for .equiv in integrated assembler, patch by Jörg Sonnenberger!
...
llvm-svn: 124467
2011-01-28 03:04:41 +00:00
bb8420a070
Fix PLD encoding.
...
llvm-svn: 124458
2011-01-27 23:48:34 +00:00
ed5efb4053
Add support for specifying register name in cfi-register/offset/def
...
as well as register number.
llvm-svn: 124379
2011-01-27 17:16:37 +00:00
ce0af9c961
Add encoding testcases for ARM vcvtr variations
...
llvm-svn: 124289
2011-01-26 13:53:38 +00:00
178c1e0c9b
fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions
...
llvm-svn: 124288
2011-01-26 13:28:14 +00:00
78c9f78fc9
Jörg Sonnenberger noticed that we were missing this test.
...
llvm-svn: 124139
2011-01-24 19:40:38 +00:00
689939e648
Handle strings in section names the same way as gas:
...
* If the name is a single string, we remove the quotes
* If the name starts without a quote, we include any quotes in the name
llvm-svn: 124127
2011-01-24 18:02:54 +00:00
b3eca9bb71
Add support for the --noexecstack option.
...
llvm-svn: 124077
2011-01-23 17:55:27 +00:00
8bac423ddb
Add support for lowercase variants.
...
llvm-svn: 124071
2011-01-23 16:11:25 +00:00
4b7b7fba38
Delay the creation of eh_frame so that the user can change the defaults.
...
Add support for SHT_X86_64_UNWIND.
llvm-svn: 124059
2011-01-23 05:43:40 +00:00
4bd612384a
Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm",
...
qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.
llvm-svn: 123975
2011-01-21 14:07:40 +00:00
1f69de3983
Add testcases for clz encoding
...
llvm-svn: 123937
2011-01-20 19:27:16 +00:00
e965f06f7f
Fix the encoding and parsing of clrex instruction
...
llvm-svn: 123936
2011-01-20 19:18:32 +00:00
d8f9b37f31
Add cdp/cdp2 instructions for thumb/thumb2
...
llvm-svn: 123929
2011-01-20 18:32:09 +00:00
33461ecc82
- Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present
...
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.
llvm-svn: 123927
2011-01-20 18:06:58 +00:00
4d4b490fb7
Add mcr*2 and mr*c2 support to thumb2 targets
...
llvm-svn: 123919
2011-01-20 16:58:48 +00:00
cf99dc7eb9
Add mcr* and mr*c support to thumb targets
...
llvm-svn: 123917
2011-01-20 16:35:57 +00:00
d6335ce508
Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc
...
llvm-svn: 123837
2011-01-19 16:56:52 +00:00
dac7a0174e
When matching asm operands, always try to match the most restricted type first.
...
Unfortunately, while this is the "right" thing to do, it breaks some ARM
asm parsing tests because MemMode5 and ThumbMemModeReg are ambiguous. This
is tricky to resolve since neither is a subset of the other.
XFAIL the test for now. The old way was broken in other ways, just ways
we didn't happen to be testing, and our ARM asm parsing is going to require
significant revisiting at a later point anyways.
llvm-svn: 123786
2011-01-18 23:01:21 +00:00
2082057b18
Create two new generic classes to represent the following VMRS/VMSR variations:
...
vmrs reg, fpexc
vmrs reg, fpsid
vmsr fpexc, reg
vmsr fpsid, reg
llvm-svn: 123783
2011-01-18 21:58:20 +00:00
cba727f291
Fix MRS encoding for arm and thumb.
...
llvm-svn: 123778
2011-01-18 21:31:35 +00:00
e86a7ad01a
Fix the encoding of t2ISB by using the right class and also parse it correctly
...
llvm-svn: 123776
2011-01-18 21:17:09 +00:00
e6290ccf9b
Follow the current hack set and enable the correct parsing of bkpt while in thumb mode.
...
llvm-svn: 123772
2011-01-18 20:55:11 +00:00
7f639c11d7
Add support for parsing and encoding ARM's official syntax for the BFI instruction
...
llvm-svn: 123770
2011-01-18 20:45:56 +00:00
66e91d4a58
McARM: Start marking T2 address operands as such, for the benefit of the parser.
...
llvm-svn: 123722
2011-01-18 03:06:03 +00:00
ec517cdf24
Update tests.
...
llvm-svn: 123591
2011-01-16 18:02:57 +00:00
d4a5c05c97
Completed :lower16: / :upper16: support for movw / movt pairs on Darwin.
...
- Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first.
- Added support for Thumb2 :lower16: and :upper16: fix up.
- Added :upper16: and :lower16: relocation support to mach-o object writer.
llvm-svn: 123424
2011-01-14 02:38:49 +00:00
ec47597ecd
As far as I can tell, unified syntax uses c0-c15 instead of cr0-cr15 for mcr and friends.
...
llvm-svn: 123407
2011-01-13 22:38:16 +00:00
965b3c7323
Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step
...
in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.
llvm-svn: 123369
2011-01-13 07:58:56 +00:00
e6ff05c59d
Sort the register list based on the *actual* register numbers rather than the
...
enum values we give to them. <rdar://problem/8823730>
llvm-svn: 123321
2011-01-12 21:20:59 +00:00
9c5b65d289
1. Support ELF pcrel relocations for movw/movt:
...
R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)
llvm-svn: 123294
2011-01-12 00:19:25 +00:00
1f7bc0707d
Workaround for bug 8721.
...
.s Test added.
llvm-svn: 123292
2011-01-11 23:53:41 +00:00
abd2dfd3dc
Fix PR8946, a missing reg/reg form of movdqu.
...
llvm-svn: 123242
2011-01-11 17:04:55 +00:00
9d944b3fcc
McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out the
...
carry setting flag from the mnemonic.
Note that this currently involves me disabling a number of working cases in
arm_instructions.s, this is a hopefully short term evil which will be rapidly
fixed (and greatly surpassed), assuming my current approach flies.
llvm-svn: 123238
2011-01-11 15:59:50 +00:00
c0e8756ba9
McARM: Flush out hard coded known non-predicated mnemonic list.
...
llvm-svn: 123189
2011-01-10 21:01:03 +00:00
9f9a10691a
Correctly disassemble truncated asm.
...
Patch by Richard Simth.
llvm-svn: 122962
2011-01-06 16:48:42 +00:00
f02ca16ba7
Convert MC tests to .s so codegen changes won't break them.
...
llvm-svn: 122786
2011-01-03 23:47:14 +00:00
3686473578
Fix PR8878.
...
llvm-svn: 122658
2011-01-01 19:05:35 +00:00
ee0432ce08
Add another non-commutable instruction that gas accepts commuted forms for.
...
Fixes PR8861.
llvm-svn: 122641
2010-12-30 22:10:49 +00:00
ab14a6f174
MC/Mach-O/Thumb: Set the thumb bit in the symbol table.
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llvm-svn: 122630
2010-12-29 14:14:06 +00:00
46a5b05207
Correctly encode pcrel|indirect.
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llvm-svn: 122624
2010-12-29 04:31:26 +00:00
563301dfdb
Fix bug when trying to output uint16_t or uint32_t.
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llvm-svn: 122615
2010-12-29 02:30:49 +00:00
290d71671e
Implement cfi_def_cfa. Also don't convert to dwarf reg numbers twice. Looks
...
like 6 is a fixed point of that and so the previous tests were OK :-)
llvm-svn: 122614
2010-12-29 01:42:56 +00:00
426e68f793
Implement cfi_def_cfa_register.
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llvm-svn: 122612
2010-12-29 00:26:06 +00:00
86d347dd31
Initial .cfi_offset implementation.
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llvm-svn: 122611
2010-12-29 00:09:59 +00:00
6bbfb6c06c
Don't produce a "DW_CFA_advance_loc 0".
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llvm-svn: 122609
2010-12-28 23:38:03 +00:00
85d91982ca
Implement .cfi_remember_state and .cfi_restore_state.
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llvm-svn: 122602
2010-12-28 18:36:23 +00:00
736a35d9ab
Relax address updates in the eh_frame section.
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llvm-svn: 122591
2010-12-28 05:39:27 +00:00
a75b87b55a
Start adding basic support for emitting the call frame instructions.
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llvm-svn: 122590
2010-12-28 04:15:37 +00:00
1de2dd0e5e
Add support for .cfi_lsda.
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llvm-svn: 122584
2010-12-27 15:56:22 +00:00
a895c69431
MC/Mach-O/Thumb: Select appropriate relocation types for Thumb.
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llvm-svn: 122583
2010-12-27 14:49:49 +00:00
8fc59a682f
Handle reloc_riprel_4byte_movq_load. Should make the bots happy.
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llvm-svn: 122579
2010-12-27 02:03:24 +00:00
2ac8355ecd
Add support for the same encodings of the personality function that gnu as
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supports.
llvm-svn: 122577
2010-12-27 00:36:05 +00:00
9ae2d05d45
Add support for @note. Patch by Jörg Sonnenberger.
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llvm-svn: 122568
2010-12-26 21:30:59 +00:00
9141b611ad
Add basic support for .cfi_personality.
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llvm-svn: 122566
2010-12-26 20:20:31 +00:00
03a102bff3
Generalize a previous change, fixing PR8855 - an valid large immediate
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rejected by the mc assembler.
llvm-svn: 122557
2010-12-25 21:36:35 +00:00
7f2bb4dcae
MC/Mach-O/ARM: Start handling some Thumb branches.
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llvm-svn: 122547
2010-12-24 16:41:46 +00:00
fa3c6f148c
In llvm-mc parse a Hash token as a full line comment. Allows handling of
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preprocessed .s files and matches darwin gas. rdar://8798690
Also fix a comment on the next line of AsmParser.cpp after this new code.
llvm-svn: 122531
2010-12-24 00:12:02 +00:00
ac8173cf71
MC/Mach-O/ARM: Don't try to use scattered relocs for BR24 fixups.
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llvm-svn: 122441
2010-12-22 21:26:43 +00:00
1af01a69d4
Add reduced test from 8845.
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llvm-svn: 122438
2010-12-22 21:15:13 +00:00
45140d2efc
MC/Mach-O/ARM: We always use the SECTDIFF reloc type on ARM, which is
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esp. important given that the LOCAL_SECTDIFF enumeration got redefined.
llvm-svn: 122412
2010-12-22 16:52:19 +00:00
9ccf843a61
MC/Mach-O/ARM: Add enough relocation logic to get BR24 relocations.
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llvm-svn: 122407
2010-12-22 16:19:24 +00:00
73c0ae77ca
Simplify the handling of .size expressions.
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llvm-svn: 122404
2010-12-22 16:03:00 +00:00
ae58e7b179
Teach the MBlaze disassembler to disassemble special purpose registers.
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llvm-svn: 122269
2010-12-20 21:18:04 +00:00
55184ddd35
Set the value of absolute symbols.
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llvm-svn: 122268
2010-12-20 21:14:39 +00:00
e15f591de4
Print all 64bits for st_value and st_size. Adjust tests accordingly.
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llvm-svn: 122263
2010-12-20 20:49:43 +00:00
3307d7cbad
Teach the MBlaze asm parser how to parse special purpose register names.
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llvm-svn: 122261
2010-12-20 20:43:24 +00:00
71d29167ea
Add support for lexing single quotes like 'c'.
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This fixed 8615.
llvm-svn: 122150
2010-12-18 08:56:37 +00:00
2140ff508f
Add a test that shows that we produce no fixups when computing the difference
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of two symbols in the same fragment.
llvm-svn: 122145
2010-12-18 05:07:45 +00:00
af5ab7ad26
Test for push being relaxed.
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llvm-svn: 122124
2010-12-18 01:16:59 +00:00
137d422e50
MC/Expr: Implemnt more aggressive folding during symbol evaluation using
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IsSymbolRefDifferenceFullyResolved(). For example, we will now fold away
something like:
--
_a:
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L0:
...
L1:
...
.long (L1 - L0) / 2
--
llvm-svn: 122043
2010-12-17 05:50:33 +00:00
32c74ea3ab
"Fix" FDE alignment to match what gas does.
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llvm-svn: 122006
2010-12-17 00:28:02 +00:00
654cc4a81c
Make pushq produce signed relocations.
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llvm-svn: 122005
2010-12-16 22:50:01 +00:00
fa27a8621c
Add Neon VCVT instructions for f32 <-> f16 conversions.
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Clang is now providing intrinsics for these and so we need to support them
in the backend. Radar 8068427.
llvm-svn: 121902
2010-12-15 22:14:12 +00:00
c3ff538dcf
Fix misspelled target triples in MC/ARM test commands.
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llvm-svn: 121901
2010-12-15 22:14:01 +00:00
844f6b6cfb
Relax alignment fragments.
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With this we don't need the EffectiveSize field anymore. Without that field
LayoutFragment only updates offsets and we don't need to invalidate the
current fragment when it is relaxed (only the ones following it).
This is also a very small improvement in the accuracy of the layout info as
we now use the after relaxation size immediately.
llvm-svn: 121857
2010-12-15 08:45:53 +00:00
8911d03504
Patch by David Meyer to avoid a O(N^2) behaviour when relaxing fragments.
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Since we now don't update addresses so early, we might relax a bit more than
we need to. This is simillar to the issue in PR8467.
llvm-svn: 121856
2010-12-15 07:39:29 +00:00
4886cc8be7
Add some more MC tests for ARM arithmetic instructions that update or don't
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update the condition codes. These come from my test generator and are just
the ones that MC currently assembles correctly.
llvm-svn: 121830
2010-12-15 01:24:36 +00:00
a9b9300bb8
MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup.
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llvm-svn: 121772
2010-12-14 17:37:16 +00:00
0a017a6db2
Fixed version of 121434 with no new memory leaks.
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llvm-svn: 121471
2010-12-10 07:39:47 +00:00
a945a34c73
Revert my previous patch to make the valgrind bots happy.
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llvm-svn: 121461
2010-12-10 04:01:09 +00:00
56eb741237
Initial support for the cfi directives. This is just enough to get
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f:
.cfi_startproc
nop
.cfi_endproc
assembled (on ELF).
llvm-svn: 121434
2010-12-09 23:48:29 +00:00
3164a346e6
Add support for parsing ARM arithmetic instructions that update or don't update
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the condition codes. Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix. The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present. Four simple test cases added for now, lots more to come.
llvm-svn: 121401
2010-12-09 19:19:43 +00:00
87bc591fc5
Allow a slash, '/', as a prefix separator for X86. rdar://8741045
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llvm-svn: 121320
2010-12-08 23:57:59 +00:00
e78d3b38de
Fix absolute recording of differences of symbols in two sections. Reduced from ctor_dtor_count-2.cpp.
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llvm-svn: 121152
2010-12-07 17:12:32 +00:00
bdbe5a712d
Fix relocations with weak definitions.
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llvm-svn: 121114
2010-12-07 05:57:28 +00:00
2eabaae459
Fix pcrel relocations that cross sections.
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llvm-svn: 121107
2010-12-07 03:50:14 +00:00
a2421ec705
Fix a crash reduced from gcc produced assembly.
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llvm-svn: 121085
2010-12-07 01:09:54 +00:00
99ea8a3510
Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.
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llvm-svn: 121082
2010-12-07 00:45:21 +00:00
44bbe36de6
Second try at making direct object emission produce the same results
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as llc + llvm-mc. This time ELF is not changed and I tested that llvm-gcc
bootstrap on darwin10 using darwin9's assembler and linker.
llvm-svn: 121006
2010-12-06 17:27:56 +00:00
ac60adb38d
Don't use PadSectionToAlignment on windows.
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llvm-svn: 120978
2010-12-06 03:03:44 +00:00
1c8ac8f027
There are two reasons why we might want to use
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foo = a - b
.long foo
instead of just
.long a - b
First, on darwin9 64 bits the assembler produces the wrong result. Second,
if "a" is the end of the section all darwin assemblers (9, 10 and mc) will not
consider a - b to be a constant but will if the dummy foo is created.
Split how we handle these cases. The first one is something MC should take care
of. The second one has to be handled by the caller.
llvm-svn: 120889
2010-12-04 03:21:47 +00:00
1048e75fb9
Next step: Only pad debug_line when the target is darwin. Add a FIXME to avoid
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doing that if the target is darwin10 or newer.
This fixes
*) Direct object emission was producing objects without the workaround on
darwin9.
*) Assembly printing was producing objects with the workaround on linux.
llvm-svn: 120866
2010-12-04 00:31:13 +00:00
567ebd0cb5
Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order
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halfword being emitted to the stream first. rdar://8728174
llvm-svn: 120848
2010-12-03 22:31:40 +00:00
ca7eaaafda
When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the
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32-bit wide version by adding the .w suffix.
llvm-svn: 120838
2010-12-03 20:33:01 +00:00
5fe5f45352
Rename temporary symbols if they conflict with artificial symbols created
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by the assembler. This was blocking parsing any large .s produced by clang for
example.
Fixes PR8596.
llvm-svn: 120603
2010-12-01 20:46:11 +00:00
943fb60b1f
Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax.
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llvm-svn: 120589
2010-12-01 19:18:46 +00:00
6187e66801
Add tests for more forms of Thumb2 loads and stores.
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llvm-svn: 120436
2010-11-30 18:15:21 +00:00
811c936ed5
Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost
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certainly be made more generic. But it does allow us to parse something like:
ldr r3, [r2, r4]
correctly in Thumb mode.
llvm-svn: 120408
2010-11-30 07:44:32 +00:00
e22c7322b8
Correct Thumb2 encodings for a much wider range of loads and stores.
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llvm-svn: 120364
2010-11-30 00:14:31 +00:00
50d662b6cb
Provide Thumb2 encodings for basic loads and stores.
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llvm-svn: 120340
2010-11-29 22:44:32 +00:00
e6840ef4b3
Fix some broken CHECK lines.
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llvm-svn: 120332
2010-11-29 22:34:55 +00:00
232e52cfb7
Add more Thumb encodings.
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llvm-svn: 120279
2010-11-29 01:07:48 +00:00
ccba1a8d95
More Thumb encodings.
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llvm-svn: 120278
2010-11-29 01:00:43 +00:00
9600e97c60
Add Thumb encodings for REV instructions.
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llvm-svn: 120277
2010-11-29 00:42:50 +00:00
775899eb2e
Add more Thumb encodings.
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llvm-svn: 120272
2010-11-29 00:18:15 +00:00
7e8a99b1c3
fix PR8686, accepting a 'b' suffix at the end of all the setcc
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instructions. I choose to handle this with an asmparser hack,
though it could be handled by changing all the instruction definitions
to allow be "setneb" instead of "setne". The asm parser hack is
better in this case, because we want the disassembler to produce
setne, not setneb.
llvm-svn: 120260
2010-11-28 20:23:50 +00:00
eab0800695
Implement the data16 prefix.
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llvm-svn: 120224
2010-11-27 20:29:45 +00:00
1440fd3539
macho-dump: Fix typo.
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llvm-svn: 120185
2010-11-27 04:00:06 +00:00
7c2acd022e
Use multiple 0x66 prefixes so that all nops up to 15 bytes are a single instruction.
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llvm-svn: 120147
2010-11-25 17:14:16 +00:00
f8e127eaf6
Factor some code to parseSectionFlags and fix the default type of a section.
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llvm-svn: 120145
2010-11-25 15:32:56 +00:00
9f75d5df0b
Behave a bit more like gnu as and use the symbol (instead of the section)
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for any relocation to a symbol defined in a tls section.
llvm-svn: 120121
2010-11-24 21:57:39 +00:00
708ac4d6ad
Relocate with the symbol if the relocation is of kind NTPOFF.
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Patch by David Meyer, I added the test.
llvm-svn: 120104
2010-11-24 19:23:50 +00:00
e98d483b71
Fix and add tests for all cases in x86 and x86_64 where gnu as implicitly
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sets the type of a symbol to STT_TLS.
llvm-svn: 120100
2010-11-24 18:51:21 +00:00
af9a7a3e92
Testcase for r120017.
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llvm-svn: 120099
2010-11-24 18:03:57 +00:00
4e70ac7b68
If a symbol is used as tls, mark it as tls even if not declare as so. Probably
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fixes PR8659.
llvm-svn: 120076
2010-11-24 02:19:40 +00:00
3c7cab1402
Produce a relocation for pcrel absolute values. Based on a patch by David Meyer.
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llvm-svn: 120006
2010-11-23 07:20:12 +00:00
c01d679928
Add encoding for ARM "trap" instruction.
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llvm-svn: 119938
2010-11-21 11:05:29 +00:00
b4cd1819fa
implement PR8524, apparently mainline gas accepts movq as an alias for movd
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when transfering between i64 gprs and mmx regs.
llvm-svn: 119931
2010-11-21 08:18:57 +00:00
26cb15a549
Handle PCRel relocations with absolute values. Fixes PR8656.
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llvm-svn: 119917
2010-11-21 00:48:25 +00:00
8be14414f6
Added support for the Mach-O .symbol_resolver directive. rdar://8673046
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llvm-svn: 119816
2010-11-19 18:39:33 +00:00
945b776b6e
Add MC encodings for some Thumb instructions. Test for a few of them. The "bx
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lr" instruction cannot be tested just yet. It requires matching a "condition
code", but adding one of those makes things go south quickly...
llvm-svn: 119774
2010-11-19 01:33:10 +00:00
2063b84297
Add support for parsing the writeback ("!") token.
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llvm-svn: 119761
2010-11-18 23:43:05 +00:00
690fa953e1
More tests.
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llvm-svn: 119756
2010-11-18 23:30:10 +00:00
3517585249
Fix encodings for pkhbt, and fix some tests where I accidentally tested ARM mode instead of Thumb2.
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llvm-svn: 119755
2010-11-18 23:29:56 +00:00
3fec5ff14b
More Thumb2 encodings.
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llvm-svn: 119737
2010-11-18 21:15:19 +00:00
3625098459
Fill out the set of Thumb2 multiplication operator encodings.
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llvm-svn: 119733
2010-11-18 20:32:18 +00:00
d127e7174b
Try again at providing Thumb2 encodings for basic multiplication operators.
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llvm-svn: 119601
2010-11-18 01:08:42 +00:00
28883834e1
Revert r119593 while I figure out my testing disagrees with the buildbot.
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llvm-svn: 119597
2010-11-18 00:42:51 +00:00
64aaddcd64
Provide correct Thumb2 encodings for basic multiplication operators.
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llvm-svn: 119593
2010-11-18 00:19:10 +00:00
307e4688c5
Now that the MBlaze backend is in its own directory, split the test cases into multiple files for different types of instructions.
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llvm-svn: 119580
2010-11-17 22:54:43 +00:00
55425e7f78
Second attempt at correct encodings for Thumb2 bitfield instructions.
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llvm-svn: 119575
2010-11-17 22:16:31 +00:00
6c37ceb182
Revert r119551, which broke buildbots.
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llvm-svn: 119555
2010-11-17 20:48:51 +00:00
7464116bde
Provide Thumb2 encodings for bitfield instructions.
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llvm-svn: 119551
2010-11-17 20:35:29 +00:00
Johnny Chen