llvm-project

Author	SHA1	Message	Date
Nadav Rotem	0f1bc60d51	Optimize sext <4 x i8> and <4 x i16> to <4 x i64>. Patch by Ahmad, Muhammad T <muhammad.t.ahmad@intel.com> llvm-svn: 177421	2013-03-19 18:38:27 +00:00
Elena Demikhovsky	0ccdd1315b	I optimized the following patterns: sext <4 x i1> to <4 x i64> sext <4 x i8> to <4 x i64> sext <4 x i16> to <4 x i64> I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns: (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT))) The sext_in_reg (v4i32 x) may be lowered to shl+sar operations. The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution. I also added a cost of this operations to the AVX costs table. llvm-svn: 175619	2013-02-20 12:42:54 +00:00
Nadav Rotem	0a471ea66c	Cost Model: change the default cost of control flow instructions (br / ret / ...) to zero. llvm-svn: 169423	2012-12-05 21:21:26 +00:00
Nadav Rotem	f036ca466e	CostModel: add another known vector trunc optimization. llvm-svn: 167488	2012-11-06 21:17:17 +00:00
Nadav Rotem	0914f0b262	Cost Model: add tables for some avx type-conversion hacks. llvm-svn: 167480	2012-11-06 19:33:53 +00:00
Nadav Rotem	ae79765676	Code Model: Improve the accuracy of the zext/sext/trunc vector cost estimation. llvm-svn: 167412	2012-11-05 22:20:53 +00:00