David Goodwin
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6deba28c6f
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Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.
llvm-svn: 76883
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2009-07-23 17:06:46 +00:00 |
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Anton Korobeynikov
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c5df7e2dc1
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Emit cross regclass register moves for thumb2.
Minor code duplication cleanup.
llvm-svn: 76124
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2009-07-16 23:26:06 +00:00 |
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Evan Cheng
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cd4cdd1157
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Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
llvm-svn: 75359
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2009-07-11 06:43:01 +00:00 |
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David Goodwin
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c9b1efd515
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t2LDM_RET does not fall-through.
llvm-svn: 75250
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2009-07-10 15:33:46 +00:00 |
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David Goodwin
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22c2fba978
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Use common code for both ARM and Thumb-2 instruction and register info.
llvm-svn: 75067
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2009-07-08 23:10:31 +00:00 |
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David Goodwin
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03ab0bbb24
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Generalize opcode selection in ARMBaseRegisterInfo.
llvm-svn: 75036
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2009-07-08 20:28:28 +00:00 |
|
David Goodwin
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af7451b674
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Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
llvm-svn: 75010
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2009-07-08 16:09:28 +00:00 |
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David Goodwin
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ade05a37f1
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Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2.
llvm-svn: 74731
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2009-07-02 22:18:33 +00:00 |