91033bed94
Really control isel of barrier instructions with cpu feature.
...
llvm-svn: 110787
2010-08-11 06:36:31 +00:00
6e809de90c
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
...
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
instructions).
- Added tests for memory barrier codegen.
llvm-svn: 110785
2010-08-11 06:22:01 +00:00
920f74aaab
Mark ARM compare instructions as isCompare.
...
llvm-svn: 110761
2010-08-11 00:22:27 +00:00
9664984be8
Add a separate ARM instruction format for Saturate instructions.
...
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!! Two of them were already out of sync. I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.) Add support for encoding these instructions.
llvm-svn: 110754
2010-08-11 00:01:18 +00:00
b1021395b8
Fix indentation.
...
llvm-svn: 110363
2010-08-05 19:00:21 +00:00
72de307116
Add an ARM RSCrr instruction for disassembly only.
...
Partial fix for PR7792.
llvm-svn: 110361
2010-08-05 18:59:36 +00:00
adb93e56a3
Add an ARM RSBrr instruction for disassembly only.
...
Partial fix for PR7792.
llvm-svn: 110358
2010-08-05 18:23:43 +00:00
b128824b60
Move newlines before inline jumptables from the asm strings in .td files to
...
the jtblock_operand print methods. This avoids extra newlines in the
disassembler's output. PR7757.
llvm-svn: 109948
2010-07-31 06:28:10 +00:00
c4a96c0e8c
Add builtins for ssat/usat, similar to RealView's __ssat and __usat intrinsics.
...
llvm-svn: 109813
2010-07-29 22:48:09 +00:00
7010a71ac4
Add intrinsics __builtin_arm_qadd & __builtin_arm_qsub to allow access to the QADD & QSUB instructions.
...
Behave identically to __qadd & __qsub RealView instruction intrinsics.
llvm-svn: 109770
2010-07-29 17:56:55 +00:00
c445a7d29b
ARM mode version of r109693. Remove incorrect substitution pattern for UXTB16. It wrongly assumed the input shift was actually a rotate. rdar://8240138
...
llvm-svn: 109696
2010-07-28 23:25:44 +00:00
11013eda5a
Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction
...
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.
llvm-svn: 108570
2010-07-16 23:05:05 +00:00
a90af1ba38
Improve 64-subtraction of immediates when parts of the immediate can fit
...
in the literal field of an instruction. E.g.,
long long foo(long long a) {
return a - 734439407618LL;
}
rdar://7038284
llvm-svn: 108339
2010-07-14 17:45:16 +00:00
0cc4ad983d
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.
...
llvm-svn: 108258
2010-07-13 19:27:42 +00:00
e2289285ae
Changes to ARM tail calls, mostly cosmetic.
...
Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.
llvm-svn: 107851
2010-07-08 01:18:23 +00:00
523e554afa
LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it
...
being moved around away from the jump table it references. rdar://8104340
llvm-svn: 106483
2010-06-21 21:27:27 +00:00
d5c58b76ab
Fix PR 7433. Silly typo in non-Darwin ARM tail call
...
handling, plus correct R9 handling in that mode.
llvm-svn: 106434
2010-06-21 18:21:49 +00:00
e5fcd333da
Indentation and remove dead code.
...
llvm-svn: 106362
2010-06-19 00:11:54 +00:00
589ffb4902
Fix ARM/Thumb reversal in previous attempt.
...
llvm-svn: 106314
2010-06-18 21:07:47 +00:00
a06c2f79fc
An attempt to fix the problem Anton reported with
...
ARM tail calls. Don't know if it works, but it
doesn't break Darwin.
llvm-svn: 106309
2010-06-18 20:44:28 +00:00
3ac52b3e43
Last round of changes for ARM tail calls.
...
Not turning them on yet.
llvm-svn: 106295
2010-06-18 18:13:11 +00:00
438c35b5d1
Add file missing from previous commit.
...
llvm-svn: 106058
2010-06-15 22:24:08 +00:00
d679ff7330
Early implementation of tail call for ARM.
...
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.
llvm-svn: 105413
2010-06-03 21:09:53 +00:00
84511e1526
Clean up 80 column violations. No functional change.
...
llvm-svn: 105350
2010-06-02 21:53:11 +00:00
b342e09b5e
correct retattr
...
llvm-svn: 104980
2010-05-28 18:03:48 +00:00
37eb2c24b9
make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.
...
llvm-svn: 104967
2010-05-28 17:37:40 +00:00
faa3abbe39
Update the saved stack pointer in the sjlj function context following either
...
an alloca() or an llvm.stackrestore(). rdar://8031573
llvm-svn: 104900
2010-05-27 23:49:24 +00:00
c98892fdaa
Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in
...
ISD::. No functional change.
llvm-svn: 104734
2010-05-26 20:22:18 +00:00
bd9485db63
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
...
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
llvm-svn: 104419
2010-05-22 01:06:18 +00:00
b7704fee4c
Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable.
...
llvm-svn: 104114
2010-05-19 07:26:50 +00:00
dd7f566597
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
...
llvm-svn: 104111
2010-05-19 06:07:03 +00:00
2c452fcd14
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
...
llvm-svn: 104102
2010-05-19 01:52:25 +00:00
497d831966
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
...
llvm-svn: 103903
2010-05-16 09:15:36 +00:00
2b7aace2e0
"trap" pseudo-op turned out to be apple-local.
...
Temporary emit it as raw bytes until it will be added to binutils as well.
llvm-svn: 103878
2010-05-15 17:19:20 +00:00
2fa5a7e7e4
Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
...
llvm-svn: 103459
2010-05-11 07:26:32 +00:00
151cd8f159
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
...
instructions to subtarget features and update tests to reflect.
PR5717.
llvm-svn: 103136
2010-05-05 23:44:43 +00:00
92d999001c
Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by
...
Jordy <snhjordy@gmail.com>.
Followup patches will add some tests and adjust to use Subtarget features
for the instructions.
llvm-svn: 103119
2010-05-05 20:44:35 +00:00
807e1748fc
Multiclass LdStCop was using pre-UAL syntax LDC<c>L for the L fragment. Changed
...
to the UAL syntax of LDCL<c>, instead.
Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().
llvm-svn: 101527
2010-04-16 19:33:23 +00:00
acbc06c2a3
Fixed a bug in ARM disassembly where LDRSBT should have am3offset operand, not
...
am2offset. Modified the instruction table entry and added a new test case.
llvm-svn: 101415
2010-04-15 23:12:47 +00:00
0106063556
Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets
...
such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.
llvm-svn: 100892
2010-04-09 20:41:18 +00:00
34de7768bf
Make the use of the vmla and vmls VFP instructions controllable via cmd line.
...
Preliminary testing shows significant performance wins by not using these
instructions.
llvm-svn: 99436
2010-03-24 22:31:46 +00:00
ae08a736d6
Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")
...
with changes to add a separate optional register update argument. Change all
the NEON instructions with address register writeback to use it.
llvm-svn: 99095
2010-03-20 22:13:40 +00:00
053e3510a3
Revert r98679. The disassembler will be updated to depend on the existence of
...
IndexModeUpd and then populates the Inst{21}=1 while populating the instructions
for disassembly.
llvm-svn: 99013
2010-03-19 23:50:27 +00:00
e4191e719b
Revert this change, since it was causing ARM performance regressions.
...
--- Reverse-merging r98889 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMISelLowering.h
U lib/Target/ARM/ARMInstrInfo.td
U lib/Target/ARM/ARMInstrVFP.td
U lib/Target/ARM/ARMISelLowering.cpp
U lib/Target/ARM/ARMInstrFormats.td
llvm-svn: 99010
2010-03-19 22:51:32 +00:00
0433699ef0
set SDNPVariadic on nodes throughout the rest of the targets that
...
need them.
llvm-svn: 98937
2010-03-19 05:33:51 +00:00
f11aa9e7b4
Get rid of target-specific fp <-> int nodes when still I'm here.
...
llvm-svn: 98889
2010-03-18 22:35:45 +00:00
c7ba918b84
Revert 98683. It is breaking something in the disassembler.
...
llvm-svn: 98692
2010-03-16 23:01:13 +00:00
c953bca10b
Remove redundant writeback flag from ARM address mode 6. Also remove the
...
optional register update argument, which is currently unused -- when we add
support for that, it can just be a separate operand.
llvm-svn: 98683
2010-03-16 21:44:40 +00:00
71ab18bdd5
Disambiguate the *_UPD and * variants by specifying the writeback flag as 1.
...
This is for the disassembly work.
There are cases where this is not possible, for example, A8.6.53 LDM Encoding T1.
In such case, we'll use an adhoc approach to deduce the Opcode programmatically.
llvm-svn: 98679
2010-03-16 21:25:05 +00:00
d6243b49d4
Remove the writeback flag from ARM's address mode 4. Now that we have separate
...
instructions for ld/st with writeback, the flag is completely redundant.
llvm-svn: 98643
2010-03-16 17:46:45 +00:00
f1e8f7ff7d
Attempt to appease the arm-linux buildbot by fixing the JIT encodings for new
...
base register updating load/store-multiple instructions.
llvm-svn: 98427
2010-03-13 07:34:35 +00:00
947f04bad0
Change ARM ld/st multiple instructions to have variant instructions for
...
writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback register operand. There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand. The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other. This also fixes Radar 7495976 and should help the verifier work
better for ARM code.
There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.
llvm-svn: 98409
2010-03-13 01:08:20 +00:00
9a3e2398ae
Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero
...
operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.
llvm-svn: 98172
2010-03-10 18:59:38 +00:00
15804db55c
MSR (Move to Special Register from ARM core register) requires a mask to specify
...
what fields of the CPSR or SPSR are affected.
llvm-svn: 98085
2010-03-09 21:39:34 +00:00
b8a7427636
fix a bunch of partially ambiguous patterns on ARM. As an
...
example, this:
(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))
is ambiguous because DPR contains both f64 and v2f32. tblgen
currently accidentally picks f64 because it's first in the
regclass.
llvm-svn: 97955
2010-03-08 18:51:21 +00:00
bf16a17fc1
Initial bits of ARMv4-only support.
...
Patch by John Tytgat!
llvm-svn: 97886
2010-03-06 19:39:36 +00:00
d520eabcb9
Change some asm shift opcode strings to lowercase.
...
llvm-svn: 97567
2010-03-02 17:03:18 +00:00
718ed8a6d5
Added STRHT for disassembly only and fixed a bug in AI3sthpo class where the W
...
bit should be set to 0 instead of 1.
llvm-svn: 97481
2010-03-01 19:22:00 +00:00
8c5d683aa9
The mayHaveSideEffects flag is no longer used.
...
llvm-svn: 97348
2010-02-27 23:47:46 +00:00
38e7bb6f34
Added the follwoing 32-bit Thumb instructions for disassembly only:
...
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
llvm-svn: 97276
2010-02-26 22:04:29 +00:00
45fceea0e4
Updated version of r96634 (which was reverted due to failing 176.gcc and
...
126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.
llvm-svn: 96822
2010-02-22 23:10:38 +00:00
5ddd4aca97
Added SEL, SXTB16, SXTAB16, UXTAB16, SMMULR, SMMLAR, SMMLSR, SMUAD, and SMUSD,
...
for disassembly only.
llvm-svn: 96806
2010-02-22 21:50:40 +00:00
9d4a3e2a7c
Added a bunch of instructions for disassembly only:
...
o signed/unsigned add/subtract
o signed/unsigned halving add/subtract
o unsigned sum of absolute difference [and accumulate]
o signed/unsigned saturate
o signed multiply accumulate/subtract [long] dual
llvm-svn: 96795
2010-02-22 18:50:54 +00:00
a07c9c7c56
Undo r96654. The printing of ARM shift instructions in canonical forms can be
...
handled in ARMInstPrinter.cpp.
And added PLD/PLDW/PLI (Preload Data/Instruction) for disassembly only.
llvm-svn: 96719
2010-02-21 04:42:01 +00:00
1ca8af9b76
Added entries for ASR, LSL, LSR, ROR, and RRX so that the disassembler prints
...
out the canonical form (A8.6.98) instead of the pseudo-instruction as provided
via MOVs.
DBG_ARM_DISASM=YES llvm-mc -triple=arm-unknown-unknown --disassemble
0xc0 0x00 0xa0 0xe1
Opcode=29 Name=ASR Format=ARM_FORMAT_LDMISCFRM
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
asr r0, r0, #1
llvm-svn: 96654
2010-02-19 02:12:06 +00:00
688a90e2d7
Added LDRD_PRE/POST & STRD_PRE/POST for disassembly only.
...
llvm-svn: 96619
2010-02-18 22:31:18 +00:00
74c904589e
Added LDRSBT, LDRHT, LDRSHT for disassembly only. And fixed encoding errors
...
of AI3ldsbpo, AI3ldhpo, and AI3ldshpo in ARMInstrFormats.td in the process.
llvm-svn: 96565
2010-02-18 03:27:42 +00:00
f3d79a5025
Added for disassembly only the variants of DMB, DSB, and ISB.
...
llvm-svn: 96540
2010-02-18 00:19:08 +00:00
1d793a5e0e
Added CLREX (Clear-Exclusive) for disassembly only.
...
A8.6.30
llvm-svn: 96523
2010-02-17 22:37:58 +00:00
5454e0633e
Added RFE for disassembly only.
...
B6.1.8 RFE Return From Exception loads the PC and the CPSR from the word at the
specified address and the following word respectively.
llvm-svn: 96519
2010-02-17 21:39:10 +00:00
036b2f6542
Added BFI for disassembly only.
...
A8.6.18 BFI - Bitfield insert (Encoding A1)
llvm-svn: 96462
2010-02-17 06:31:48 +00:00
4c444bf606
Add SMC (Secure Monitor Call) system instruction for disassembly only.
...
llvm-svn: 96401
2010-02-16 21:59:54 +00:00
3e2cad3b1a
80 column cleanup
...
llvm-svn: 96393
2010-02-16 21:23:02 +00:00
fba7fce5be
Remove trailing whitespace
...
llvm-svn: 96388
2010-02-16 21:07:46 +00:00
2284ddab56
Update Thumb2 to not use CarryDefIsUnused or CarryDefIsUsed predicates, but
...
to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.
llvm-svn: 96384
2010-02-16 20:42:29 +00:00
756ab53e60
Remove redundant setting of Defs. CPSR is already marked by the block level set of Defs.
...
llvm-svn: 96383
2010-02-16 20:35:59 +00:00
0a334d0df9
First step in eliminating the CarryDefIsUnused and CarryDefIsUsed predicates.
...
They won't work with the new ISel mechanism, as Requires predicates are no
longer allowed to reference the node being selected. Moving the predicate to
the patterns instead solves the problem.
This patch handles ARM mode. Thumb2 will follow.
llvm-svn: 96381
2010-02-16 20:17:57 +00:00
46c39d4f1f
Added for disassembly the following instructions:
...
o Store Return State (SRSW, SRS)
o Load/Store Coprocessor (LDC/STC and friends)
o MSR (immediate)
llvm-svn: 96380
2010-02-16 20:04:27 +00:00
70aa8d0745
Fix pr6111: Avoid using the LR register for the target address of an indirect
...
branch in ARM v4 code, since it gets clobbered by the return address before
it is used. Instead of adding a new register class containing all the GPRs
except LR, just use the existing tGPR class.
llvm-svn: 96360
2010-02-16 17:24:15 +00:00
a945c64b5a
Put repeated empty pattern into the AQI instruction class.
...
We could almost use a multiclass for the signed/unsigned instructions, but
there are only 6 of them so I guess it's not worth it.
llvm-svn: 96297
2010-02-15 23:43:47 +00:00
c95a814ec3
Try to factorize the specification of saturating add/subtract operations a bit,
...
as suggested by Bob Wilson.
llvm-svn: 96153
2010-02-14 06:32:20 +00:00
52a6ab3ba7
Add SETEND and BXJ instructions for disassembly only.
...
llvm-svn: 96075
2010-02-13 02:51:09 +00:00
b0208d2a06
Added a bunch of saturating add/subtract instructions for disassembly only.
...
llvm-svn: 96063
2010-02-13 01:21:01 +00:00
29a9103ee6
Add YIELD, WFE, WFI, and SEV instructions for disassembly only.
...
Plus add two formats: MiscFrm and ThumbMiscFrm. Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.
llvm-svn: 96032
2010-02-12 22:53:19 +00:00
dc2051c802
Add halfword multiply accumulate long SMLALBB/BT/TB/TT for disassembly only.
...
llvm-svn: 96019
2010-02-12 21:59:23 +00:00
bdf1b9520c
Add SWP (Swap) and SWPB (Swap Byte) for disassembly only.
...
llvm-svn: 96010
2010-02-12 20:48:24 +00:00
cf20cbec49
Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only.
...
llvm-svn: 95999
2010-02-12 18:55:33 +00:00
905a2d7727
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2,
...
MRRC, MRRc2. For disassembly only.
llvm-svn: 95955
2010-02-12 01:44:23 +00:00
af88c0a84d
Added LDRT/LDRBT/STRT/STRBT for disassembly only.
...
llvm-svn: 95916
2010-02-11 20:31:08 +00:00
f40b8e03fb
Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose.
...
llvm-svn: 95884
2010-02-11 18:12:29 +00:00
9c13dfb5dd
Add pseudo instruction TRAP for disassembly, which is encoded according to A5-21
...
as the "Permanently UNDEFINED" instruction.
llvm-svn: 95873
2010-02-11 17:14:31 +00:00
c7e14704d0
Added NOP, DBG, SVC to the instruction table for disassembly purpose.
...
llvm-svn: 95784
2010-02-10 18:02:25 +00:00
a570d05228
tighten up eh.setjmp sequence a bit.
...
llvm-svn: 95603
2010-02-08 23:22:00 +00:00
5b66b31774
MOVi16 should also be marked as a UnaryDP instruction, i.e., it doesn't have a
...
Rn operand.
llvm-svn: 95025
2010-02-01 23:06:04 +00:00
b3562f7cf6
For MVNr and MVNs, we need to set Inst{25} = 0 so as not to confuse the decoder.
...
llvm-svn: 94955
2010-01-31 11:22:28 +00:00
267430f74d
Fix PR5694. The CMN instructions set the flags differently from CMP, so they
...
cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.
llvm-svn: 94119
2010-01-22 00:08:13 +00:00
6c0fb92c03
Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2.
...
llvm-svn: 93829
2010-01-19 00:44:15 +00:00
8546ec9c14
Patch by David Conrad:
...
"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
sequence it is now."
llvm-svn: 93758
2010-01-18 19:58:49 +00:00
ea6f91ff64
Change SelectCode's argument from SDValue to SDNode *, to make it more
...
clear what information these functions are actually using.
This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.
llvm-svn: 92564
2010-01-05 01:24:18 +00:00
69461f50c1
Mark STREX* as earlyclobber for the success result register.
...
llvm-svn: 91555
2009-12-16 19:44:06 +00:00
bee6f16fed
Add encoding bits "let Inst{11-4} = 0b00000000;" to BR_JTr to disambiguate
...
between BR_JTr and STREXD.
llvm-svn: 91339
2009-12-14 21:51:34 +00:00
3974a80307
v6 sync insn copy/paste error
...
llvm-svn: 91333
2009-12-14 21:33:32 +00:00
3c4f04112a
Add ARMv6 memory and sync barrier instructions
...
llvm-svn: 91329
2009-12-14 21:24:16 +00:00
acba3b0ae2
Fixed encoding bits typo of ldrexd/strexd.
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llvm-svn: 91327
2009-12-14 21:01:46 +00:00
fed3d088ce
correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics
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llvm-svn: 91313
2009-12-14 19:24:11 +00:00
3cdb555e0f
whitespace
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llvm-svn: 91307
2009-12-14 18:36:32 +00:00
5e0d2a2df6
ARM memory barrier instructions are not predicable
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llvm-svn: 91305
2009-12-14 18:31:20 +00:00
9d6410d040
add ldrexd/strexd instructions
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llvm-svn: 91284
2009-12-14 17:02:55 +00:00
8f9a3ac12c
Framework for atomic binary operations. The emitter for the pseudo instructions
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just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.
llvm-svn: 91200
2009-12-12 01:40:06 +00:00
22a4ea8690
memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around.
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llvm-svn: 91150
2009-12-11 20:29:53 +00:00
afdddaed55
Update properties.
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llvm-svn: 91140
2009-12-11 18:52:41 +00:00
5c4e99fca6
Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress.
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llvm-svn: 91090
2009-12-11 01:42:04 +00:00
fed78ccfb5
Add instruction encoding for DMB/DSB
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llvm-svn: 91053
2009-12-10 18:35:32 +00:00
53e8854443
Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics.
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llvm-svn: 91003
2009-12-10 00:11:09 +00:00
c168a52627
Fix some more ARM unified syntax warnings.
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llvm-svn: 90141
2009-11-30 17:47:19 +00:00
2522908653
Materialize global addresses via movt/movw pair, this is always better
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than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
llvm-svn: 89720
2009-11-24 00:44:37 +00:00
de5dea869f
Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
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Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
llvm-svn: 89711
2009-11-23 23:20:51 +00:00
04c0e76772
fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate.
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llvm-svn: 89694
2009-11-23 20:35:53 +00:00
bdb43a9d99
Remat VLDRD from constpool. Clean up some instruction property specifications.
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llvm-svn: 89478
2009-11-20 19:57:15 +00:00
9dea05d724
Fix a few places that were missed when we converted to unified syntax.
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llvm-svn: 89214
2009-11-18 18:10:35 +00:00
14b25eb87b
Set Inst{15-12} (Rd/Rt) to 0b1111 (PC) for BR_JTadd, BR_JTr, and BR_JTm to
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distinguish between them and the more generic instructions (add, mov, and ldr).
llvm-svn: 89108
2009-11-17 17:17:50 +00:00
18183b6d8e
Set Rm bits of BX_RET to 0b1110 (R14); and set condition code bits of BRIND to
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0b1110 (ALways). This is so that the disassembler decoder can distinguish among
BX_RET, BRIND, and BXr9.
llvm-svn: 89000
2009-11-16 23:57:56 +00:00
d7cf55cd0e
Use Unified Assembly Syntax for the ARM backend.
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llvm-svn: 86494
2009-11-09 00:11:35 +00:00
d1d002a6fe
Support alignment specifier for NEON vld/vst instructions
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llvm-svn: 86404
2009-11-07 21:25:39 +00:00
3467dcb12d
My previous patch (r84124) for setting the encoding bits 4 and 7 of DPSoRegFrm
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was wrong and too aggressive in the sense that DPSoRegFrm includes both constant
shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and
Inst{7} = 0). The 'rr' fragment of the multiclass definitions actually means
register/register with no shift, see A8-11.
llvm-svn: 86319
2009-11-07 00:54:36 +00:00
1c66e8a6b7
Put BlockAddresses into ARM constant pools.
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llvm-svn: 85824
2009-11-02 20:59:23 +00:00
5ac6f244fd
Fix schedule model for BFC.
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llvm-svn: 85809
2009-11-02 17:28:36 +00:00
1cf0b03064
Add ARM codegen for indirect branches.
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clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
llvm-svn: 85577
2009-10-30 05:45:42 +00:00
73789b848d
Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
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opcode and operand with a tab. Check for these instructions in the usual
places.
llvm-svn: 85411
2009-10-28 18:26:41 +00:00
e4b80c9bee
Add an indirect branch pattern for ARM. Testcase will be coming soon.
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llvm-svn: 85355
2009-10-28 00:37:03 +00:00
cde65ec581
Similar to r85280, do not clear the "S" bit for RSBri and RSBrs.
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llvm-svn: 85299
2009-10-27 20:51:49 +00:00
4f36affe5f
Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between
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BL_pred and BLr9_pred.
llvm-svn: 85297
2009-10-27 20:45:15 +00:00
b5044ce5a9
Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI"
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instruction format that already takes care of setting this.
llvm-svn: 85280
2009-10-27 19:52:03 +00:00
df5dcdaa10
Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10})
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for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.
llvm-svn: 85271
2009-10-27 18:44:24 +00:00
13edef55b6
Change ARM asm strings to separate opcode from operands with a tab instead of a space.
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llvm-svn: 85178
2009-10-26 23:45:59 +00:00
a33fa47141
Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding
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bits. Johnny, please review -- I do not have a good track record of getting
these right.
llvm-svn: 85173
2009-10-26 22:59:12 +00:00
a6aba77e0a
Add more ARM instruction encodings for 's' bit set and "rs" register encoding
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bits. Patch by Johnny Chen.
llvm-svn: 85167
2009-10-26 22:34:44 +00:00
a93ca3c637
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
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immediate operands when they will fit into the using instruction.
llvm-svn: 84778
2009-10-21 20:44:34 +00:00
786b15fe12
Match more patterns to movt.
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llvm-svn: 84751
2009-10-21 08:15:52 +00:00
2f69ed8f4c
implement printSORegOperand, add lowering for the nasty and despicable MOVi2pieces :)
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llvm-svn: 84573
2009-10-20 00:40:56 +00:00
1a791eedbf
Set instruction encoding bits 4 and 7 for ARM register-register and
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register-shifted-register instructions. Patch by Johnny Chen.
llvm-svn: 84124
2009-10-14 19:00:24 +00:00
423e42b371
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
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llvm-svn: 84009
2009-10-13 18:59:48 +00:00
453a06e3ac
Add some ARM instruction encoding bits.
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Patch by Johnny Chen.
llvm-svn: 83983
2009-10-13 17:35:30 +00:00
0bc673de0d
Fix a tab. Thanks to Johnny Chen for pointing it out.
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llvm-svn: 83973
2009-10-13 15:27:23 +00:00
4a72f7ab53
Mark the LDR instruction with isReMaterializable, as it is rematerializable
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when loading from an invariant memory location.
llvm-svn: 83688
2009-10-09 23:28:27 +00:00
dc7d1ce575
Fix a comment typo.
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Patch by Johnny Chen.
llvm-svn: 83407
2009-10-06 20:18:46 +00:00
1b2b64f618
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
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ld / st pairs, etc.
llvm-svn: 83197
2009-10-01 08:22:27 +00:00
3bbc6c3ae6
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
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llvm-svn: 83191
2009-10-01 01:33:39 +00:00
bcad0c8421
Add "isBarrier = 1" to return instructions.
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Patch by Sylvere Teissier.
llvm-svn: 83135
2009-09-30 01:35:11 +00:00
83e0d481ae
Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
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instruction. This makes it re-materializable.
Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.
llvm-svn: 82982
2009-09-28 09:14:39 +00:00
Evan Cheng