Commit Graph

5046 Commits

Author SHA1 Message Date
Simon Dardis d9d41f531e [mips] MIPSR6 Compact jump support
This patch adds support for compact jumps similiar to the previous compact
branch support for MIPSR6. Unlike compact branches, compact jumps do not
have a forbidden slot.

As MipsInstrInfo::getEquivalentCompactForm can determine the correct
expansion for jumps and branches for both microMIPS and MIPSR6, remove the
unnecessary distinction in the delay slot filler.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders
llvm-svn: 265390
2016-04-05 12:50:29 +00:00
Daniel Sanders b3c2764f89 [mips] Range check simm32 and fold MIPS16's imm32 into simm32.
Summary:
At this point we should be able to enable IAS by default for O32 without
breaking check-all, or recursion.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18439

llvm-svn: 265302
2016-04-04 15:32:49 +00:00
Ulrich Weigand 99ac5045ab [SystemZ] Add compare-and-branch instructions to MC
This adds MC support for fused compare + indirect branch instructions,
ie. CRB, CGRB, CLRB, CLGRB, CIB, CGIB, CLIB, CLGIB. They aren't actually
generated yet -- this is preparation for their use for conditional
returns in the next iteration of D17339.

Author: koriakin
Differential Revision: http://reviews.llvm.org/D18742

llvm-svn: 265296
2016-04-04 14:26:43 +00:00
Zoran Jovanovic 2b7cc5a4ae [mips][microMIPS] Revert commits r264245 and r264248.
Commit r264245 was the reason for failing tests in LLVM test suite.
Commit r264248 depends on the first one.

llvm-svn: 265249
2016-04-02 23:06:13 +00:00
Saleem Abdulrasool 85b43639b1 AArch64: support .cpu directive
Add support for the AArch64 .cpu directive.  This is a slightly involved
directive since the parameter is actually a variable encoded string.  The
general structure is:

  <cpu>[[+-]<feature>]*

We now map some of the supported string names for features for internal
representation of feature flags.  If we encounter one which we do not support,
bail out as we cannot validate the assembly any longer.

Resolves PR27010.

llvm-svn: 265240
2016-04-02 19:29:52 +00:00
Adrian Prantl cf0961f5ea Add missing emissionKind flags to the DICompileUnits of several old testcases.
llvm-svn: 265192
2016-04-01 22:18:43 +00:00
Valery Pykhtin 5b3559c1ec [AMDGPU] fix MADAK/MADMK instructions operand namings to match encoding fields.
$vsrc1 -> $src1, $k -> $imm

Differential Revision: http://reviews.llvm.org/D18659

llvm-svn: 265141
2016-04-01 13:13:12 +00:00
Sagar Thakur 48973d21e1 [MIPS][LLVM-MC] Fix JR encoding for MIPSR6 ISA
Summary: The assembler was picking the wrong JR variant because the pre-R6 one was still enabled at R6.

Author: nitesh.jain
Reviewers: vkalintiris, dsanders
Subscribers: dsanders, llvm-commits, mohit.bhakkad, sagar, bhushan, jaydeep
Differential: D18387
llvm-svn: 265134
2016-04-01 11:55:33 +00:00
James Molloy b876c72bcc Fix for pr24346: arm asm label calculation error in sub
Some ARM instructions encode 32-bit immediates as a 8-bit integer (0-255)
and a 4-bit rotation (0-30, even) in its least significant 12 bits. The
original fixup, FK_Data_4, patches the instruction by the value bit-to-bit,
regardless of the encoding. For example, assuming the label L1 and L2 are
0x0 and 0x104 respectively, the following instruction:

  add r0, r0, #(L2 - L1) ; expects 0x104, i.e., 260

would be assembled to the following, which adds 1 to r0, instead of 260:

  e2800104 add r0, r0, #4, 2 ; equivalently 1

The new fixup kind fixup_arm_mod_imm takes care of the encoding:

  e2800f41 add r0, r0, #260

Patch by Ting-Yuan Huang!

llvm-svn: 265122
2016-04-01 09:40:47 +00:00
Oliver Stannard a5520b02a5 [AArch64] Better errors for out-of-range fixups
When a fixup that can be resolved by the assembler is out of range, we should
report an error in the source, rather than crashing.

Differential Revision: http://reviews.llvm.org/D18402

llvm-svn: 265120
2016-04-01 09:14:50 +00:00
Adrian Prantl b8089516a5 testcase gardening: update the emissionKind enum to the new syntax. (NFC)
llvm-svn: 265081
2016-04-01 00:16:49 +00:00
Jacques Pienaar 4badd6aaf3 [lanai] isBrImm should accept any non-constant immediate.
isBrImm should accept any non-constant immediate. Previously it was only accepting LanaiMCExpr ones which was wrong.

Differential Revision: http://reviews.llvm.org/D18571

llvm-svn: 265032
2016-03-31 17:58:55 +00:00
Ehsan Amiri 99b017ae35 [PPC] basic support for Power 9 direct move instructions
http://reviews.llvm.org/D18097

Initial support does not include any patterns to generate this instructions

llvm-svn: 265031
2016-03-31 17:47:17 +00:00
Valery Pykhtin ab962acd59 [AMDGPU] enable few disassembler tests that were mistakenly marked as FIXME.
llvm-svn: 265028
2016-03-31 17:28:46 +00:00
Nemanja Ivanovic a621a7f9c3 [PowerPC] Basic support for P9 atomic loads and stores
This patch corresponds to review:
http://reviews.llvm.org/D18032

This patch provides asm implementation for the following instructions:
lwat, ldat, stwat, stdat, ldmx, mcrxrx

llvm-svn: 265022
2016-03-31 15:26:37 +00:00
Daniel Sanders 85fd10bd93 [mips] Range check simm16
Summary:
There are too many instructions to exhaustively test so addiu and lwc2 are
used as representative examples.

It should be noted that many memory instructions that should have simm16
range checking do not because it is also necessary to support the macro
of the same name which accepts simm32. The range checks for these occur in
the macro expansion.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18437

llvm-svn: 265019
2016-03-31 14:34:00 +00:00
Daniel Sanders eab3146156 [mips] Range check simm11 and mem_simm11.
Summary:
ldc2/sdc2 now emit slightly worse diagnostics for MIPS-I. The problem
is that they don't trigger the custom parser because all the candidates
are disabled by feature bits. On all other subtargets, the diagnostics are
accurate but are subject to the usual issues of needing to report multiple
ways to correct the code (e.g. smaller offset, enable a CPU feature) but
only being able to report one error.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18436

llvm-svn: 265018
2016-03-31 14:23:20 +00:00
Sam Kolton 1048fb1818 [AMDGPU] Disassembler: support for DPP
Review: http://reviews.llvm.org/D18642
llvm-svn: 265015
2016-03-31 14:15:04 +00:00
Daniel Sanders dc0602a2c2 [mips] Split mem_msa into range checked mem_simm10 and mem_simm10_lsl[123]
Summary:
Also, made test_mi10.s formatting consistent with the majority of the
MC tests.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18435

llvm-svn: 265014
2016-03-31 14:12:01 +00:00
Daniel Sanders 2e9f69d933 [mips] Range check simm9 and fix a bug this revealed.
Summary:
The bug was that microMIPS's [ls]w[lr]e instructions claimed to support a
12-bit offset when it is only 9-bit.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D18434

llvm-svn: 265010
2016-03-31 13:15:23 +00:00
Zlatko Buljan 6221be8e46 [mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructions
Differential Revision: http://reviews.llvm.org/D17334

llvm-svn: 265002
2016-03-31 08:51:24 +00:00
Jonas Paulsson f76123386a [SystemZ] Add nop and nopr InstAliases.
For compatability with GAS, nop and nopr are recognized as alises for
bc and bcr, respectively. A mask of 0 turns these instructions
effectively into no-operations.

Reviewed by Ulrich Weigand.

llvm-svn: 264875
2016-03-30 16:11:58 +00:00
Evgeniy Stepanov a023f79db1 Handle section vs global name conflict.
This is a fix for PR26941.

When there is both a section and a global definition with the same
name, the global wins.

Section symbols are not added to the symbol table; section references
are left undefined and fixed up in the object writer unless they've
been satisfied by some other definition.

llvm-svn: 264649
2016-03-28 20:36:28 +00:00
Douglas Katzman d0c11cf7ad Sparc: silently ignore .proc assembler directive
Differential Revision: http://reviews.llvm.org/D18463

llvm-svn: 264579
2016-03-28 14:00:11 +00:00
Jacques Pienaar fcef3e4617 [lanai] Add Lanai backend.
Add the Lanai backend to lib/Target.

General Lanai backend discussion on llvm-dev thread "[RFC] Lanai backend" (http://lists.llvm.org/pipermail/llvm-dev/2016-February/095118.html).

Differential Revision: http://reviews.llvm.org/D17011

llvm-svn: 264578
2016-03-28 13:09:54 +00:00
Chuang-Yu Cheng d5eb774eb6 [Power9] Implement new altivec instructions: bcd* series
This patch implements the following altivec instructions:

- Decimal Convert From/to National/Zoned/Signed-QWord:
    bcdcfn. bcdcfz. bcdctn. bcdctz. bcdcfsq. bcdctsq.

- Decimal Copy-Sign/Set-Sign:
    bcdcpsgn. bcdsetsgn.

- Decimal Shift/Unsigned-Shift/Shift-and-Round:
    bcds. bcdus. bcdsr.

- Decimal (Unsigned) Truncate:
    bcdtrunc. bcdutrunc.

Total 13 instructions

Thanks Amehsan's advice! Thanks Kit's great help!
Reviewers: hal, nemanja, kbarton, tjablin, amehsan

http://reviews.llvm.org/D17838

llvm-svn: 264568
2016-03-28 09:04:23 +00:00
Chuang-Yu Cheng 80722719eb [Power9] Implement new vsx instructions: insert, extract, test data class, min/max, reverse, permute, splat
This change implements the following vsx instructions:

- Scalar Insert/Extract
    xsiexpdp xsiexpqp xsxexpdp xsxsigdp xsxexpqp xsxsigqp

- Vector Insert/Extract
    xviexpdp xviexpsp xvxexpdp xvxexpsp xvxsigdp xvxsigsp
    xxextractuw xxinsertw

- Scalar/Vector Test Data Class
    xststdcdp xststdcsp xststdcqp
    xvtstdcdp xvtstdcsp

- Maximum/Minimum
    xsmaxcdp xsmaxjdp
    xsmincdp xsminjdp

- Vector Byte-Reverse/Permute/Splat
    xxbrd xxbrh xxbrq xxbrw
    xxperm xxpermr
    xxspltib

30 instructions

Thanks Nemanja for invaluable discussion! Thanks Kit's great help!
Reviewers: hal, nemanja, kbarton, tjablin, amehsan

http://reviews.llvm.org/D16842

llvm-svn: 264567
2016-03-28 08:34:28 +00:00
Chuang-Yu Cheng 5663848996 [Power9] Implement new vsx instructions: quad-precision move, fp-arithmetic
This change implements the following vsx instructions:

- quad-precision move
    xscpsgnqp, xsabsqp, xsnegqp, xsnabsqp

- quad-precision fp-arithmetic
    xsaddqp(o) xsdivqp(o) xsmulqp(o) xssqrtqp(o) xssubqp(o)
    xsmaddqp(o) xsmsubqp(o) xsnmaddqp(o) xsnmsubqp(o)

22 instructions

Thanks Nemanja and Kit for careful review and invaluable discussion!
Reviewers: hal, nemanja, kbarton, tjablin, amehsan

http://reviews.llvm.org/D16110

llvm-svn: 264565
2016-03-28 07:38:01 +00:00
Chuang-Yu Cheng 065969ec8e [Power9] Implement new altivec instructions: permute, count zero, extend sign, negate, parity, shift/rotate, mul10
This change implements the following vector operations:
- vclzlsbb vctzlsbb vctzb vctzd vctzh vctzw
- vextsb2w vextsh2w vextsb2d vextsh2d vextsw2d
- vnegd vnegw
- vprtybd vprtybq vprtybw
- vbpermd vpermr
- vrlwnm vrlwmi vrldnm vrldmi vslv vsrv
- vmul10cuq vmul10uq vmul10ecuq vmul10euq

28 instructions

Thanks Nemanja, Kit for invaluable hints and discussion!
Reviewers: hal, nemanja, kbarton, tjablin, amehsan

Phabricator: http://reviews.llvm.org/D15887
llvm-svn: 264504
2016-03-26 05:46:11 +00:00
Simon Atanasyan 26fe92d19f [MC][mips] Add MipsMCInstrAnalysis class and register it as MC instruction analyzer
The `MipsMCInstrAnalysis` class overrides the `evaluateBranch` method
and calculates target addresses for branch and calls instructions.
That allows llvm-objdump to print functions' names in branch instructions
in the disassemble mode.

Differential Revision: http://reviews.llvm.org/D18209

llvm-svn: 264309
2016-03-24 17:18:14 +00:00
Simon Atanasyan b7807a0c8e [llvm-readobj] Decode st_other symbol's flags
The patch supports common STV_xxx visibility flags and MIPS specific
STO_MIPS_xxx flags.

Differential Revision: http://reviews.llvm.org/D18447

llvm-svn: 264300
2016-03-24 16:10:37 +00:00
Daniel Sanders 15f8fb6f83 [mips] Range check vsplat_simm5 and vsplat_simm10
Summary:

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D18177

llvm-svn: 264287
2016-03-24 14:53:40 +00:00
Daniel Sanders 837f15187b [mips] Range check simm10
Summary:

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D18148

llvm-svn: 264279
2016-03-24 13:26:59 +00:00
Zlatko Buljan 94af4cbcf4 [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions
Differential Revision: http://reviews.llvm.org/D17137

llvm-svn: 264248
2016-03-24 09:22:45 +00:00
Hrvoje Varga 2cb74ac3c3 [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructions
Differential Revision: http://reviews.llvm.org/D17328

llvm-svn: 264246
2016-03-24 08:02:09 +00:00
Oliver Stannard aa77b1e025 [AArch64] Replace some uses of report_fatal_error with reportError in AArch64 ELF object writer
If we can't handle a relocation type, report it as an error in the source,
rather than asserting. I've added a more descriptive message and a test for the
only cases of this that I've been able to trigger.

Differential Revision: http://reviews.llvm.org/D18388

llvm-svn: 264156
2016-03-23 13:45:03 +00:00
Valery Pykhtin c0a77c5064 [AMDGPU] Fix missing assembler predicates.
Differential Revision: http://reviews.llvm.org/D18351

llvm-svn: 264137
2016-03-23 04:27:26 +00:00
Daniel Sanders 97297770a6 [mips] Range check simm7.
Summary:
Also renamed li_simm7 to li16_imm since it's not a simm7 and has an unusual
encoding (it's a uimm7 except that 0x7f represents -1).

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18145

llvm-svn: 264056
2016-03-22 14:40:00 +00:00
Daniel Sanders 0f17d0da4a [mips] Range check simm5.
Summary:
We can't check the error message for this one because there's another lw/sw
available that covers a larger range. We therefore check the transition
between the two sizes.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D18144

llvm-svn: 264054
2016-03-22 14:29:53 +00:00
Daniel Sanders 946dee3b5b [mips] Range check vsplat_uimm[1234568].
Summary:

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18143

llvm-svn: 264053
2016-03-22 14:17:41 +00:00
Daniel Sanders 93fa4ce9b7 [mips] Range check uimm4_ptr, remove uimm6_ptr, and use correctly sized immediates in MSA copy/insert.
Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18142

llvm-svn: 264052
2016-03-22 13:58:53 +00:00
Marina Yatsina 33ef7dad18 [ELF][gcc compatibility]: support section names with special characters (e.g. "/")
Adding support for section names with special characters in them (e.g. "/").
GCC successfully compiles such section names.
This also fixes PR24520.

Differential Revision: http://reviews.llvm.org/D15678

llvm-svn: 264038
2016-03-22 11:23:15 +00:00
Krzysztof Parzyszek b14f4fd0de [Hexagon] Add handling fixups and instruction relaxation
llvm-svn: 263981
2016-03-21 20:27:17 +00:00
Krzysztof Parzyszek c6f1e1a709 [Hexagon] Properly encode registers in duplex instructions
llvm-svn: 263980
2016-03-21 20:13:33 +00:00
Colin LeMahieu 0143146514 [MCParser] Accept uppercase radix variants 0X and 0B
Differential Revision: http://reviews.llvm.org/D14781

llvm-svn: 263802
2016-03-18 18:22:07 +00:00
Colin LeMahieu 307a83d76a [llvm-objdump] Print <unknown> in place of instruction text if it couldn't be disassembled.
llvm-svn: 263793
2016-03-18 16:26:48 +00:00
Sam Kolton a74cd526e9 [AMDGPU] Assembler: Change dpp_ctrl syntax to match sp3
Review: http://reviews.llvm.org/D18267
llvm-svn: 263789
2016-03-18 15:35:51 +00:00
Valery Pykhtin c4546ec0cf [AMDGPU] add VI disassembler tests. NFC.
Autogenerated from the corresponding assembler tests with a few FIXME added (will fix soon).

Differential Revision: http://reviews.llvm.org/D18249

llvm-svn: 263729
2016-03-17 17:56:33 +00:00
Simon Atanasyan 58ee875296 [mips] Use `formatImm` call to print immediate value in the `MipsInstPrinter`
That allows, for example, to print hex-formatted immediates using
llvm-objdump --print-imm-hex command line option.

Differential Revision: http://reviews.llvm.org/D18195

llvm-svn: 263704
2016-03-17 10:43:36 +00:00
Nikolay Haustov cb9dddb1d7 [AMDGPU] Assembler: Update SOP* tests
Add VI encodings.
Reformat sopp.s to match style of other files.

Differential Revision: http://reviews.llvm.org/D18084

llvm-svn: 263540
2016-03-15 07:44:57 +00:00