llvm-project

Author	SHA1	Message	Date
Tim Northover	e94a518a22	IR: add a second ordering operand to cmpxhg for failure The syntax for "cmpxchg" should now look something like: cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic where the second ordering argument gives the required semantics in the case that no exchange takes place. It should be no stronger than the first ordering constraint and cannot be either "release" or "acq_rel" (since no store will have taken place). rdar://problem/15996804 llvm-svn: 203559	2014-03-11 10:48:52 +00:00
Dmitry Vyukov	a878e74351	tsan: instrument atomic nand operation llvm-svn: 168684	2012-11-27 08:09:25 +00:00
Dmitry Vyukov	12b5cb9a0a	[tsan] add fail order to compare_exchange llvm-svn: 168586	2012-11-26 11:36:19 +00:00
Dmitry Vyukov	0044e386e9	tsan: switch to new memory_order constants (ABI compatible) llvm-svn: 167615	2012-11-09 14:12:16 +00:00
Dmitry Vyukov	92b9e1dbfd	tsan: instrument all atomics (including fetch_add, exchange, cas, etc) llvm-svn: 167612	2012-11-09 12:55:36 +00:00
Dmitry Vyukov	84d75cdffd	tsan: update the test for new atomic enums llvm-svn: 165109	2012-10-03 13:19:20 +00:00
Dmitry Vyukov	68845093dd	tsan: update the test for new atomic enums llvm-svn: 165108	2012-10-03 13:13:54 +00:00
Kostya Serebryany	a1259778b4	[tsan] Atomic support for ThreadSanitizer, patch by Dmitry Vyukov llvm-svn: 155698	2012-04-27 07:31:53 +00:00