Commit Graph

370082 Commits

Author SHA1 Message Date
Haojian Wu efa9aaad70 [clang] Suppress "follow-up" diagnostics on recovery call expressions.
Because of typo-correction, the AST can be transformed, and the transformed
AST is marginally useful for diagnostics purpose, the following
diagnostics usually do harm than good (easily cause confusions).

Given the following code:

```
void abcc();
void test() {
  if (abc());
  // diagnostic 1 (for the typo-correction): the typo is correct to `abcc()`, so the code is treate as `if (abcc())` in AST perspective;
  // diagnostic 2 (for mismatch type): we perform an type-analysis on `if`, discover the type is not match
}
```

The secondary diagnostic "convertable to bool" is likely bogus to users.

The idea is to use RecoveryExpr (clang's dependent mechanism) to preserve the
recovery behavior but suppress all follow-up diagnostics.

Differential Revision: https://reviews.llvm.org/D89946
2020-10-26 12:40:00 +01:00
Simon Pilgrim 6b2eb31e1e [InstCombine] Add support for zext(and(neg(amt),width-1)) rotate shift amount patterns
Alive2: https://alive2.llvm.org/ce/z/bCvvHd
2020-10-26 11:22:41 +00:00
Simon Pilgrim 821f3b763a [InstCombine] Add rotate tests where the shift amount is zero extended after masking 2020-10-26 11:22:40 +00:00
Dmitry Vyukov 5cad535ccf tsan: add mips64 support in lib/tsan/go/buildgo.sh
Enable mips64 support in buildgo.sh.

Author: mzh (Meng Zhuo)
Reviewed-in: https://reviews.llvm.org/D90130
2020-10-26 12:19:52 +01:00
Evgeny Leviant 1876d06ea3 [llvm-mca] Add few memory instructions to cortex-a57 test 2020-10-26 14:18:15 +03:00
Djordje Todorovic a64b2c9366 [NFC][InstrRefLDV] Fix a typo 2020-10-26 04:04:16 -07:00
Pavel Labath e4cc6e9bcd [lldb] Modernize PseudoTerminal::Fork 2020-10-26 12:01:20 +01:00
Pavel Labath 97ca9ca180 [lldb] Fix bitfield "frame var" for pointers (pr47743)
Displaying large packed bitfields did not work if one was accessing them
through a pointer, and he used the "->" notation ("[0]." notation is
fine). The reason for that is that implicit dereference in -> is plumbed
all the way down to ValueObjectChild::UpdateValue, where the process of
fetching the child value was forked for this flag. The bitfield
"sliding" code was implemented only for the branch which did not require
dereferencing.

This patch restructures the function to avoid this mistake. Processing
now happens in two stages.
- first the parent is dereferenced (if needed)
- then the child value is computed (this step includes sliding and is
  common for both branches)

Differential Revision: https://reviews.llvm.org/D89236
2020-10-26 12:01:20 +01:00
Michał Górny f5ca27569e [lldb] [Process/Linux] Reuse NativeRegisterContextWatchpoint_x86
Differential Revision: https://reviews.llvm.org/D90119
2020-10-26 11:55:22 +01:00
Michał Górny a890237665 [lldb] [Process/NetBSD] Set xs_xstate_bv correctly when setting regs
Ensure that xs_xstate_bv is set correctly before calling
WriteRegisterSet().  The bit can be clear if the relevant registers
were at their initial state when they were read, and it needs to be set
in order to apply changes from the XState structure.

Differential Revision: https://reviews.llvm.org/D90105
2020-10-26 11:54:40 +01:00
Michał Górny 37d4d3bb4d [lldb] [test/Register] Use initial state for write tests
Reset registers to their 'initial' state instead of a semi-random
pattern in write tests.  While the latter might have been helpful
while debugging failures (i.e. to distinguish unmodified registers
from mistakenly written zeroes), the former makes it possible to test
whether xstate_bv field is written correctly when using XSAVE.

With this change, the four relevant tests start failing on NetBSD
without D90105.

Differential Revision: https://reviews.llvm.org/D90114
2020-10-26 11:54:00 +01:00
Michał Górny 7acf2e2e1e [lldb] [Process/FreeBSDRemote] Fix #include for i386 compat
Include <x86/fpu.h> rather than <machine/fpu.h>, as the latter is not
present on i386.

Differential Revision: https://reviews.llvm.org/D90128
2020-10-26 11:53:26 +01:00
Tyker 4afa077899 Try to fix buildbots after d3205bbca3 2020-10-26 11:49:21 +01:00
Jean Perier 878b526409 [flang] Tighten rules to resolve procedure as intrinsic procedure
2 Bug fixes:

- Do not resolve procedure as intrinsic if they appeared in an
  EXTERNAL attribute statement (one path was not considering this flag)

- Emit an error if a procedure resolved to be an intrinsic function
  (resp. subroutine) is used as a subroutine (resp. function).
  Lowering was attempted while the evaluate::Expression for the
  call was missing without any errors.

1 behavior change:

- Do not implicitly resolve subroutines (resp. functions) as intrinsics
  because their name is the name of an intrinsic function (resp.
  subroutine). Add justification in documentation.

Reviewed By: klausler, tskeith

Differential Revision: https://reviews.llvm.org/D90049
2020-10-26 11:25:40 +01:00
Tyker d3205bbca3 [Annotation] Allows annotation to carry some additional constant arguments.
This allows using annotation in a much more contexts than it currently has.
especially when annotation with template or constexpr.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D88645
2020-10-26 10:50:05 +01:00
Kazushi (Jam) Marukawa 8aa60f67dc [VE] Add vector comparison and min/max
Add VCMP/VCPS/VCPX/VCMS/VCMX vector instructions.  Also add regression
tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D89643
2020-10-26 18:32:04 +09:00
Kazushi (Jam) Marukawa 0acf700243 [VE] Add integer arithmetic vector instructions
Add VADD/VADS/VADX/VSUB/VSBS/VSBX/VMPY/VMPS/VMPX/VMPD/VDIV/VDVS/VDVX
instructions.  Also add regression tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D89642
2020-10-26 18:30:11 +09:00
Florian Hahn b2bec7cece [AsmPrinter] Add per BB instruction mix remark.
This patch adds a remarks that provides counts for each opcode per basic block.

An snippet of the generated information can be seen below.

The current implementation uses the target specific opcode for the counts. For example, on AArch64 this means we currently get 2 entries for `add` instructions if the block contains 32 and 64 bit adds. Similarly, immediate version are treated differently.

Unfortunately there seems to be no convenient way to get only the mnemonic part of the instruction as a string AFAIK. This could be improved in the future.

```
--- !Analysis
Pass:            asm-printer
Name:            InstructionMix
DebugLoc:        { File: arm64-instruction-mix-remarks.ll, Line: 30, Column: 30 }
Function:        foo
Args:
  - String:          'BasicBlock: '
  - BasicBlock:      else
  - String:          "\n"
  - String:          INST_MADDWrrr
  - String:          ': '
  - INST_MADDWrrr:   '2'
  - String:          "\n"
  - String:          INST_MOVZWi
  - String:          ': '
  - INST_MOVZWi:     '1'
```

Reviewed By: anemet, thegameg, paquette

Differential Revision: https://reviews.llvm.org/D89892
2020-10-26 09:25:45 +00:00
Sebastian Neubauer a094b4fa4b [AMDGPU] Emit new pal metadata by default
If no pal metadata is given, default to the msgpack format instead of
the legacy metadata. This makes tests better readable.

Differential Revision: https://reviews.llvm.org/D90035
2020-10-26 10:16:17 +01:00
Evgeny Leviant a95ce5f65f [ARM][SchedModels] Rename and generalize predicate. NFC 2020-10-26 12:14:55 +03:00
Kai Luo 82150dae86 [PowerPC] Add test case for pr47830. NFC. 2020-10-26 09:11:33 +00:00
Kazushi (Jam) Marukawa f32992ad24 [VE] Support atomic load
Support atomic load instruction and add a regression test.
VE uses release consitency, so need to insert fence around
atomic instructions.  This patch enable AtomicExpandPass
and use emitLeadingFence and emitTrailingFence mechanism
for such purpose.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90135
2020-10-26 18:02:45 +09:00
Evgeny Leviant 99b2756517 [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred
Differential revision: https://reviews.llvm.org/D90024
2020-10-26 12:01:39 +03:00
Evgeny Leviant a4fc18e641 [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate
Differential revision: https://reviews.llvm.org/D90029
2020-10-26 11:54:08 +03:00
Evgeny Leviant d613e39d52 [ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate
Differential revision: https://reviews.llvm.org/D90045
2020-10-26 11:43:02 +03:00
LLVM GN Syncbot 8000d277ba [gn build] Port 61bc18de0b 2020-10-26 08:07:25 +00:00
David Green 61bc18de0b [Schedule] Add a MultiHazardRecognizer
This adds a MultiHazardRecognizer and starts to make use of it in the
ARM backend. The idea of the class is to allow multiple independent
hazard recognizers to be added to a single base MultiHazardRecognizer,
allowing them to all work in parallel without requiring them to be
chained into subclasses. They can then be added or not based on cpu or
subtarget features, which will become useful in the ARM backend once
more hazard recognizers are being used for various things.

This also renames ARMHazardRecognizer to ARMHazardRecognizerFPMLx in the
process, to more clearly explain what that recognizer is designed for.

Differential Revision: https://reviews.llvm.org/D72939
2020-10-26 08:06:17 +00:00
Kazushi (Jam) Marukawa 52f03fe115 [VE] Support atomic fence
Support atomic fence instruction and add a regression test.
Add MEMBARRIER pseudo insturction also to use it as a barrier
against to the compiler optimizations.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D90112
2020-10-26 17:03:09 +09:00
Max Kazantsev bfabd7878b Fix broken build after previous commit 2020-10-26 14:55:46 +07:00
Max Kazantsev cdccc82f48 [NFC] Remove unused funciton param 2020-10-26 14:53:22 +07:00
Max Kazantsev 4b5e848bef [NFC] Factor out common code into lambda for further improvement 2020-10-26 14:50:45 +07:00
Max Kazantsev c019099053 [IndVars] Use contextual knowledge when proving trivial conds
No exact example where it would help, but it's a generally a more
powerful way to prove predicates.
2020-10-26 13:48:32 +07:00
Kirill Bobyrev 15f6bad6d7
[clangd] Add dependency on remote index service proto
It requires Index.proto to be built first. Failed builds:
https://github.com/clangd/clangd/runs/1305985916
2020-10-26 07:08:49 +01:00
Christudasan Devadasan 5a061041ec [AMDGPU] Avoid offset register in MUBUF for direct stack object accesses
We use an absolute address for stack objects and
it would be necessary to have a constant 0 for soffset field.

Fixes: SWDEV-228562

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D89234
2020-10-26 11:08:37 +05:30
Craig Topper 82974e0114 [X86] Don't disassemble wbinvd with 0xf2 or 0x66 prefix.
The 0xf3 prefix has been defined as wbnoinvd on Icelake Server. So
the prefix isn't ignored by the CPU. AMD documentation suggests that
wbnoinvd is treated as wbinvd on older processors. Intel documentation
is not clear. Perhaps 0xf2 and 0x66 are treated the same, but its
not documented.

This patch changes TB to PS in the td file so 0xf2 and 0x66 will
be treated as errors. This matches versions of objdump after
wbnoinvd was added.
2020-10-25 20:56:01 -07:00
Liu, Chen3 180548c5c7 [X86] VEX/EVEX prefix doesn't work for inline assembly.
For now, we lost the encoding information if we using inline assembly.
The encoding for the inline assembly will keep default even if we add
the vex/evex prefix.

Differential Revision: https://reviews.llvm.org/D90009
2020-10-26 08:37:45 +08:00
Craig Topper 63ba82ed00 [X86] Use TargetConstant for immediates for VASTART_SAVE_XMM_REGS. 2020-10-25 12:52:56 -07:00
Craig Topper 2ed16aa66f [X86] Use TargetConstant instead of Constant for operands to X86vaarg64. 2020-10-25 12:24:59 -07:00
Sanjay Patel f2c25c7079 [CostModel] remove cost-kind predicate for some vector reduction costs
This is a modified 2nd try of 22d10b8ab4
(reverted by 1c8371692d because it managed
to expose an existing crashing bug that should be fixed by
74ffc823 ).

Original commit message:

This is similar in spirit to 01ea93d85d (memcpy) except that
here the underlying caller assumptions were created for vectorizer
use (throughput) rather than other passes.

That meant targets could have an enormous throughput cost with no
corresponding size, latency, or blended cost increase.
The ARM costs show a small difference between throughput and
size because there's an underlying difference in cmp/sel
costs that is also predicated on cost-kind.

Paraphrasing from the previous commits:
This may not make sense for some callers, but at least now the
costs will be consistently wrong instead of mysteriously wrong.

Targets should provide better overrides if the current modeling
is not accurate.
2020-10-25 15:17:52 -04:00
Sanjay Patel 74ffc823ed [CostModel] fix operand/type accounting for fadd/fmul reductions
I'm not sure if/how this ever worked, but it must not be tested
currently because the basic tests added here were crashing as
noted in the post-review comments for 1c83716 (which reverted
another cost-model fix in 22d10b8ab4).
2020-10-25 15:01:19 -04:00
Nikita Popov ebeef022aa [SCEV] Strenthen nowrap flags after constant folding for mul exprs
Same change as 0dda633317, but for
mul expressions. We want to first fold any constant operans and
then strengthen the nowrap flags, as we can compute more precise
flags at that point.
2020-10-25 19:43:58 +01:00
Aaron Puchert b296c64e64 Thread safety analysis: Nullability improvements in TIL, NFCI
The constructor of Project asserts that the contained ValueDecl is not
null, use that in the ThreadSafetyAnalyzer. In the case of LiteralPtr
it's the other way around.

Also dyn_cast<> is sufficient if we know something isn't null.
2020-10-25 19:37:16 +01:00
Aaron Puchert 5250a03a99 Thread safety analysis: Consider global variables in scope
Instead of just mutex members we also consider mutex globals.
Unsurprisingly they are always in scope. Now the paper [1] says that

> The scope of a class member is assumed to be its enclosing class,
> while the scope of a global variable is the translation unit in
> which it is defined.

But I don't think we should limit this to TUs where a definition is
available - a declaration is enough to acquire the mutex, and if a mutex
is really limited in scope to a translation unit, it should probably be
only declared there.

The previous attempt in 9dcc82f34e was causing false positives because
I wrongly assumed that LiteralPtrs were always globals, which they are
not. This should be fixed now.

[1] https://static.googleusercontent.com/media/research.google.com/en/us/pubs/archive/42958.pdf

Fixes PR46354.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D84604
2020-10-25 19:32:26 +01:00
Nikita Popov 1ff313f098 [SCEV] Always constant fold mul expression operands
Establish parity with the handling of add expressions, by always
constant folding mul expression operands before checking the depth
limit (this is a non-recursive simplification). The code was already
unconditionally constant folding the case where all operands were
constants, but was not folding multiple constant operands together
if there were also non-constant operands.

This requires picking out a different demonstration for depth-based
folding differences in the limit-depth.ll test.
2020-10-25 18:50:06 +01:00
Nikita Popov 22a5cde541 [SCEV] Separate out constant folding in mul expr creation
Separate out the code handling constant folding into a separate
block, that is independent of other folds that need a constant
first operand. Also make some minor adjustments to make the
constant folding look nearly identical to the same code in
getAddExpr().

The only reason this change is not strictly NFC is that the
C1*(C2+V) fold is moved below the constant folding, which means
that it now also applies to C1*C2*(C3+V), as it should.
2020-10-25 18:46:50 +01:00
Nikita Popov 0dda633317 [SCEV] Strength nowrap flags after constant folding
We should first try to constant fold the add expression and only
strengthen nowrap flags afterwards. This allows us to determine
stronger flags if e.g. only two operands are left after constant
folding (and thus "guaranteed no wrap region" code applies) or the
resulting operands are non-negative and thus nsw->nuw strengthening
applies.
2020-10-25 18:00:22 +01:00
Nikita Popov c5718253c9 [IndVars] Regenerate test checks (NFC)
Also run the test case through -instnamer.
2020-10-25 17:45:12 +01:00
Sanjay Patel e77ba263fe [InstSimplify] peek through 'not' operand in logic-of-icmps fold
This extends D78430 to solve cases like:
https://llvm.org/PR47858

There are still missed opportunities shown in the tests,
and as noted in the earlier patches, we have related
functionality in InstCombine, so we may want to extend
other folds in a similar way.

A semi-random sampling of test diff proofs in this patch:
https://rise4fun.com/Alive/sS4C
2020-10-25 11:13:30 -04:00
Sanjay Patel 7de2add829 [InstSimplify] add tests for logic-of-cmps with not op; NFC
One variant of this is shown in:
https://llvm.org/PR47858
2020-10-25 11:13:30 -04:00
Melanie Blower 576d436c82 Correct LIT test failure detected on buildbot after mibintc committed rG2e204e23911b: [clang] Enable support for #pragma STDC FENV_ACCESS D87528 2020-10-25 08:10:34 -07:00