Commit Graph

8 Commits

Author SHA1 Message Date
David Blaikie a79ac14fa6 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

llvm-svn: 230794
2015-02-27 21:17:42 +00:00
Daniel Sanders 1ede3002fa [mips][msa] Build all the tests in little and big endian modes and correct an incorrect test.
Summary:
This patch (correctly) breaks some MSA tests by exposing the cases when
SelectionDAG::getConstant() produces illegal types. These have been temporarily
marked XFAIL and the XFAIL flag will be removed when
SelectionDAG::getConstant() is fixed.

There are three categories of failure:
* Immediate instructions are not selected in one endian mode.
* Immediates used in ldi.[bhwd] must be different according to endianness.
  (this only affects cases where the 'wrong' ldi is used to load the correct
   bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...)))
* Non-immediate instructions that rely on immediates affected by the
  previous two categories as part of their match pattern.
  For example, the bset match pattern is the vector equivalent of
  'ws | (1 << wt)'.

One test needed correcting to expect different output depending on whether big
or little endian was in use. This test was
test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category
of failure shown above. The little endian version of this test is named
basic_operations_little.ll and will be merged back into basic_operations.ll in
a follow up commit now that FileCheck supports multiple check prefixes.

Reviewers: bkramer, jacksprat, dsanders

Reviewed By: dsanders

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1972

llvm-svn: 194806
2013-11-15 11:04:16 +00:00
Daniel Sanders 50e5ed3d08 [mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from normal IR (i.e. not intrinsics)
llvm-svn: 192438
2013-10-11 10:50:42 +00:00
Daniel Sanders 0210dd4b93 [mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intrinsics)
llvm-svn: 191737
2013-10-01 10:22:35 +00:00
Daniel Sanders 1b1e25b7c5 [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
llvm-svn: 191498
2013-09-27 10:08:31 +00:00
Daniel Sanders 3ce56622c8 [mips][msa] Added support for matching max, maxi, min, mini from normal IR (i.e. not intrinsics)
llvm-svn: 191291
2013-09-24 12:18:31 +00:00
Daniel Sanders 86d0c8d751 [mips][msa] Added support for matching addvi, and subvi from normal IR (i.e. not intrinsics)
llvm-svn: 191203
2013-09-23 14:29:55 +00:00
Daniel Sanders 7fab912257 [mips][msa] Added test cases that were supposed to be part of r190507, r190509, r190512, and r190518.
llvm-svn: 190522
2013-09-11 12:39:25 +00:00