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172 Commits

Author SHA1 Message Date
Krzysztof Parzyszek e8e754da74 [Hexagon] Register save/restore functions do not follow regular conventions 
Do not mark them as modifying any of the volatile registers by default.

llvm-svn: 267433
 2016-04-25 17:49:44 +00:00
Craig Topper 6e6a1f0a5b [Hexagon] Set ctlz_zero_undef/cttz_zero_undef to Expand so LegalizeDAG will convert them to ctlz/cttz. Remove the now unneccessary isel patterns. NFC 
llvm-svn: 267266
 2016-04-23 02:49:31 +00:00
Krzysztof Parzyszek 5ffee8d829 [Hexagon] Fix printing the address operand of S2_storerinewabs 
llvm-svn: 266811
 2016-04-19 20:20:33 +00:00
Krzysztof Parzyszek c9d4caa32c [Hexagon] Add support for run-time stack overflow checking 
Patch by Sundeep Kushwaha.

llvm-svn: 264328
 2016-03-24 20:20:07 +00:00
Krzysztof Parzyszek 181fdbd174 [Hexagon] Generate PIC-specific versions of save/restore routines 
In PIC mode, the registers R14, R15 and R28 are reserved for use by
the PLT handling code. This causes all functions to clobber these
registers. While this is not new for regular function calls, it does
also apply to save/restore functions, which do not follow the standard
ABI conventions with respect to the volatile/non-volatile registers.

Patch by Jyotsna Verma.

llvm-svn: 264324
 2016-03-24 19:18:48 +00:00
Krzysztof Parzyszek 6895b2ceb2 [Hexagon] Add support for __builtin_prefetch 
llvm-svn: 261210
 2016-02-18 13:58:38 +00:00
Krzysztof Parzyszek 73f1a40626 [Hexagon] Use zero-extending loads for anyext 
llvm-svn: 260895
 2016-02-15 16:01:01 +00:00
Krzysztof Parzyszek f49a8411f8 [Hexagon] Add implicit uses of GP to GP-relative loads and stores 
llvm-svn: 257337
 2016-01-11 15:49:58 +00:00
Krzysztof Parzyszek 21dc8bdd9e [Hexagon] Add PIC support 
llvm-svn: 256025
 2015-12-18 20:19:30 +00:00
Krzysztof Parzyszek de25ecfa62 [Hexagon] Remove TFRI_V4 instruction, use existing A2_tfrsi instead 
llvm-svn: 254539
 2015-12-02 19:44:35 +00:00
Krzysztof Parzyszek 29d23f9f4c [Hexagon] Update instruction formats 
llvm-svn: 253867
 2015-11-23 14:09:26 +00:00
Colin LeMahieu b7a5f9fc29 [Hexagon] Fixing store instructions and reenabling a few more tests. 
llvm-svn: 252561
 2015-11-10 00:22:00 +00:00
Colin LeMahieu 8ab7e8e1b5 [Hexagon] Fixing load instruction parsing and reenabling tests. 
llvm-svn: 252555
 2015-11-10 00:02:27 +00:00
Krzysztof Parzyszek 26b2c9080f [Hexagon] Fix isNVStorable flag in .td files 
An upper half and a double word cannot be used as value sources in a
new-value store.

llvm-svn: 250867
 2015-10-20 22:40:57 +00:00
Krzysztof Parzyszek 05da79d5ac [Hexagon] Remove the remnants of isConstExtProfitable 
llvm-svn: 250845
 2015-10-20 19:04:53 +00:00
Colin LeMahieu be8c453d58 [Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing. 
llvm-svn: 239161
 2015-06-05 16:00:11 +00:00
Colin LeMahieu c40be85adc Revert r239095 incorrect test tree. 
llvm-svn: 239102
 2015-06-04 21:32:42 +00:00
Colin LeMahieu fc52c11d80 [Hexagon] Adding functionality for duplexing. Duplexing is a way to compress commonly used pairs of instructions in order to reduce code size. The test case duplex.ll normally would be 8 bytes, assign register to 0 and jump to link register. After duplexing this is only 4 bytes. This also tests the HexagonMCShuffler code path which is used to make sure duplexed instructions still follow slot requirements. 
llvm-svn: 239095
 2015-06-04 21:16:16 +00:00
Sergey Dmitrouk 842a51bad8 Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes" 
[DebugInfo] Add debug locations to constant SD nodes

This adds debug location to constant nodes of Selection DAG and updates
all places that create constants to pass debug locations
(see PR13269).

Can't guarantee that all locations are correct, but in a lot of cases choice
is obvious, so most of them should be. At least all tests pass.

Tests for these changes do not cover everything, instead just check it for
SDNodes, ARM and AArch64 where it's easy to get incorrect locations on
constants.

This is not complete fix as FastISel contains workaround for wrong debug
locations, which drops locations from instructions on processing constants,
but there isn't currently a way to use debug locations from constants there
as llvm::Constant doesn't cache it (yet). Although this is a bit different
issue, not directly related to these changes.

Differential Revision: http://reviews.llvm.org/D9084

llvm-svn: 235989
 2015-04-28 14:05:47 +00:00
Daniel Jasper 48e93f7181 Revert "[DebugInfo] Add debug locations to constant SD nodes" 
This breaks a test:
http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/23870

llvm-svn: 235987
 2015-04-28 13:38:35 +00:00
Sergey Dmitrouk adb4c69d5c [DebugInfo] Add debug locations to constant SD nodes 
This adds debug location to constant nodes of Selection DAG and updates
all places that create constants to pass debug locations
(see PR13269).

Can't guarantee that all locations are correct, but in a lot of cases choice
is obvious, so most of them should be. At least all tests pass.

Tests for these changes do not cover everything, instead just check it for
SDNodes, ARM and AArch64 where it's easy to get incorrect locations on
constants.

This is not complete fix as FastISel contains workaround for wrong debug
locations, which drops locations from instructions on processing constants,
but there isn't currently a way to use debug locations from constants there
as llvm::Constant doesn't cache it (yet). Although this is a bit different
issue, not directly related to these changes.

Differential Revision: http://reviews.llvm.org/D9084

llvm-svn: 235977
 2015-04-28 11:56:37 +00:00
Krzysztof Parzyszek 952d951418 [Hexagon] Some cleanup of instruction selection code 
llvm-svn: 235552
 2015-04-22 21:17:00 +00:00
Krzysztof Parzyszek cd97c985c7 [Hexagon] Use A2_tfrsi for constant pool and jump table addresses 
llvm-svn: 235535
 2015-04-22 18:25:53 +00:00
Krzysztof Parzyszek 499bc5faa1 [Hexagon] Patterns for frame index with offset for isel 
llvm-svn: 235418
 2015-04-21 21:28:03 +00:00
Krzysztof Parzyszek a29622a8c5 Remove unused complex patterns for addressing modes on Hexagon. 
llvm-svn: 232057
 2015-03-12 16:44:50 +00:00
Krzysztof Parzyszek 6d5a4b5dcd Eliminate constant-extender profitability checks from Hexagon isel 
llvm-svn: 231992
 2015-03-12 00:19:59 +00:00
Colin LeMahieu bdc6c83d24 [Hexagon] Adding frame index + add load/store patterns. 
llvm-svn: 231850
 2015-03-10 21:24:13 +00:00
Colin LeMahieu 3901c066e0 [Hexagon] Simplifying deallocret definitions. 
llvm-svn: 231847
 2015-03-10 21:12:32 +00:00
Colin LeMahieu 4e90d2136f [Hexagon] Separating InstHexagon from OpcodeHexagon. 
llvm-svn: 231844
 2015-03-10 20:56:22 +00:00
Colin LeMahieu 60a99e66a0 [Hexagon] Adding nodes for PIC support. 
llvm-svn: 231829
 2015-03-10 20:04:44 +00:00
Colin LeMahieu 092d9c18a8 [Hexagon] Adding DuplexInst instruction format and duplex class defs. 
llvm-svn: 231828
 2015-03-10 19:53:14 +00:00
Colin LeMahieu 96bfaa9766 [Hexagon] Eliminating immediate condition set. 
llvm-svn: 231693
 2015-03-09 19:57:18 +00:00
Colin LeMahieu 404d5b242d [Hexagon] Adding vector load with post-increment instructions. Adding decoder function for 64bit control register class. 
llvm-svn: 228708
 2015-02-10 16:59:36 +00:00
Colin LeMahieu 328b1633d7 [Hexagon] Adding missing load instructions and removing an unused multiclass parameter. 
llvm-svn: 228630
 2015-02-09 23:45:24 +00:00
Colin LeMahieu 4282e7cffd [Hexagon] Factoring classes out of some load patterns and deleting some unused ones. 
llvm-svn: 228627
 2015-02-09 23:05:44 +00:00
Colin LeMahieu 4fd203d3e1 [Hexagon] Removing more V4 predicates since V4 is the required minimum. 
llvm-svn: 228614
 2015-02-09 21:56:37 +00:00
Colin LeMahieu 641c24b9bf [Hexagon] Removing v2-4 flags. V4 is the minimum supported version. 
llvm-svn: 228605
 2015-02-09 21:07:35 +00:00
Colin LeMahieu 38e6689276 [Hexagon] Cleaning up definition formatting. 
llvm-svn: 228593
 2015-02-09 19:24:44 +00:00
Colin LeMahieu 6e3e62fd13 [Hexagon] Renaming v4 compare-and-jump instructions. 
llvm-svn: 228349
 2015-02-05 22:03:32 +00:00
Colin LeMahieu a66cf6f2df [Hexagon] Since decoding conflicts have been resolved, isCodeGenOnly = 0 by default and remove explicitly setting it. 
llvm-svn: 228316
 2015-02-05 17:32:17 +00:00
Colin LeMahieu ceebe8659b [Hexagon] Deleting unused instructions and adding isCodeGenOnly to some defs. 
llvm-svn: 228238
 2015-02-05 00:10:16 +00:00
Colin LeMahieu 9cb9078ccf [Hexagon] Updating load extend to i64 patterns. 
llvm-svn: 228237
 2015-02-04 23:55:16 +00:00
Colin LeMahieu 712d5c393b [Hexagon] Cleaning up i1 load and extension patterns. 
llvm-svn: 228232
 2015-02-04 23:27:48 +00:00
Colin LeMahieu 90a91bbf43 [Hexagon] Simplifying more load and store patterns and using new addressing patterns. 
llvm-svn: 228231
 2015-02-04 23:23:16 +00:00
Colin LeMahieu ad13d4e8a6 [Hexagon] Simplifying some load and store patterns. 
llvm-svn: 228227
 2015-02-04 23:10:21 +00:00
Colin LeMahieu 68292c96da [Hexagon] Converting absolute-address load patterns to use AddrGP. 
llvm-svn: 228225
 2015-02-04 22:54:51 +00:00
Colin LeMahieu 8bf5de10c3 [Hexagon] Converting atomic store/load to use AddrGP addressing. 
llvm-svn: 228223
 2015-02-04 22:40:36 +00:00
Colin LeMahieu 5149135369 [Hexagon] Simplifying some store patterns. Adding AddrGP addressing forms. 
llvm-svn: 228220
 2015-02-04 22:36:28 +00:00
Colin LeMahieu 987b0943c8 [Hexagon] Adding selection for GlobalAddress and converting [z/i]ext load patterns to make use of them. 
llvm-svn: 228184
 2015-02-04 20:38:01 +00:00
Colin LeMahieu 86abe35ceb [Hexagon] Replacing some load patterns with cleaner versions. 
llvm-svn: 228169
 2015-02-04 19:05:32 +00:00