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5 Commits

Author SHA1 Message Date
Andrew Kaylor 5b444a21df Add optimization bisect opt-in calls for Hexagon passes 
Differential Revision: http://reviews.llvm.org/D19509

llvm-svn: 267593
 2016-04-26 19:46:28 +00:00
Derek Schuff 1dbf7a571f Add MachineFunctionProperty checks for AllVRegsAllocated for target passes 
Summary:
This adds the same checks that were added in r264593 to all
target-specific passes that run after register allocation.

Reviewers: qcolombet

Subscribers: jyknight, dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18525

llvm-svn: 265313
 2016-04-04 17:09:25 +00:00
Duncan P. N. Exon Smith f9ab416d70 WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFC 
Update APIs in MachineInstrBundle.h to take and return MachineInstr&
instead of MachineInstr* when the instruction cannot be null.  Besides
being a nice cleanup, this is tacking toward a fix for PR26753.

llvm-svn: 262141
 2016-02-27 17:05:33 +00:00
Craig Topper e5e035a3a8 Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical register arrays already use this typedef. 
llvm-svn: 254843
 2015-12-05 07:13:35 +00:00
Krzysztof Parzyszek 921722049d [Hexagon] Generate MUX from conditional transfers when dot-new not possible 
llvm-svn: 242711
 2015-07-20 21:23:25 +00:00