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13688 Commits

Author SHA1 Message Date
Evan Cheng e4f97ccf7f X86 SSE2 supports v8i16 multiplication 
llvm-svn: 27644
 2006-04-13 05:10:25 +00:00
Evan Cheng d2eb662415 Update 
llvm-svn: 27643
 2006-04-13 05:09:45 +00:00
Evan Cheng b3fe00bdc6 padds{b|w}, paddus{b|w}, psubs{b|w}, psubus{b|w} intrinsics. 
llvm-svn: 27639
 2006-04-13 00:43:35 +00:00
Evan Cheng 0aab735a1a Naming inconsistency. 
llvm-svn: 27638
 2006-04-13 00:00:23 +00:00
Evan Cheng c88afc36a9 SSE / SSE2 conversion intrinsics. 
llvm-svn: 27637
 2006-04-12 23:42:44 +00:00
Evan Cheng 92232307d0 All "integer" logical ops (pand, por, pxor) are now promoted to v2i64. 
Clean up and fix various logical ops issues.

llvm-svn: 27633
 2006-04-12 21:21:57 +00:00
Evan Cheng 119266ea92 Promote vector AND, OR, and XOR 
llvm-svn: 27632
 2006-04-12 21:20:24 +00:00
Reid Spencer 7c8fef2cd1 Make sure CVS versions of yacc and lex files get distributed. 
llvm-svn: 27630
 2006-04-12 20:57:05 +00:00
Reid Spencer 13a1a7a4a6 Get rid of a signed/unsigned compare warning. 
llvm-svn: 27625
 2006-04-12 19:28:15 +00:00
Chris Lattner 147e50e1c5 Add a new way to match vector constants, which make it easier to bang bits of 
different types.

Codegen spltw(0x7FFFFFFF) and spltw(0x80000000) without a constant pool load,
implementing PowerPC/vec_constants.ll:test1.  This compiles:

typedef float vf __attribute__ ((vector_size (16)));
typedef int vi __attribute__ ((vector_size (16)));
void test(vi *P1, vi *P2, vf *P3) {
  *P1 &= (vi){0x80000000,0x80000000,0x80000000,0x80000000};
  *P2 &= (vi){0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF};
  *P3 = vec_abs((vector float)*P3);
}

to:

_test:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        vspltisw v0, -1
        vslw v0, v0, v0
        lvx v1, 0, r3
        vand v1, v1, v0
        stvx v1, 0, r3
        lvx v1, 0, r4
        vandc v1, v1, v0
        stvx v1, 0, r4
        lvx v1, 0, r5
        vandc v0, v1, v0
        stvx v0, 0, r5
        mtspr 256, r2
        blr

instead of (with two constant pool entries):

_test:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        li r6, lo16(LCPI1_0)
        lis r7, ha16(LCPI1_0)
        li r8, lo16(LCPI1_1)
        lis r9, ha16(LCPI1_1)
        lvx v0, r7, r6
        lvx v1, 0, r3
        vand v0, v1, v0
        stvx v0, 0, r3
        lvx v0, r9, r8
        lvx v1, 0, r4
        vand v1, v1, v0
        stvx v1, 0, r4
        lvx v1, 0, r5
        vand v0, v1, v0
        stvx v0, 0, r5
        mtspr 256, r2
        blr

GCC produces (with 2 cp entries):

_test:
        mfspr r0,256
        stw r0,-4(r1)
        oris r0,r0,0xc00c
        mtspr 256,r0
        lis r2,ha16(LC0)
        lis r9,ha16(LC1)
        la r2,lo16(LC0)(r2)
        lvx v0,0,r3
        lvx v1,0,r5
        la r9,lo16(LC1)(r9)
        lwz r12,-4(r1)
        lvx v12,0,r2
        lvx v13,0,r9
        vand v0,v0,v12
        stvx v0,0,r3
        vspltisw v0,-1
        vslw v12,v0,v0
        vandc v1,v1,v12
        stvx v1,0,r5
        lvx v0,0,r4
        vand v0,v0,v13
        stvx v0,0,r4
        mtspr 256,r12
        blr

llvm-svn: 27624
 2006-04-12 19:07:14 +00:00
Chris Lattner b19a5c661b Turn casts into getelementptr's when possible. This enables SROA to be more 
aggressive in some cases where LLVMGCC 4 is inserting casts for no reason.

This implements InstCombine/cast.ll:test27/28.

llvm-svn: 27620
 2006-04-12 18:09:35 +00:00
Reid Spencer 175d57c4bc Don't emit useless warning messages. 
llvm-svn: 27617
 2006-04-12 17:56:16 +00:00
Chris Lattner 74cf9ff761 Rename get_VSPLI_elt -> get_VSPLTI_elt 
Canonicalize BUILD_VECTOR's that match VSPLTI's into a single type for each
form, eliminating a bunch of Pat patterns in the .td file and allowing us to
CSE stuff more aggressively.  This implements
PowerPC/buildvec_canonicalize.ll:VSPLTI

llvm-svn: 27614
 2006-04-12 17:37:20 +00:00
Evan Cheng e2157c6e41 Promote v4i32, v8i16, v16i8 load to v2i64 load. 
llvm-svn: 27612
 2006-04-12 17:12:36 +00:00
Chris Lattner e318a7574e Ensure that zero vectors are always v4i32, which forces them to CSE with 
each other.  This implements CodeGen/PowerPC/vxor-canonicalize.ll

llvm-svn: 27609
 2006-04-12 16:53:28 +00:00
Evan Cheng be8a8933e6 Vector type promotion for ISD::LOAD and ISD::SELECT 
llvm-svn: 27606
 2006-04-12 16:33:18 +00:00
Chris Lattner d3b504ae10 Implement support for the formal_arguments node. To get this, targets shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload 
llvm-svn: 27604
 2006-04-12 16:20:43 +00:00
Evan Cheng 29be057d92 Various SSE2 conversion intrinsics 
llvm-svn: 27603
 2006-04-12 05:20:24 +00:00
Chris Lattner 417b96b6dd Don't memoize vloads in the load map! Don't memoize them anywhere here, let 
getNode do it.  This fixes CodeGen/Generic/2006-04-11-vecload.ll

llvm-svn: 27602
 2006-04-12 03:25:41 +00:00
Evan Cheng 70c74a3ced Added __builtin_ia32_storelv4si, __builtin_ia32_movqv4si, 
__builtin_ia32_loadlv4si, __builtin_ia32_loaddqu, __builtin_ia32_storedqu.

llvm-svn: 27599
 2006-04-11 22:28:25 +00:00
Nate Begeman f19bcd5177 Fix SingleSource/UnitTests/Vector/sumarray-dbl 
llvm-svn: 27594
 2006-04-11 19:44:43 +00:00
Nate Begeman 1bb132099f Fix PR727, correctly handling large stack aligments on ppc 
llvm-svn: 27593
 2006-04-11 19:29:21 +00:00
Chris Lattner aaa04230bd we have a shuffle instr, add an example. 
llvm-svn: 27592
 2006-04-11 18:47:03 +00:00
Evan Cheng 6b60357f4a gcc lower SSE prefetch into generic prefetch intrinsic. Need to add support 
later.

llvm-svn: 27591
 2006-04-11 18:04:57 +00:00
Evan Cheng 6ea715af28 Misc. intrinsics. 
llvm-svn: 27590
 2006-04-11 17:35:57 +00:00
Jim Laskey 02b3b72bfc Suppress debug label when not debug. 
llvm-svn: 27588
 2006-04-11 08:11:53 +00:00
Evan Cheng 09a956271a movnt* and maskmovdqu intrinsics 
llvm-svn: 27587
 2006-04-11 06:57:30 +00:00
Evan Cheng 7256b0ae05 Only get Tmp2 for cases where number of operands is > 1. Fixed return void. 
llvm-svn: 27586
 2006-04-11 06:33:39 +00:00
Chris Lattner 6cf3bbbe17 add some todos 
llvm-svn: 27580
 2006-04-11 02:00:08 +00:00
Chris Lattner e4db08a2f1 Vector function results go into V2 according to GCC. The darwin ABI doc 
doesn't say where they go :-/

llvm-svn: 27579
 2006-04-11 01:38:39 +00:00
Chris Lattner 2eb22eef7d Add basic support for legalizing returns of vectors 
llvm-svn: 27578
 2006-04-11 01:31:51 +00:00
Chris Lattner 92533cfb4a Move some return-handling code from lowerarguments to the ISD::RET handling stuff. 
No functionality change.

llvm-svn: 27577
 2006-04-11 01:21:43 +00:00
Evan Cheng 12ba3e23d0 Added support for _mm_move_ss and _mm_move_sd. 
llvm-svn: 27575
 2006-04-11 00:19:04 +00:00
Jim Laskey dca2655daa Use existing information. 
llvm-svn: 27574
 2006-04-10 23:09:19 +00:00
Chris Lattner 2d37f920ad Implement vec_shuffle.ll:test3 
llvm-svn: 27573
 2006-04-10 23:06:36 +00:00
Chris Lattner fbb77a408b Implement InstCombine/vec_shuffle.ll:test[12] 
llvm-svn: 27571
 2006-04-10 22:45:52 +00:00
Evan Cheng f8ac02283c Remove some bogus patterns; clean up. 
llvm-svn: 27569
 2006-04-10 22:35:16 +00:00
Chris Lattner d99f57c1e1 add a note 
llvm-svn: 27567
 2006-04-10 21:51:03 +00:00
Evan Cheng 051de9a82b Remove an entry that is now done. 
llvm-svn: 27565
 2006-04-10 21:42:57 +00:00
Evan Cheng 76112c3cb8 Added some missing shuffle patterns. 
llvm-svn: 27564
 2006-04-10 21:42:19 +00:00
Evan Cheng 664fcba5fa Correct an entry 
llvm-svn: 27563
 2006-04-10 21:41:39 +00:00
Evan Cheng 395fa3d2a6 movups / movupd 
llvm-svn: 27562
 2006-04-10 21:11:06 +00:00
Andrew Lenharth a9cdcca3c3 Add a simple pass to make sure that all (non-library) calls to malloc and free 
are visible to analysis as intrinsics.  That is, make sure someone doesn't pass
free around by address in some struct (as happens in say 176.gcc).

This doesn't get rid of any indirect calls, just ensure calls to free and malloc
are always direct.

llvm-svn: 27560
 2006-04-10 19:26:09 +00:00
Evan Cheng cb73b8d419 Missing break 
llvm-svn: 27559
 2006-04-10 18:54:36 +00:00
Evan Cheng 617a6a812e Conditional move of vector types. 
llvm-svn: 27556
 2006-04-10 07:23:14 +00:00
Evan Cheng 014849e121 New entries 
llvm-svn: 27555
 2006-04-10 07:22:03 +00:00
Evan Cheng c9ed8e4c1a Use movaps to do VR128 reg-to-reg copies for now. It's shorter and available for SSE1. 
llvm-svn: 27554
 2006-04-10 07:21:31 +00:00
Chris Lattner 3a68f3c3ca properly mark vector selects as expanded to select_cc 
llvm-svn: 27544
 2006-04-08 22:59:15 +00:00
Chris Lattner 0a3d1bbca4 Add VRRC select support 
llvm-svn: 27543
 2006-04-08 22:45:08 +00:00
Chris Lattner 02274a5265 Add code generator support for VSELECT 
llvm-svn: 27542
 2006-04-08 22:22:57 +00:00