5edb03ee57
ARM Binary encoding information for BFC/BFI instructions.
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llvm-svn: 117072
2010-10-21 22:03:21 +00:00
2bfa8ed045
Move the encoding logic for Q registers into getMachineOpValue().
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llvm-svn: 117060
2010-10-21 20:49:13 +00:00
68a335e185
ARM mode encoding information for UBFX and SBFX instructions.
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llvm-svn: 116588
2010-10-15 17:15:16 +00:00
6f52f8a87d
Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
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here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
llvm-svn: 116471
2010-10-14 02:33:26 +00:00
1e7db68774
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
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llvm-svn: 116421
2010-10-13 19:56:10 +00:00
efd5369749
Add the rest of the ARM so_reg encoding options (register shifted register)
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and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.
llvm-svn: 116377
2010-10-12 23:53:58 +00:00
12e493ace4
Move the ARM so_imm encoding into a custom operand encoder and remove the
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explicit handling of the instructions referencing it from the MC code
emitter.
llvm-svn: 116367
2010-10-12 23:18:08 +00:00
d9d31dafda
Add custom encoder for the 's' bit denoting whether an ARM arithmetic
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instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.
llvm-svn: 116360
2010-10-12 23:00:24 +00:00
0e57a9f7a9
Add MOVi ARM encoding.
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llvm-svn: 116321
2010-10-12 18:09:12 +00:00
feeae27ad9
Nuke unused wrapper function.
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llvm-svn: 116318
2010-10-12 17:53:25 +00:00
6fead930af
Add encoding information for the remainder of the generic arithmetic
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ARM instructions.
llvm-svn: 116313
2010-10-12 17:11:26 +00:00
b7c2962d20
MC machine encoding for simple aritmetic instructions that use a shifted
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register operand.
llvm-svn: 116259
2010-10-11 23:16:21 +00:00
c43c930690
Implement a few more binary encoding bits. Still very early stage proof-of-
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concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
llvm-svn: 116112
2010-10-08 21:45:55 +00:00
b770c00610
Reapply 116059, this time without the fatfingered pasto at the top.
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''const'ify getMachineOpValue() and associated helpers.'
llvm-svn: 116067
2010-10-08 17:45:54 +00:00
00351b7731
Reverting 116059. Bots are unhappy with it.
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llvm-svn: 116064
2010-10-08 17:28:40 +00:00
e2d30cd4b5
'const'ify getMachineOpValue() and associated helpers.
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llvm-svn: 116059
2010-10-08 16:52:44 +00:00
0bb2f9afa9
Enable binary encoding of some simple instructions.
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llvm-svn: 116022
2010-10-08 00:39:21 +00:00
a7b6d58f45
Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
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llvm-svn: 116018
2010-10-08 00:21:28 +00:00
91029094e0
Trivial MC code emitter shell. No instruction forms actually handled yet.
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llvm-svn: 115993
2010-10-07 22:12:50 +00:00
8aed386d82
Include the auto-generated bits for machine encoding.
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llvm-svn: 115987
2010-10-07 21:57:55 +00:00
07b5b1802e
ARM instruction don't have instruction prefixes, so remove the helper functions
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for them from the MCCodeEmitter.
llvm-svn: 115975
2010-10-07 20:41:30 +00:00
abf60e3421
Fix build.
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llvm-svn: 114292
2010-09-18 17:54:37 +00:00
1287f4f3b8
Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim!
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llvm-svn: 114195
2010-09-17 18:46:17 +00:00
Jim Grosbach