2dded8302a
Add accessor for 64bit flag, so that we can tell when it is safe to
...
generate the fun in-register fp<->long instructions.
llvm-svn: 23244
2005-09-06 15:30:12 +00:00
d23739d020
Next round of DAGCombiner changes. This version now passes all the tests
...
I have run so far when run before Legalize. It still needs to pick up the
SetCC folds, and nodes that use SetCC.
llvm-svn: 23243
2005-09-06 04:43:02 +00:00
c8bd5bda59
revert part of the last change, should fix regressions
...
llvm-svn: 23241
2005-09-04 06:12:19 +00:00
aa833d4571
explicitly specify an operands list for patterns with inputs (e.g. neg)
...
llvm-svn: 23240
2005-09-03 01:28:40 +00:00
8ae9525bd0
include the dag isel fragment
...
llvm-svn: 23239
2005-09-03 01:17:22 +00:00
0442dcfabc
ask for a dag isel
...
llvm-svn: 23238
2005-09-03 01:15:41 +00:00
821628ff2a
Fix a checking failure in gs
...
llvm-svn: 23235
2005-09-03 01:04:40 +00:00
5f12cf14be
Change the isel to not break out of the big giant switch. Instead, the
...
switch should never be exited, so its bottom is now unreachable.
llvm-svn: 23234
2005-09-03 00:53:47 +00:00
9220f92c41
rearrange logical ops to group them together more consistently.
...
Define the PatFrag class which can be used to define subpatterns to match
things with. Define 'not', and use it to define the patterns for andc,
nand, etc.
llvm-svn: 23233
2005-09-03 00:21:51 +00:00
dcbb561b76
Add AND/OR/XOR
...
llvm-svn: 23232
2005-09-02 22:35:53 +00:00
7cea6ef16e
Next round of DAG Combiner changes. Just need to support multiple return
...
values, and then we should be able to hook it up.
llvm-svn: 23231
2005-09-02 21:18:40 +00:00
3a1002d529
Add some initial patterns to simple binary instructions, though they
...
currently don't do anything. This elides patterns for binary operators
that ping on the carry flag, since we don't model it yet.
This patch also removes PPC::SUB, because it is dead.
llvm-svn: 23230
2005-09-02 21:18:00 +00:00
1a570f1fe4
Clean up some code from the last checkin
...
llvm-svn: 23229
2005-09-02 20:32:45 +00:00
630226697f
Fix a bug in legalize where it would emit two calls to libcalls that return
...
i64 values on targets that need that expanded to 32-bit registers. This fixes
PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll and speeds up 189.lucas from
taking 122.72s to 81.96s on my desktop.
llvm-svn: 23228
2005-09-02 20:26:58 +00:00
06e237f253
turn on dag isel by default
...
llvm-svn: 23226
2005-09-02 19:53:54 +00:00
b95b280bee
Make sure to auto-cse nullary ops
...
llvm-svn: 23224
2005-09-02 19:36:17 +00:00
27d628dfc9
Add help support for -mcpu and -mattr.
...
llvm-svn: 23222
2005-09-02 19:27:43 +00:00
1e89e36dcd
Fix some buggy logic where we would try to remove nodes with two operands
...
from the binary ops map, even if they had multiple results. This latent bug
caused a few failures with the dag isel last night.
To prevent stuff like this from happening in the future, add some really
strict checking to make sure that the CSE maps always match up with reality!
llvm-svn: 23221
2005-09-02 19:15:44 +00:00
9690a4f321
Pull out Lowering in preperation for multiple ISels. Oh, and get rid of some stuff
...
llvm-svn: 23220
2005-09-02 18:46:02 +00:00
b0b4ec5655
Don't create zero sized stack objects even for array allocas with a zero
...
number of elements.
llvm-svn: 23219
2005-09-02 18:41:28 +00:00
aa3b1fcc58
Decouple fsqrt from gpul optimizations, implementing fsqrt.ll.
...
Remove the -enable-gpopt option which is subsumed by feature flags.
llvm-svn: 23218
2005-09-02 18:33:05 +00:00
b6cde17d29
Fix the release build, noticed by Eric van Riet Paap
...
llvm-svn: 23215
2005-09-02 07:09:28 +00:00
b5e381a8cf
Fix a problem that Dan Berlin noticed, where reassociation would not succeed
...
in building maximal expressions before simplifying them. In particular, i
cases like this:
X-(A+B+X)
the code would consider A+B+X to be a maximal expression (not understanding
that the single use '-' would be turned into a + later), simplify it (a noop)
then later get simplified again.
Each of these simplify steps is where the cost of reassociation comes from,
so this patch should speed up the already fast pass a bit.
Thanks to Dan for noticing this!
llvm-svn: 23214
2005-09-02 07:07:58 +00:00
9fe263aa75
Avoid creating garbage instructions, just move the old add instruction
...
to where we need it when converting -(A+B+C) -> -A + -B + -C.
llvm-svn: 23213
2005-09-02 06:38:04 +00:00
d1325da091
add some assertions and fix problems where reassociate could access the
...
Ops vector out of range
llvm-svn: 23211
2005-09-02 05:23:22 +00:00
a6dde9962d
Fix VC++ build errors
...
llvm-svn: 23210
2005-09-02 02:51:42 +00:00
763a3a0fa7
Restore this patch now that the latent bug has been fixed
...
llvm-svn: 23209
2005-09-02 01:24:55 +00:00
d9af1aab51
Make sure to legalize assert[zs]ext's operand correctly
...
llvm-svn: 23208
2005-09-02 01:15:01 +00:00
06d440f2ee
Revert the previous patch which causes a mysterious regression in toast.
...
llvm-svn: 23207
2005-09-02 00:47:05 +00:00
7138f91424
Teach live intervals to not crash on dead livein regs
...
llvm-svn: 23206
2005-09-02 00:20:32 +00:00
a66403dbf7
For values that are live across basic blocks and need promotion, use ANY_EXTEND
...
instead of ZERO_EXTEND to eliminate extraneous extensions. This eliminates
dead zero extensions on formal arguments and other cases on PPC, implementing
the newly tightened up test/Regression/CodeGen/PowerPC/small-arguments.ll test.
llvm-svn: 23205
2005-09-02 00:19:37 +00:00
7753f175e6
legalize ANY_EXTEND appropriately
...
llvm-svn: 23204
2005-09-02 00:18:10 +00:00
8c393c218b
Add support for ANY_EXTEND and add a few minor folds for it
...
llvm-svn: 23203
2005-09-02 00:17:32 +00:00
210975cfbb
Handle any_extend like zext
...
llvm-svn: 23202
2005-09-02 00:16:09 +00:00
2493f0e5fd
Handle ANY_EXTEND like ZERO_EXTEND. Simplify the extend/truncate code on
...
the observation that it only has to handle i1 -> i64 and i64 -> i1.
llvm-svn: 23201
2005-09-02 00:15:30 +00:00
9ee867b93b
Implement small-arguments.ll:test3 by teaching the DAG optimizer that
...
the results of calls to functions returning small values are properly
sign/zero extended.
llvm-svn: 23198
2005-09-01 23:44:32 +00:00
d78d975437
Fix some code in the current node combining code, spotted when it was moved
...
over to DAGCombiner.cpp
1. Don't assume that SetCC returns i1 when folding (xor (setcc) constant)
2. Don't duplicate code in folding AND with AssertZext that is handled by
MaskedValueIsZero
llvm-svn: 23196
2005-09-01 23:25:49 +00:00
2504fe2613
Implement first round of feedback from chris (there's still a couple things
...
left to do).
llvm-svn: 23195
2005-09-01 23:24:04 +00:00
68d15fdfea
Align functions to 16-byte boundaries, to eliminate noise in performance measurements. This improves the performance of 'treeadd' by about 20% with the dag
...
isel, restoring it to the pattern-isel level (which happens to get the alignment right).
llvm-svn: 23194
2005-09-01 23:08:50 +00:00
e40a3ccd60
Local labels on darwin apparently start with just 'L', not .L like other
...
platforms. This reduces executable size and makes shark realize the actual
bounds of functions instead of showing each MBB as a function :)
llvm-svn: 23193
2005-09-01 21:48:35 +00:00
19058c3989
1. Use SubtargetFeatures in llc/lli.
...
2. Propagate feature "string" to all targets.
3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget.
llvm-svn: 23192
2005-09-01 21:38:21 +00:00
3fee6a51a9
This new class provides support for platform specific "features". The intent
...
is to manage processor specific attributes from the command line. See examples
of use in llc/lli and PowerPCTargetSubtarget.
llvm-svn: 23191
2005-09-01 21:36:18 +00:00
a305d28cf6
Implement dynamic allocas correctly. In particular, because we were copying
...
directly out of R1 (without using a CopyFromReg, which uses a chain), multiple
allocas were getting CSE'd together, producing bogus code. For this:
int %foo(bool %X, int %A, int %B) {
br bool %X, label %T, label %F
F:
%G = alloca int
%H = alloca int
store int %A, int* %G
store int %B, int* %H
%R = load int* %G
ret int %R
T:
ret int 0
}
We were generating:
_foo:
stwu r1, -16(r1)
stw r31, 4(r1)
or r31, r1, r1
stw r1, 12(r31)
cmpwi cr0, r3, 0
bne cr0, .LBB_foo_2 ; T
.LBB_foo_1: ; F
li r2, 16
subf r2, r2, r1 ;; One alloca
or r1, r2, r2
or r3, r1, r1
or r1, r2, r2
or r2, r1, r1
stw r4, 0(r3)
stw r5, 0(r2)
lwz r3, 0(r3)
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
.LBB_foo_2: ; T
li r3, 0
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
Now we generate:
_foo:
stwu r1, -16(r1)
stw r31, 4(r1)
or r31, r1, r1
stw r1, 12(r31)
cmpwi cr0, r3, 0
bne cr0, .LBB_foo_2 ; T
.LBB_foo_1: ; F
or r2, r1, r1
li r3, 16
subf r2, r3, r2 ;; Alloca 1
or r1, r2, r2
or r2, r1, r1
or r6, r1, r1
subf r3, r3, r6 ;; Alloca 2
or r1, r3, r3
or r3, r1, r1
stw r4, 0(r2)
stw r5, 0(r3)
lwz r3, 0(r2)
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
.LBB_foo_2: ; T
li r3, 0
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
This fixes Povray and SPASS with the dag isel, the last two failing cases.
Tommorow we will hopefully turn it on by default! :)
llvm-svn: 23190
2005-09-01 21:31:30 +00:00
293b3a68e0
Fix a bug where we were useing HA to get the high part, which seems like it
...
could cause a miscompile. Fixing this didn't fix the two programs that fail
though. :(
This also changes the implementation to follow the pattern selector more
closely, causing us to select 0 to li instead of lis.
llvm-svn: 23189
2005-09-01 19:38:28 +00:00
34182aff7f
Do not select the operands being passed into SelectCC. IT does this itself
...
and selecting early prevents folding immediates into the cmpw* instructions
llvm-svn: 23188
2005-09-01 19:20:44 +00:00
975f5c9f46
It is NDEBUG not _NDEBUG
...
llvm-svn: 23186
2005-09-01 18:44:10 +00:00
e8f78d1aab
Add the rest of the currently implemented visit routines to the switch
...
statement in visit().
llvm-svn: 23185
2005-09-01 00:33:32 +00:00
21158fc485
First pass at the DAG Combiner. It isn't used anywhere yet, but it should
...
be mostly functional. It currently has all folds from SelectionDAG.cpp
that do not involve a condition code.
llvm-svn: 23184
2005-09-01 00:19:25 +00:00
d4d10fff99
If a function has live ins/outs, print them
...
llvm-svn: 23181
2005-08-31 22:34:59 +00:00
da2e04c69d
Move FCTIWZ handling out of the instruction selectors and into legalization,
...
getting them out of the business of making stack slots.
llvm-svn: 23180
2005-08-31 21:09:52 +00:00
6bad1fb19e
Remove dead code
...
llvm-svn: 23179
2005-08-31 20:25:15 +00:00
e675a08e10
Move SHL,SHR i64 -> legalizer
...
llvm-svn: 23178
2005-08-31 20:23:54 +00:00
3a04a4b767
Remove code that is now dead from the pattern isel.
...
llvm-svn: 23177
2005-08-31 19:11:36 +00:00
2f03896a0f
lower sra_parts on the dag, implementing it for the dag isel, and exposing
...
the ops to dag optimization.
llvm-svn: 23176
2005-08-31 19:09:57 +00:00
8a1a5f2818
Allow targets to custom expand shifts that are too large for their registers
...
llvm-svn: 23173
2005-08-31 19:01:53 +00:00
2bd2af8ecd
add assert zext/sext to the dag isel
...
llvm-svn: 23171
2005-08-31 18:08:46 +00:00
46ff6aa993
Handle AssertSext/AssertZext nodes, fixing the regressions last night.
...
llvm-svn: 23170
2005-08-31 17:48:04 +00:00
d8c84e3c7e
Fix VC++ precedence warnings
...
llvm-svn: 23169
2005-08-31 02:47:06 +00:00
e3287b85b7
Enable generation of AssertSext and AssertZext in the PPC backend.
...
llvm-svn: 23168
2005-08-31 01:58:39 +00:00
f4d594370b
Fix 'ret long' to return the high and lo parts in the right registers. This
...
fixes crafty and probably others.
llvm-svn: 23167
2005-08-31 01:34:29 +00:00
539e7c892c
Sigh, not my day. Fix typo.
...
llvm-svn: 23166
2005-08-31 00:43:49 +00:00
d513d8a662
Fix a mistake in my previous patch pointed out by sabre; the AssertZext
...
case in MaskedValueIsZero was wrong.
llvm-svn: 23165
2005-08-31 00:43:08 +00:00
e07bc28cca
Remove some unnecessary casts, and add the AssertZext case to
...
MaskedValueIsZero.
llvm-svn: 23164
2005-08-31 00:27:53 +00:00
69e9a9a94c
now that physregs can exist in the same dag with multiple types, remove some
...
ugly hacks
llvm-svn: 23162
2005-08-30 22:59:48 +00:00
5764da422a
Allow physregs to occur in the dag with multiple types. Though I don't likethis, it is a requirement on PPC, which can have an f32 value in r3 at onepoint in a function and a f64 value in r3 at another point. :(
...
This fixes compilation of mesa
llvm-svn: 23161
2005-08-30 22:38:38 +00:00
8f8d539746
Fix type mismatches when passing f32 values to calls
...
llvm-svn: 23159
2005-08-30 21:28:19 +00:00
4d602bed10
When checking the fixed intervals, don't forget to check for register aliases.
...
This fixes PR621 and Regression/CodeGen/X86/2005-08-30-RegAllocAliasProblem.ll
llvm-svn: 23158
2005-08-30 21:03:36 +00:00
9f23ae226f
Fix some indentation (first hunks).
...
Remove code (last hunk) that miscompiled immediate and's, such as
and uint %tmp.30, 4294958079
into
andi. r8, r8, 56319
andis. r8, r8, 65535
instead of:
li r9, -9217
and r8, r8, r9
The first always generates zero.
This fixes espresso.
llvm-svn: 23155
2005-08-30 18:37:48 +00:00
6a41fd75cd
Fix a problem Nate found where we swapped the operands of SHL/SHR_PARTS. This
...
fixes fourinarow
llvm-svn: 23153
2005-08-30 17:42:59 +00:00
bdf3d3defb
codegen ADD_PARTS correctly: put the results in the right registers! This
...
fixes fhourstones
llvm-svn: 23152
2005-08-30 17:40:13 +00:00
61d21b1f3c
Fix FreeBench/fourinarow with the dag isel, by not adding a bogus result
...
to SHIFT_PARTS nodes
llvm-svn: 23151
2005-08-30 17:21:17 +00:00
45706e9fb8
add operands in the right order, fixing McCat/18-imp with the dag isel
...
llvm-svn: 23150
2005-08-30 17:13:58 +00:00
9a4ad487f0
Fix a miscompile of PtrDist/bc. Sign extending bools is not the right thing,
...
at least tends to expose problems elsewhere.
llvm-svn: 23149
2005-08-30 16:56:19 +00:00
a3da8c4819
Remove a bogus piece of my AssertSext/AssertZext patch. oops.
...
llvm-svn: 23148
2005-08-30 02:54:28 +00:00
43144a2fe0
Add support for AssertSext and AssertZext, folding other extensions with
...
them. This allows for elminination of redundant extends in the entry
blocks of functions on PowerPC.
Add support for i32 x i32 -> i64 multiplies, by recognizing when the inputs
to ISD::MUL in ExpandOp are actually just extended i32 values and not real
i64 values. this allows us to codegen
int mulhs(int a, int b) { return ((long long)a * b) >> 32; }
as:
_mulhs:
mulhw r3, r4, r3
blr
instead of:
_mulhs:
mulhwu r2, r4, r3
srawi r5, r3, 31
mullw r5, r4, r5
add r2, r2, r5
srawi r4, r4, 31
mullw r3, r4, r3
add r3, r2, r3
blr
with a similar improvement on x86.
llvm-svn: 23147
2005-08-30 02:44:00 +00:00
08a1e38730
Name this variable to be what it really is!
...
llvm-svn: 23145
2005-08-30 01:58:51 +00:00
04cb82278a
Handle CopyToReg nodes with flag operands correctly
...
llvm-svn: 23144
2005-08-30 01:57:23 +00:00
7a59b1cf90
Make sure the selector emits register register copies with flag operands
...
linking them to calls when appropriate, this prevents the scheduler from
pulling these copies away from the call.
This fixes Ptrdist/yacr2
llvm-svn: 23143
2005-08-30 01:57:02 +00:00
e413b60632
The first operand to AND does not always have more than two operands. This
...
fixes MediaBench/toast with the dag selector
llvm-svn: 23141
2005-08-30 00:59:16 +00:00
e75b5e63a7
Fix a bug in my patch for legalizing to fsel. It cannot handle seteq/setne,
...
which I failed to include when I moved the code over. This fixes
MallocBench/gs.
llvm-svn: 23140
2005-08-30 00:45:18 +00:00
61f7c3e843
emit FMR instructions to convert f64<->f32 instructions, so things like
...
STOREs, know the right type to store.
llvm-svn: 23139
2005-08-30 00:30:43 +00:00
62b9a5d1f8
Fix some really strange indentation that xcode likes to use.
...
no xcode, this is not right:
if (!foo) break;
X;
llvm-svn: 23138
2005-08-30 00:19:00 +00:00
12357281b8
fix a crash in cfrac
...
llvm-svn: 23137
2005-08-29 23:49:25 +00:00
1cbbe1015a
Implement DYNAMIC_STACKALLOC, wrap some long lines
...
llvm-svn: 23136
2005-08-29 23:30:11 +00:00
f7e5ec84c6
Add a hack to avoid some horrible code in some cases by always emitting
...
token chains first. For this C function:
int test() {
int i;
for (i = 0; i < 100000; ++i)
foo();
}
Instead of emitting this (condition before call)
.LBB_test_1: ; no_exit
addi r30, r30, 1
lis r2, 1
ori r2, r2, 34464
cmpw cr2, r30, r2
bl L_foo$stub
bne cr2, .LBB_test_1 ; no_exit
Emit this:
.LBB_test_1: ; no_exit
bl L_foo$stub
addi r30, r30, 1
lis r2, 1
ori r2, r2, 34464
cmpw cr0, r30, r2
bne cr0, .LBB_test_1 ; no_exit
Which makes it so we don't have to save/restore cr2 in the prolog/epilog of
the function.
This also makes the code much more similar to what the pattern isel produces.
llvm-svn: 23135
2005-08-29 23:21:29 +00:00
b2b418509b
Fix a dumb bug of mine where we were mishandling the PPC ABI (undef handling).
...
This fixes voronoi and bh in Olden, allowing all of olden to pass!
llvm-svn: 23133
2005-08-29 22:22:57 +00:00
c738d000d5
Add a new API for Nate
...
llvm-svn: 23131
2005-08-29 21:59:31 +00:00
835cbb364d
Some of us cared about the the promote path
...
llvm-svn: 23130
2005-08-29 20:46:51 +00:00
dcde1b2b6a
Fix an infinite loop on x86
...
llvm-svn: 23129
2005-08-29 17:30:00 +00:00
1a1ecf0679
Allow bugpoint+PPC codegen to use fsqrt
...
llvm-svn: 23128
2005-08-29 13:14:24 +00:00
c429ab2fb1
Fix a bug the last patch exposed in treeadd among others
...
llvm-svn: 23127
2005-08-29 01:07:02 +00:00
d4d683a47b
A hack to fix a problem folding immedaites. This fixes Olden/power.
...
llvm-svn: 23126
2005-08-29 01:01:01 +00:00
3ccad3fb8c
Fix order of operands for copytoreg node when emitting calls. This fixes
...
Olden/msFix order of operands for copytoreg node when emitting calls. This fixes
Olden/mstt.
llvm-svn: 23125
2005-08-29 00:26:57 +00:00
46d4c75cd1
Fix a bug in my previous patch that was using the wrong iterator. This fixes
...
Olden/bisort among others.
llvm-svn: 23124
2005-08-29 00:10:46 +00:00
66ddc8d3bf
add operands in the correct order
...
llvm-svn: 23123
2005-08-29 00:02:01 +00:00
87421c8658
Fix a bug in ReplaceAllUsesWith
...
llvm-svn: 23122
2005-08-28 23:59:36 +00:00
dfcde88d07
Fix a bug in FP_EXTEND, implement FP_TO_SINT
...
llvm-svn: 23121
2005-08-28 23:59:09 +00:00
38660c6666
fix an assertion failure in treeadd
...
llvm-svn: 23120
2005-08-28 23:39:22 +00:00
aa7fbca285
Adjust to member variable name change.
...
llvm-svn: 23119
2005-08-27 19:09:48 +00:00
85d93a3ec9
Change the names of member variables per Chris' instructions, and document
...
them more clearly.
llvm-svn: 23118
2005-08-27 19:09:02 +00:00
dfb3fb4a25
Implement PR614:
...
These changes modify the makefiles so that the output of flex and bison are
placed in the SRC directory, not the OBJ directory. It is intended that they
be checked in as any other LLVM source so that platforms without convenient
access to flex/bison can be compiled. From now on, if you change a .y or
.l file you *must* also commit the generated .cpp and .h files.
llvm-svn: 23115
2005-08-27 18:50:39 +00:00
075250bda1
Disable this code, which broke many tests last night
...
llvm-svn: 23114
2005-08-27 16:16:51 +00:00
5ee85e89b6
fix PHI node emission for basic blocks that have select_cc's in them on ppc32
...
llvm-svn: 23113
2005-08-27 00:58:02 +00:00
787e962795
The condition register being branched on may not be cr0, as such, print it.
...
This fixes: UnitTests/2005-07-17-INT-To-FP.c
llvm-svn: 23112
2005-08-26 23:42:05 +00:00
29bfaa7ef0
Propagate cr# from COND_BRANCH to the actual branch instruction as appropriate
...
llvm-svn: 23111
2005-08-26 23:41:27 +00:00
56ca46ee04
Nate noticed that Andrew never did this. This fixes PR600
...
llvm-svn: 23110
2005-08-26 22:50:40 +00:00
e7a2998064
Don't copy regs that are only used in the entry block into a vreg. This
...
changes the code generated for:
short %test(short %A) {
%B = xor short %A, -32768
ret short %B
}
to:
_test:
xori r2, r3, 32768
xoris r2, r2, 65535
extsh r3, r2
blr
instead of:
_test:
rlwinm r2, r3, 0, 16, 31
xori r2, r3, 32768
xoris r2, r2, 65535
extsh r3, r2
blr
llvm-svn: 23109
2005-08-26 22:49:59 +00:00
d4f43f7967
Make this code safe for when loadRegFromStackSlot inserts multiple instructions.
...
llvm-svn: 23108
2005-08-26 22:18:32 +00:00
422e23dd02
allow code using mtcrf to assemble
...
llvm-svn: 23107
2005-08-26 22:05:54 +00:00
72f23815bc
Remove operand type 'crbit', since it is no longer used
...
llvm-svn: 23106
2005-08-26 22:04:17 +00:00
c3d1bdd0a9
teach getClass what a condition reg is
...
llvm-svn: 23105
2005-08-26 21:51:29 +00:00
97345405a6
Minor cleanups:
...
* avoid calling getClass() multiple times (it is relatively expensive)
* Allow -disable-fp-elim to turn of frame pointer elimination.
llvm-svn: 23104
2005-08-26 21:49:18 +00:00
4a5ebe94ba
Checking types here is not safe, because multiple types can map to the same
...
register class.
llvm-svn: 23103
2005-08-26 21:39:15 +00:00
9b577f108a
implement SELECT_CC fully for the DAG->DAG isel!
...
llvm-svn: 23101
2005-08-26 21:23:58 +00:00
c6a0338c04
spell this right
...
llvm-svn: 23099
2005-08-26 20:55:40 +00:00
13d7c252e5
Call the InsertAtEndOfBasicBlock hook if the usesCustomDAGSchedInserter
...
flag is set on an instruction.
llvm-svn: 23098
2005-08-26 20:54:47 +00:00
0081dfa91e
Add a flag
...
llvm-svn: 23092
2005-08-26 20:29:01 +00:00
b2854fadda
Make fsel emission work with both the pattern and dag-dag selectors, by
...
giving it a non-instruction opcode. The dag->dag selector used to not
select the operands of the fsel, because it thought that whole tree was
already selected.
llvm-svn: 23091
2005-08-26 20:25:03 +00:00
bec817ce6f
implement the fold for:
...
bool %test(int %X, int %Y) {
%C = setne int %X, 0
ret bool %C
}
to:
_test:
addic r2, r3, -1
subfe r3, r2, r3
blr
llvm-svn: 23089
2005-08-26 18:46:49 +00:00
a9e6a82d66
Changes to adjust to new ReplaceAllUsesWith syntax. Change FP_EXTEND to
...
just return its input, instead of emitting an explicit copy.
llvm-svn: 23088
2005-08-26 18:37:23 +00:00
373f048a79
Revampt ReplaceAllUsesWith to be more efficient and easier to use.
...
llvm-svn: 23087
2005-08-26 18:36:28 +00:00
76eea9a480
Remove some code made dead by the fsel patch
...
llvm-svn: 23085
2005-08-26 17:45:06 +00:00
c75e047245
now that fsel is formed during legalization, this code is dead
...
llvm-svn: 23084
2005-08-26 17:40:39 +00:00
7f1fa8eaef
implement the other half of the select_cc -> fsel lowering, which handles
...
when the RHS of the comparison is 0.0. Turn this on by default.
llvm-svn: 23083
2005-08-26 17:36:52 +00:00
d0dc6f4299
Fix a bug in my previous checkin
...
llvm-svn: 23082
2005-08-26 17:18:44 +00:00
c30405e0ee
Change ConstantPoolSDNode to actually hold the Constant itself instead of
...
putting it into the constant pool. This allows the isel machinery to
create constants that it will end up deciding are not needed, without them
ending up in the resultant function constant pool.
llvm-svn: 23081
2005-08-26 17:15:30 +00:00
7bbdae53d6
Fix some warnings in an optimized build
...
llvm-svn: 23080
2005-08-26 16:38:51 +00:00
2091a36631
Fix a huge annoyance: SelectNodeTo took types before the opcode unlike
...
every other SD API. Fix it to take the opcode before the types.
llvm-svn: 23079
2005-08-26 16:36:26 +00:00
7b809f593b
Fix JIT encoding of conditional branches
...
llvm-svn: 23076
2005-08-26 04:11:42 +00:00
f3d06c6417
add initial support for converting select_cc -> fsel in the legalizer
...
instead of in the backend. This currently handles fsel cases with registers,
but doesn't have the 0.0 and -0.0 optimization enabled yet.
Once this is finished, special hack for fp immediates can go away.
llvm-svn: 23075
2005-08-26 00:52:45 +00:00
c6d481db7a
the 5th operand is the 4th number
...
llvm-svn: 23074
2005-08-26 00:43:46 +00:00
89093ca62a
SUBFIC produces two results, not one.
...
llvm-svn: 23073
2005-08-26 00:34:06 +00:00
bed4f2b982
Implement SHL_PARTS and SRL_PARTS
...
llvm-svn: 23072
2005-08-26 00:28:00 +00:00
5f573416cd
Add support for targets that want to custom expand select_cc in some cases.
...
llvm-svn: 23071
2005-08-26 00:23:59 +00:00
dff50cadaa
Allow LowerOperation to return a null SDOperand in case it wants to lower
...
some things given to it, but not all.
llvm-svn: 23070
2005-08-26 00:14:16 +00:00
1cb550c603
Fix a nasty bug from a previous patch of mine
...
llvm-svn: 23069
2005-08-26 00:13:12 +00:00
b81431b012
Emit the lo/hi parts in the right order :)
...
llvm-svn: 23068
2005-08-25 23:36:49 +00:00
02884fe41c
implement support for 64-bit add/sub, fix a broken assertion for 64-bit
...
return. Allow the udiv breaker-upper to work with any non-zero constant
operand.
llvm-svn: 23066
2005-08-25 23:21:06 +00:00
abbd8ea048
simplify the add/sub_parts code
...
llvm-svn: 23065
2005-08-25 23:19:58 +00:00
6e184f2b3d
Finish implementing SDIV/UDIV by copying over the majik constant code from
...
ISelPattern
llvm-svn: 23062
2005-08-25 22:04:30 +00:00
717f97a5c8
Simplify some code. It's not clear why the UDIV expanded sequence
...
doesn't work for large uint constants, but we'll keep the current behavior
llvm-svn: 23061
2005-08-25 22:03:50 +00:00
b746dd1cf6
Implement setcc correctly for G5 and non-G5 systems
...
llvm-svn: 23060
2005-08-25 21:39:42 +00:00
3dcd75bc54
implement setcc on the G5. We're still missing the non-g5 specific bits, but
...
they will come later.
llvm-svn: 23059
2005-08-25 20:08:18 +00:00
33840c3268
New fold for SELECT_CC
...
llvm-svn: 23058
2005-08-25 20:04:38 +00:00
65ffd8fbf4
Remove option to make SetCC illegal on PowerPC after long discussion with
...
Chris. This will be accomplished through correctly modeling CR's and
subregs.
llvm-svn: 23056
2005-08-25 20:01:10 +00:00
f9c19157df
Don't auto-cse nodes that return flags
...
llvm-svn: 23055
2005-08-25 19:12:10 +00:00
12756be53b
add printer support for flag operands
...
llvm-svn: 23054
2005-08-25 17:59:23 +00:00
9d28a56d55
simplify the code a bit using isOperationLegal
...
llvm-svn: 23053
2005-08-25 17:54:58 +00:00
dc66457022
Add support for sdiv by 2^k and -2^k. Producing code like:
...
_test:
srawi r2, r3, 2
addze r3, r2
blr
llvm-svn: 23052
2005-08-25 17:50:06 +00:00
4bd2aab6c1
fit in 80 cols
...
llvm-svn: 23051
2005-08-25 17:49:31 +00:00
8a93f64efa
Add support for flag operands
...
llvm-svn: 23050
2005-08-25 17:48:54 +00:00
d24ad52efa
add an enum value
...
llvm-svn: 23048
2005-08-25 17:07:09 +00:00
25db699671
Implement support for taking the address of constant pool indices, which
...
is used by the int -> FP code among other things. This gets
2005-05-12-Int64ToFP past that failure, to dying on lack of support for add_parts
llvm-svn: 23042
2005-08-25 05:04:11 +00:00
407c6415b4
ADd support for TargetConstantPool nodes
...
llvm-svn: 23041
2005-08-25 05:03:06 +00:00
666512c832
Add support for FP constants, fixing UnitTests/2004-02-02-NegativeZero
...
llvm-svn: 23038
2005-08-25 04:47:18 +00:00
e4c338d0d8
Fully implement frame index, so that we can pass the address of alloca's
...
around to functions and stuff
llvm-svn: 23036
2005-08-25 00:45:43 +00:00
bbe0e7df2c
add a new TargetFrameIndex node
...
llvm-svn: 23035
2005-08-25 00:43:01 +00:00
66a6a13225
implement unconditional branches, fixing UnitTests/2003-05-02-DependentPHI.c
...
llvm-svn: 23034
2005-08-25 00:29:58 +00:00
4ae278a760
LFS/STFS load and store FP values, not integer ones. This change allows us
...
to codegen this: float foo() { return 1.245; }
into this:
_foo:
lis r2, ha16(.CPI_foo_0)
lfs f1, lo16(.CPI_foo_0)(r2)
blr
instead of this:
_foo:
lis r2, ha16(.CPI_foo_0)
lfs r2, lo16(.CPI_foo_0)(r2) <-- ouch
or f1, r2, r2 <-- ouch
blr
with the dag isel.
llvm-svn: 23033
2005-08-25 00:26:22 +00:00
794eb6684d
Fix a broken assertion
...
llvm-svn: 23032
2005-08-25 00:19:12 +00:00
c146940f0d
Fix a warning
...
llvm-svn: 23031
2005-08-25 00:05:15 +00:00
daae1e10f7
fix a warning in optimized build
...
llvm-svn: 23030
2005-08-25 00:03:21 +00:00
751c6c3944
Fix some warnings
...
llvm-svn: 23029
2005-08-25 00:00:26 +00:00
a3fbdae515
Split IMPLICIT_DEF into IMPLICIT_DEF_GPR and IMPLICIT_DEF_FP, so that the
...
instructions take a consistent reg class. Implement ISD::UNDEF in the dag->dag
selector to generate this, fixing UnitTests/2003-07-06-IntOverflow.
llvm-svn: 23028
2005-08-24 23:08:16 +00:00
45e1ce4e28
add a method
...
llvm-svn: 23027
2005-08-24 23:00:29 +00:00
d83cd354bd
implement support for calls
...
llvm-svn: 23026
2005-08-24 22:45:17 +00:00
d7ee4d8671
Add ReplaceAllUsesWith that can take a vector of replacement values.
...
Add some foldings to hopefully help the illegal setcc issue, and move some code around.
llvm-svn: 23025
2005-08-24 22:44:39 +00:00
1fc2a7f006
Remove some dead cases.
...
Emit the indcall sequence as:
mtctr inreg
mr R12, inreg
btctr
If inreg and R12 aren't coallesced, this reduces the odds of having the mtctr
and btctr in the same dispatch group. :)
llvm-svn: 23023
2005-08-24 22:21:47 +00:00
ad9565dfbe
Add support for external symbols, and support for variable arity instructions
...
llvm-svn: 23022
2005-08-24 22:02:41 +00:00
bb8cc0acb2
Fix pasto that prevented VT ndoes from showing up in -view-isel-dags correctly
...
llvm-svn: 23021
2005-08-24 18:30:00 +00:00
1e98a330f2
add an idea
...
llvm-svn: 23020
2005-08-24 18:15:24 +00:00
8ca5b2a6d2
Fix Regression/Transforms/Reassociate/2005-08-24-Crash.ll
...
llvm-svn: 23019
2005-08-24 17:55:32 +00:00
4201cd1bbc
Transform floor((double)FLT) -> (double)floorf(FLT), implementing
...
Regression/Transforms/SimplifyLibCalls/floor.ll. This triggers 19 times in
177.mesa.
llvm-svn: 23017
2005-08-24 17:22:17 +00:00
898e50ecb3
floor/ceil don't read/write memory. This allows gcse to eliminate 6 calls
...
in mesa.
llvm-svn: 23015
2005-08-24 16:58:56 +00:00
86b1658d58
teach selection dag mask tracking about the fact that select_cc operates like
...
select. Also teach it that the bit count instructions can only set the low bits
of the result, depending on the size of the input.
This allows us to compile this:
int %eq0(int %a) {
%tmp.1 = seteq int %a, 0 ; <bool> [#uses=1]
%tmp.2 = cast bool %tmp.1 to int ; <int> [#uses=1]
ret int %tmp.2
}
To this:
_eq0:
cntlzw r2, r3
srwi r3, r2, 5
blr
instead of this:
_eq0:
cntlzw r2, r3
rlwinm r3, r2, 27, 31, 31
blr
when setcc is marked illegal on ppc (which restores parity to non-illegal
setcc). Thanks to Nate for pointing this out.
llvm-svn: 23013
2005-08-24 16:46:55 +00:00
f12eb4d676
Start using isOperationLegal and isTypeLegal to simplify the code
...
llvm-svn: 23012
2005-08-24 16:35:28 +00:00
ade525491f
Adjust to new interface
...
llvm-svn: 23010
2005-08-24 16:34:12 +00:00
f85fabeb71
For PR616:
...
These patches make threading optional in LLVM. The configuration scripts are now
modified to accept a --disable-threads switch. If this is used, the Mutex class
will be implemented with all functions as no-op. Furthermore, linking against
libpthread will not be done. Finally, the ParallelJIT example needs libpthread
so its makefile was changed to always add -lpthread to the link line.
llvm-svn: 23003
2005-08-24 10:07:20 +00:00
7c1ba938be
Whoops, fix a thinko. All cases except SETNE are now handled by the
...
target independent code in SelectionDAG.cpp
llvm-svn: 23002
2005-08-24 05:06:48 +00:00
a1e0a2f72b
Remove unused statistic
...
Prefer 'neg X' to 'subfic 0, X' since neg does not set XER[CA]
llvm-svn: 23001
2005-08-24 05:03:20 +00:00
6948b79b26
Add the "ppc specific" setcc-equivalent select_cc cases
...
Prefer 'neg X' to 'subfic 0, X' since it does not set XER[CA]
llvm-svn: 23000
2005-08-24 04:59:21 +00:00
45bbbb3f11
Teach SelectionDAG how to simplify a few more setcc-equivalent select_cc
...
nodes so that backends don't have to.
llvm-svn: 22999
2005-08-24 04:57:57 +00:00
b6d034a841
Add callseq_begin/end support
...
Call stil not supported yet
llvm-svn: 22998
2005-08-24 00:47:15 +00:00
99282c7b92
Make -view-isel-dags show the dag before instruction selecting, in case
...
the target isel crashes due to unimplemented features like calls :)
llvm-svn: 22997
2005-08-24 00:34:29 +00:00
72eab5dd5c
Fix optimization of select_cc seteq X, 0, 1, 0 -> srl (ctlz X), log2 X size
...
llvm-svn: 22995
2005-08-24 00:21:28 +00:00
eeacce5a60
Implement LiveVariables.h change
...
llvm-svn: 22994
2005-08-24 00:09:33 +00:00
469652752c
adjust to new live variables interface
...
llvm-svn: 22992
2005-08-23 23:42:17 +00:00
cdc0cbbcd0
Adjust to new livevars interface
...
llvm-svn: 22991
2005-08-23 23:41:14 +00:00
774158239b
Simplify this code by using higher-level LiveVariables methods
...
llvm-svn: 22989
2005-08-23 22:51:41 +00:00
7c1c6e06f3
Simplify this code by using LiveVariables::KillsRegister
...
llvm-svn: 22988
2005-08-23 22:49:55 +00:00
22e91cc3b5
Keep track of which registers are related to which other registers.
...
Use this information to avoid doing expensive interval intersections for
registers that could not possible be interesting. This speeds up linscan
on ia64 compiling kc++ in release mode from taking 7.82s to 4.8s(!), total
itanium llc time on this program is 27.3s now. This marginally speeds up
PPC and X86, but they appear to be limited by other parts of linscan, not
this code.
On this program, on itanium, live intervals now takes 41% of llc time.
llvm-svn: 22986
2005-08-23 22:27:31 +00:00
9c0a243ce5
Fix PR618 and Regression/CodeGen/CBackend/2005-08-23-Fmod.ll by not emitting
...
x%y for 'rem' on fp values.
llvm-svn: 22984
2005-08-23 20:22:50 +00:00
5e3953d761
add a note
...
llvm-svn: 22982
2005-08-23 06:27:59 +00:00
f3ce09b36e
Ack, typo
...
llvm-svn: 22981
2005-08-23 05:45:10 +00:00
7216ad415b
Add an option to make SetCC illegal as a beta option
...
llvm-svn: 22979
2005-08-23 05:42:36 +00:00
bf8c3939d7
Teach the SelectionDAG how to transform select_cc eq, X, 0, 1, 0 into
...
either seteq X, 0 or srl (ctlz X), size(X-1), depending on what's legal
for the target.
llvm-svn: 22978
2005-08-23 05:41:12 +00:00
987121a61a
Teach Legalize how to turn setcc into select_cc
...
llvm-svn: 22977
2005-08-23 04:29:48 +00:00
06436b2b7d
Remove some instructions we no longer generate
...
llvm-svn: 22976
2005-08-23 01:16:46 +00:00
46323cf0e2
Remove some regs that are not used.
...
llvm-svn: 22975
2005-08-22 22:32:13 +00:00
956820d989
Nate noticed that 30% of the malloc/frees in llc come from calls to LowercaseString
...
in the asmprinter. This changes the .td files to use lower case register names,
avoiding the need to do this call. This speeds up the asmprinter from 1.52s
to 1.06s on kc++ in a release build.
llvm-svn: 22974
2005-08-22 22:00:02 +00:00
d2f2aff484
Fix a crash I introduced into the IA64 backend with my copyfromreg change.
...
It used to crash on any function that took float arguments.
llvm-svn: 22973
2005-08-22 21:33:11 +00:00
834a2316a3
Try to avoid scanning the fixed list. On architectures with a non-stupid
...
number of regs (e.g. most riscs), many functions won't need to use callee
clobbered registers. Do a speculative check to see if we can get a free
register without processing the fixed list (which has all of these). This
saves a lot of time on machines with lots of callee clobbered regs (e.g.
ppc and itanium, also x86).
This reduces ppc llc compile time from 184s -> 172s on kc++. This is probably
worth FAR FAR more on itanium though.
llvm-svn: 22972
2005-08-22 20:59:30 +00:00
95a157ae1a
Move some code in the register assignment case that only needs to happen if
...
we spill out of the fast path. The scan of active_ and the calls to
updateSpillWeights don't need to happen unless a spill occurs. This reduces
debug llc time of kc++ with ppc from 187.3s to 183.2s.
llvm-svn: 22971
2005-08-22 20:20:42 +00:00
9d46518e5c
Add a pass name for -time-passes output
...
llvm-svn: 22970
2005-08-22 18:28:09 +00:00
7f9e078d11
Fix a problem where constant expr shifts would not have their shift amount
...
promoted to the right type. This fixes: IA64/2005-08-22-LegalizerCrash.ll
llvm-svn: 22969
2005-08-22 17:28:31 +00:00
83b821b584
Speed up this loop a bit, based on some observations that Nate made, and
...
add some comments. This loop really needs to be reevaluated!
llvm-svn: 22966
2005-08-22 16:55:22 +00:00
ca0c0d7550
Implement stores.
...
llvm-svn: 22963
2005-08-22 01:27:59 +00:00
92626b9bc5
Add a fast-path for register values. Add support for constant pool entries,
...
allowing us to compile this:
float %test2(float* %P) {
%Q = load float* %P
%R = add float %Q, 10.1
ret float %R
}
to this:
_test2:
lfs r2, 0(r3)
lis r3, ha16(.CPI_test2_0)
lfs r3, lo16(.CPI_test2_0)(r3)
fadds f1, r2, r3
blr
llvm-svn: 22962
2005-08-22 01:04:32 +00:00
1d634b2f44
Fix compilation of:
...
float %test2(float* %P) {
%Q = load float* %P
%R = add float %Q, %Q
ret float %R
}
By returning the right result.
llvm-svn: 22961
2005-08-22 00:59:14 +00:00
b676e5a666
Make sure expressions only have one use before emitting them into a place that is conditionally executed
...
llvm-svn: 22960
2005-08-22 00:47:28 +00:00
c5292ec9de
Implement most of load support. There is still a bug though.
...
llvm-svn: 22959
2005-08-21 22:31:09 +00:00
466fecee19
add anew method
...
llvm-svn: 22957
2005-08-21 22:30:30 +00:00
4866356907
Add support for frame index nodes
...
llvm-svn: 22956
2005-08-21 19:56:04 +00:00
0548f50501
add a method
...
llvm-svn: 22955
2005-08-21 19:48:59 +00:00
968aeb18b0
Don't print out the MBB label for the entry mbb
...
llvm-svn: 22953
2005-08-21 19:09:33 +00:00
519acbfb76
Simplify the logic for BRTWOWAY_CC handling. The isel code already
...
simplifies BRTWOWAY into BR if one of the results is a fall-through.
Unless I'm missing something, there is no reason to duplicate this
in the target-specific code.
llvm-svn: 22952
2005-08-21 19:03:28 +00:00
2a1823d178
Implement selection for branches.
...
llvm-svn: 22951
2005-08-21 18:50:37 +00:00
707b39fb8c
add a method
...
llvm-svn: 22949
2005-08-21 18:49:33 +00:00
154b2bc59b
Add support for basic blocks, fix a bug in result # computation
...
llvm-svn: 22948
2005-08-21 18:49:29 +00:00
539c3fa863
When legalizing brcond ->brcc or select -> selectcc, make sure to truncate
...
the old condition to a one bit value. The incoming value must have been
promoted, and the top bits are undefined. This causes us to generate:
_test:
rlwinm r2, r3, 0, 31, 31
li r3, 17
cmpwi cr0, r2, 0
bne .LBB_test_2 ;
.LBB_test_1: ;
li r3, 1
.LBB_test_2: ;
blr
instead of:
_test:
rlwinm r2, r3, 0, 31, 31
li r2, 17
cmpwi cr0, r3, 0
bne .LBB_test_2 ;
.LBB_test_1: ;
li r2, 1
.LBB_test_2: ;
or r3, r2, r2
blr
for:
int %test(bool %c) {
%retval = select bool %c, int 17, int 1
ret int %retval
}
llvm-svn: 22947
2005-08-21 18:03:09 +00:00
0500e362bf
If the false value for a select_cc is really simple (has no inputs), evaluate
...
it in the block. This codegens:
int %test(bool %c) {
%retval = select bool %c, int 17, int 1
ret int %retval
}
as:
_test:
rlwinm r2, r3, 0, 31, 31
li r2, 17
cmpwi cr0, r3, 0
bne .LBB_test_2 ;
.LBB_test_1: ;
li r2, 1
.LBB_test_2: ;
or r3, r2, r2
blr
instead of:
_test:
rlwinm r2, r3, 0, 31, 31
li r2, 17
li r4, 1
cmpwi cr0, r3, 0
bne .LBB_test_2 ;
.LBB_test_1: ;
or r2, r4, r4
.LBB_test_2: ;
or r3, r2, r2
blr
... which is one fewer instruction. The savings are more significant for
global address and constantfp nodes.
llvm-svn: 22946
2005-08-21 17:41:11 +00:00
3588ea9bf5
reenable collapse of loadimm+AND -> dep.z (thanks guys)
...
llvm-svn: 22944
2005-08-21 15:43:53 +00:00
4b08ba26d8
fix bogus warning
...
llvm-svn: 22943
2005-08-20 18:07:27 +00:00
9b0a275f04
Repair an out by one error for IA64.
...
llvm-svn: 22942
2005-08-20 11:05:23 +00:00
4564039498
add support for global address, including PIC support.
...
This REALLY should be lowered by the legalizer!
llvm-svn: 22941
2005-08-19 22:38:53 +00:00
319e65696d
Add support for global address nodes
...
llvm-svn: 22940
2005-08-19 22:38:24 +00:00
1be7eddecf
Add support for TargetGlobalAddress nodes
...
llvm-svn: 22938
2005-08-19 22:31:04 +00:00
6d7f814b01
Implement CopyFromReg, TokenFactor, and fix a bug in CopyToReg. This allows
...
us to compile stuff like this:
double %test(double %A, double %B, double %C, double %E) {
%F = mul double %A, %A
%G = add double %F, %B
%H = sub double -0.0, %G
%I = mul double %H, %C
%J = add double %I, %E
ret double %J
}
to:
_test:
fnmadd f0, f1, f1, f2
fmadd f1, f0, f3, f4
blr
woot!
llvm-svn: 22937
2005-08-19 21:43:53 +00:00
0875d1ab89
Fix a bug in previous commit
...
llvm-svn: 22936
2005-08-19 21:34:13 +00:00
65d66797a5
Fix a typeo, no wonder all tokenfactor edges were the same!
...
llvm-svn: 22935
2005-08-19 21:33:02 +00:00
4990335eb8
Print physreg register nodes with target names (e.g. F1) instead of numbers
...
llvm-svn: 22934
2005-08-19 21:21:16 +00:00
78b200eb74
Before implementing copyfromreg, we'll implement copytoreg correctly.
...
This gets us this for the previous testcase:
_test:
lis r2, 0
ori r3, r2, 65535
blr
Note that we actually write to r3 (the return reg) correctly now :)
llvm-svn: 22933
2005-08-19 20:50:53 +00:00
cc3035e989
Now that we have operand info for machine instructions, use it to create
...
temporary registers for things that define a register. This allows dag->dag
isel to compile this:
int %test() { ret int 65535 }
into:
_test:
lis r2, 0
ori r2, r2, 65535
blr
Next up, getting CopyFromReg to work, allowing arguments and cross-bb values.
llvm-svn: 22932
2005-08-19 20:45:43 +00:00
bd26a82051
Split RegisterClass 'Methods' into MethodProtos and MethodBodies
...
llvm-svn: 22929
2005-08-19 19:13:20 +00:00
248933eb39
put reg classes into namespace
...
llvm-svn: 22927
2005-08-19 18:53:43 +00:00
1dee9b1685
Put reg classes into namespaces
...
llvm-svn: 22926
2005-08-19 18:52:55 +00:00
757a770a57
Put register classes into namespaces
...
llvm-svn: 22925
2005-08-19 18:51:57 +00:00
8975de187f
Put register classes in namespaces
...
llvm-svn: 22924
2005-08-19 18:50:46 +00:00
dc89d6be04
Fix code that assumes the register info will be dumped into a target
...
namespace instead of the reg class namespace. Update getRegClassForType()
to use modified names due to tblgen change.
llvm-svn: 22923
2005-08-19 18:50:11 +00:00
cca0503c24
put reg classes in namespaces
...
llvm-svn: 22922
2005-08-19 18:49:22 +00:00
3fb85f2702
Require that targets specify a namespace for their register classes.
...
llvm-svn: 22921
2005-08-19 18:48:48 +00:00
3262673610
The skeleton target has never had an isel
...
llvm-svn: 22917
2005-08-19 18:35:41 +00:00
f391f286d7
This code has always been dead on itanium
...
llvm-svn: 22916
2005-08-19 18:34:37 +00:00
0faf0b7313
This code has always been dead for alpha
...
llvm-svn: 22915
2005-08-19 18:33:26 +00:00
8ad3700a3e
The simple isel being gone makes this dead!
...
llvm-svn: 22914
2005-08-19 18:32:03 +00:00
ef6d8d8e94
Now that the simple isels are dead, so is this.
...
llvm-svn: 22913
2005-08-19 18:30:39 +00:00
63143a0609
Sparcv9 gets no operand info
...
llvm-svn: 22909
2005-08-19 16:56:56 +00:00
486e36cfde
Fix VC++ constant truncation warning.
...
llvm-svn: 22907
2005-08-19 16:19:21 +00:00
fcbb38077b
a bugfix (up top) and a quick repair job: disable generation of dep.z
...
(which died about a week ago) so we're back to load-(2^n-1)-then-AND
sequences. slow, but things should now be Almost Completely Working,
modulo those pesky alignment/ABI issues.
llvm-svn: 22904
2005-08-19 13:25:50 +00:00
d1f22b1282
Fix VC++ precedence warning.
...
llvm-svn: 22902
2005-08-19 04:39:48 +00:00
Nate Begeman