e4ed42a426
Refactor some code into a function
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llvm-svn: 23603
2005-10-03 01:04:44 +00:00
360928dbed
This break is bogus and I have no idea why it was there. Basically it prevents
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memoizing code when IV's are used by phinodes outside of loops. In a simple
example, we were getting this code before (note that r6 and r7 are isomorphic
IV's):
li r6, 0
or r7, r6, r6
LBB_test_3: ; no_exit
lwz r2, 0(r3)
cmpw cr0, r2, r5
or r2, r7, r7
beq cr0, LBB_test_5 ; loopexit
LBB_test_4: ; endif
addi r2, r7, 1
addi r7, r7, 1
addi r3, r3, 4
addi r6, r6, 1
cmpw cr0, r6, r4
blt cr0, LBB_test_3 ; no_exit
Now we get:
li r6, 0
LBB_test_3: ; no_exit
or r2, r6, r6
lwz r6, 0(r3)
cmpw cr0, r6, r5
beq cr0, LBB_test_6 ; loopexit
LBB_test_4: ; endif
addi r3, r3, 4
addi r6, r2, 1
cmpw cr0, r6, r4
blt cr0, LBB_test_3 ; no_exit
this was noticed in em3d.
llvm-svn: 23602
2005-10-03 00:37:33 +00:00
8fcce170cf
when checking if we should move a split edge block outside of a loop,
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check the presplit pred, not the post-split pred. This was causing us
to make the wrong decision in some cases, leaving the critical edge block
in the loop.
llvm-svn: 23601
2005-10-03 00:31:52 +00:00
9cfccfb517
Fix a problem where the legalizer would run out of stack space on extremely
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large basic blocks because it was purely recursive. This switches it to an
iterative/recursive hybrid.
llvm-svn: 23596
2005-10-02 17:49:46 +00:00
7f718e61e8
silence a bogus warning
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llvm-svn: 23595
2005-10-02 16:30:51 +00:00
9982da2703
silence some warnings
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llvm-svn: 23594
2005-10-02 16:29:36 +00:00
c0e655b65d
silence a warning
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llvm-svn: 23593
2005-10-02 16:27:59 +00:00
68303a78ff
add patterns for float binops and fma ops
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llvm-svn: 23592
2005-10-02 07:46:28 +00:00
98da1d9910
Sort the cpu and features table, so that the alpha backend doesn't fail EVERY
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compile with an assertion that the tables are not sorted!
llvm-svn: 23591
2005-10-02 07:13:52 +00:00
704d97f8b2
Add assertions to the trivial scheduler to check that the value types match
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up between defs and uses.
llvm-svn: 23590
2005-10-02 07:10:55 +00:00
3734d204b8
another solution to the fsel issue. Instead of having 4 variants, just force
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the comparison to be 64-bits. This is fine because extensions from float
to double are free.
llvm-svn: 23589
2005-10-02 07:07:49 +00:00
9e98672962
fsel can take a different FP type for the comparison and for the result. As such
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split the FSEL family into 4 things instead of just two.
llvm-svn: 23588
2005-10-02 06:58:23 +00:00
a17e6c486c
fix an f32/f64 type mismatch
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llvm-svn: 23587
2005-10-02 06:37:13 +00:00
a038d901fb
Codegen CopyFromReg using the regclass that matches the valuetype of the
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destination vreg.
llvm-svn: 23586
2005-10-02 06:34:16 +00:00
4155ae0f74
Adjust to change in ctor
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llvm-svn: 23585
2005-10-02 06:23:51 +00:00
5ab9d42bb4
Minor tweak to the branch selector. When emitting a two-way branch, and if
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we're in a single-mbb loop, make sure to emit the backwards branch as the
conditional branch instead of the uncond branch. For example, emit this:
LBBl29_z__44:
stw r9, 0(r15)
stw r9, 4(r15)
stw r9, 8(r15)
stw r9, 12(r15)
addi r15, r15, 16
addi r8, r8, 1
cmpw cr0, r8, r28
ble cr0, LBBl29_z__44
b LBBl29_z__48 *** NOT PART OF LOOP
Instead of:
LBBl29_z__44:
stw r9, 0(r15)
stw r9, 4(r15)
stw r9, 8(r15)
stw r9, 12(r15)
addi r15, r15, 16
addi r8, r8, 1
cmpw cr0, r8, r28
bgt cr0, LBBl29_z__48 *** PART OF LOOP!
b LBBl29_z__44
The former sequence has one fewer dispatch group for the loop body.
llvm-svn: 23582
2005-10-01 23:06:26 +00:00
6f4dc51d6f
like the comment says, enable this
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llvm-svn: 23581
2005-10-01 23:02:40 +00:00
5a7bfe0b72
Add some very paranoid checking for operand/result reg class matchup
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For instructions that define multiple results, use the right regclass
to define the result, not always the rc of result #0
llvm-svn: 23580
2005-10-01 07:45:09 +00:00
f8a5e5ae6e
Fix VC++ warnings.
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llvm-svn: 23579
2005-10-01 03:57:14 +00:00
8713ebf37c
fix typo
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llvm-svn: 23578
2005-10-01 02:51:36 +00:00
d3eee1a09b
Modify the ppc backend to use two register classes for FP: F8RC and F4RC.
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These are used to represent float and double values, and the two regclasses
contain the same physical registers.
llvm-svn: 23577
2005-10-01 01:35:02 +00:00
fda6944c5b
add a method
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llvm-svn: 23575
2005-10-01 00:17:07 +00:00
d3850457a1
typo
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llvm-svn: 23574
2005-10-01 00:08:23 +00:00
9d96932879
1. Simplify the gathering of node groups.
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2. Printing node groups when displaying nodes.
llvm-svn: 23573
2005-10-01 00:03:07 +00:00
f61232354f
Should be using flag and not chain.
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llvm-svn: 23572
2005-09-30 23:43:37 +00:00
fbfad0b565
Remove some now-dead code.
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llvm-svn: 23571
2005-09-30 21:28:27 +00:00
49e48f6234
subtarget support for CIX and FIX extentions (the only 2 I care about right now)
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llvm-svn: 23569
2005-09-30 20:24:38 +00:00
3fe3841c2a
1. Made things node-centric (from operand).
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2. Added node groups to handle flagged nodes.
3. Started weaning simple scheduling off existing emitter.
llvm-svn: 23566
2005-09-30 19:15:27 +00:00
c9f4219cfc
Rename MRegisterDesc -> TargetRegisterDesc for consistency
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llvm-svn: 23564
2005-09-30 17:49:27 +00:00
81f32a2acb
trim down the target info structs now that we have a preferred spill register class for each callee save register
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Why is V9 maintaining these tables manually? ugh!
llvm-svn: 23561
2005-09-30 17:38:36 +00:00
2e794c9198
now that we have a reg class to spill with, get this info from the regclass
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llvm-svn: 23559
2005-09-30 17:19:22 +00:00
88025e17c5
constant fold these calls
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llvm-svn: 23558
2005-09-30 17:16:59 +00:00
bb1c9ecb17
simplify this code using the new regclass info passed in
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llvm-svn: 23557
2005-09-30 17:12:38 +00:00
51878189c5
Now that we have getCalleeSaveRegClasses() info, use it to pass the register
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class into the spill/reload methods. Targets can now rely on that argument.
llvm-svn: 23556
2005-09-30 16:59:07 +00:00
8688b92b86
stub out a virtual method
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llvm-svn: 23554
2005-09-30 06:55:18 +00:00
4984e99b83
CR registers are not used by this "target"
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llvm-svn: 23552
2005-09-30 06:43:58 +00:00
6169a78f46
these registers don't belong to any register classes, so don't mark them
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as callee save. They can never be generated by the compiler.
llvm-svn: 23551
2005-09-30 06:42:24 +00:00
33ce5f8a73
Now that self referential classes are supported, get rid of a work-around.
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llvm-svn: 23544
2005-09-30 04:13:23 +00:00
f6d4173f75
pass extra args
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llvm-svn: 23539
2005-09-30 01:31:52 +00:00
64ca7cda3f
these methods get extra args
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llvm-svn: 23538
2005-09-30 01:30:55 +00:00
a654525c1c
Pass extra regclasses into spilling code
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llvm-svn: 23537
2005-09-30 01:29:42 +00:00
5a6199f387
Change this code ot pass register classes into the stack slot spiller/reloader
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code. PrologEpilogInserter hasn't been updated yet though, so targets cannot
use this info.
llvm-svn: 23536
2005-09-30 01:29:00 +00:00
08f157c5b2
Use the 32-bit version for now
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llvm-svn: 23534
2005-09-30 00:05:05 +00:00
027a2671ef
Add a bunch of patterns for F64 FP ops, add some more integer ops
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llvm-svn: 23533
2005-09-29 23:34:24 +00:00
1de5706e68
Remove code for patterns that are autogenerated
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llvm-svn: 23532
2005-09-29 23:33:31 +00:00
a7a83b9255
begining alpha subtarget support
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llvm-svn: 23531
2005-09-29 22:54:56 +00:00
0a1cd715d4
tblgen autogens this pattern now
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llvm-svn: 23530
2005-09-29 22:37:24 +00:00
bae1f9d790
copy and paste error
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llvm-svn: 23528
2005-09-29 21:11:57 +00:00
a748e3ae5b
now that tblgen is smarter, this pattern is not needed. Also, tblgen
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now inverts commuted versions of ANDC/ORC with the current .td file.
llvm-svn: 23527
2005-09-29 19:29:15 +00:00
a554c9470b
Insert stores after phi nodes in the normal dest. This fixes
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LowerInvoke/2005-08-03-InvokeWithPHI.ll
llvm-svn: 23525
2005-09-29 17:44:20 +00:00
Chris Lattner