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12709 Commits

Author SHA1 Message Date
Chris Lattner af1bccec68 Fix a bug where RecursivelyDeleteTriviallyDeadInstructions could 
delete the instruction pointed to by CGP's current instruction
iterator, leading to a crash on the testcase.  This fixes PR9578.

llvm-svn: 129200
 2011-04-09 07:05:44 +00:00
Eli Friedman 17822fcde9 PR9604; try to deal with RAUW updates correctly in the AST. I'm not convinced 
it's completely safe to cache the AST across LICM runs even with this fix,
but this fix can't hurt.

llvm-svn: 129198
 2011-04-09 06:55:46 +00:00
Eli Friedman 4db39cefdb Test for r129190. 
llvm-svn: 129197
 2011-04-09 06:39:43 +00:00
Chris Lattner 418b1037b0 fix two completely broken tests, which were matching due to PR9629. 
llvm-svn: 129195
 2011-04-09 06:34:38 +00:00
Chris Lattner ea6afab4b0 remove a bunch of CHECK lines that aren't checking what 
they thought they were, because alternation was expanding
wrong in {{}}'s.

llvm-svn: 129194
 2011-04-09 06:31:06 +00:00
Chris Lattner 41c80e89f3 have dag combine zap "store undef", which can be formed during call lowering 
with undef arguments.

llvm-svn: 129185
 2011-04-09 02:32:02 +00:00
Chris Lattner 1c42a4d159 don't test for codegen of 'store undef' 
llvm-svn: 129184
 2011-04-09 02:31:26 +00:00
Devang Patel 12599c2187 Add radar number for future reference. 
llvm-svn: 129172
 2011-04-08 23:52:04 +00:00
Devang Patel e39647951b Do not emit DW_AT_upper_bound and DW_AT_lower_bound for unbouded array. 
If lower bound is more then upper bound then consider it is an unbounded array.
An array is unbounded if non-zero lower bound is same as upper bound.
If lower bound and upper bound are zero than array has one element.

llvm-svn: 129156
 2011-04-08 21:55:10 +00:00
Evan Cheng 74d92c1924 Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time. 
llvm-svn: 129152
 2011-04-08 21:37:21 +00:00
Johnny Chen a9570f77d5 Hanlde the checking of bad regs for SMMLAR properly, instead of asserting. 
PR9650
rdar://problem/9257565

llvm-svn: 129147
 2011-04-08 19:41:22 +00:00
Johnny Chen 875e0e4626 Sanity check the option operand for DMB/DSB. 
PR9648
rdar://problem/9257634

llvm-svn: 129146
 2011-04-08 19:18:07 +00:00
Johnny Chen 74c74ba81c MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it. 
Add tests for that.

llvm-svn: 129137
 2011-04-08 17:29:58 +00:00
Johnny Chen 7e51b4640f Add sanity checking for bad register specifier(s) for the DPFrm instructions. 
Add more test cases to exercise the logical branches related to the above change.

llvm-svn: 129117
 2011-04-08 00:29:09 +00:00
Rafael Espindola 9a1a34b105 Update tests 
llvm-svn: 129116
 2011-04-07 23:51:25 +00:00
Devang Patel bc3d8b212f Do not let debug info interfer with branch folding. 
llvm-svn: 129114
 2011-04-07 23:11:25 +00:00
Johnny Chen 165a07adf9 Add a VEXT test. 
llvm-svn: 129111
 2011-04-07 22:04:01 +00:00
Evan Cheng 9a3f2772f0 Add option to emit @llvm.trap as a function call instead of a trap instruction. rdar://9249183. 
llvm-svn: 129107
 2011-04-07 20:31:12 +00:00
Rafael Espindola 88bc341061 Add support for .skip. 
Patch by Roman Divacky.
Fixes PR9361.

llvm-svn: 129106
 2011-04-07 20:26:23 +00:00
Andrew Trick 2ad0b37318 Added a check in the preRA scheduler for potential interference on a 
induction variable. The preRA scheduler is unaware of induction vars,
so we look for potential "virtual register cycles" instead.

Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing

llvm-svn: 129100
 2011-04-07 19:54:57 +00:00
Akira Hatanaka d6f1c58914 Fix handling of functions with internal linkage. 
llvm-svn: 129099
 2011-04-07 19:51:44 +00:00
Johnny Chen 04efb8f6ce Add sanity checking for invalid register encodings for signed/unsigned extend instructions. 
Add some test cases.

llvm-svn: 129098
 2011-04-07 19:28:58 +00:00
Johnny Chen 07606661f9 Add sanity checking for invalid register encodings for saturating instructions. 
llvm-svn: 129096
 2011-04-07 19:02:08 +00:00
Johnny Chen 194a2267ad Add some more comments about checkings of invalid register numbers. 
And two test cases.

llvm-svn: 129090
 2011-04-07 18:33:19 +00:00
Devang Patel 197c35298a While hoisting common code from if/else, hoist debug info intrinsics if they match. 
llvm-svn: 129078
 2011-04-07 17:27:36 +00:00
Tanya Lattner 266792a55a Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases. 
llvm-svn: 129074
 2011-04-07 15:24:20 +00:00
Johnny Chen 313ec7953a Sanity check MSRi for invalid mask values and reject it as invalid. 
rdar://problem/9246844

llvm-svn: 129050
 2011-04-07 01:37:34 +00:00
Eli Friedman c5f22a7815 PR9634: Don't unconditionally tell the AliasSetTracker that the PreheaderLoad 
is equivalent to any other relevant value; it isn't true in general.
If it is equivalent, the LoopPromoter will tell the AST the equivalence.
Also, delete the PreheaderLoad if it is unused.

Chris, since you were the last one to make major changes here, can you check
that this is sane?

llvm-svn: 129049
 2011-04-07 01:35:06 +00:00
Johnny Chen c0e86fb965 The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values 
for USAD8 and USADA8.

rdar://problem/9247060

llvm-svn: 129047
 2011-04-07 01:05:52 +00:00
Evan Cheng a7c7b54dde Change -arm-divmod-libcall to a target neutral option. 
llvm-svn: 129045
 2011-04-07 00:58:44 +00:00
Johnny Chen d4cced54b3 Should also check SMLAD for invalid register values. 
rdar://problem/9246650

llvm-svn: 129042
 2011-04-07 00:50:25 +00:00
Owen Anderson bdff1c997a Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for folded comparisons, just like ADD and SUB. 
llvm-svn: 129038
 2011-04-06 23:35:59 +00:00
Johnny Chen bd9a4f8d07 A8.6.393 
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.

So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

	vst2.32	{d0, d2}, [r3, :256], r3

we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^

llvm-svn: 129033
 2011-04-06 22:14:48 +00:00
Johnny Chen 2ac486e387 A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP" 
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.

rdar://problem/9239922
rdar://problem/9239596

llvm-svn: 129027
 2011-04-06 20:49:02 +00:00
Johnny Chen 8bca174f48 Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong. 
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.

rdar://problem/9240648

llvm-svn: 129015
 2011-04-06 18:27:46 +00:00
Nadav Rotem cc771acd77 This testcase passed even without the fix. Added the target info to make the 
test fail (without the fix). Thanks Dan.

llvm-svn: 128999
 2011-04-06 11:18:29 +00:00
Johnny Chen 0ec0e98a6a Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function. 
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0.  Otherwise, we should reject the insn as invalid.

rdar://problem/9239347
rdar://problem/9239467

llvm-svn: 128977
 2011-04-06 01:18:32 +00:00
Johnny Chen f6e327c6a3 Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register 
encodings for DisassembleArithMiscFrm().

rdar://problem/9238659

llvm-svn: 128958
 2011-04-05 23:28:00 +00:00
Johnny Chen c3656d29f6 A7.3 register encoding 
Qd -> bit[12] == 0
    Qn -> bit[16] == 0
    Qm -> bit[0]  == 0

If one of these bits is 1, the instruction is UNDEFINED.

rdar://problem/9238399
rdar://problem/9238445

llvm-svn: 128949
 2011-04-05 22:57:07 +00:00
Johnny Chen 9da60e016b ARM disassembler was erroneously accepting an invalid RSC instruction. 
Added checks for regs which should not be 15.

rdar://problem/9237734

llvm-svn: 128945
 2011-04-05 22:18:07 +00:00
Chris Lattner 57ee5a5db7 remove postdom frontiers, because it is dead. Forward dom frontiers are 
still used by RegionInfo :(

llvm-svn: 128943
 2011-04-05 21:57:17 +00:00
Johnny Chen 25883487a1 ARM disassembler was erroneously accepting an invalid LSL instruction. 
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.

rdar://problem/9237693

llvm-svn: 128941
 2011-04-05 21:49:44 +00:00
Jakob Stoklund Olesen 1ec41e2bd9 These tests no longer require linear scan because reserved register coalescing is now universal. 
llvm-svn: 128936
 2011-04-05 21:40:41 +00:00
Jakob Stoklund Olesen 6aa0fbf4c0 Run LiveDebugVariables in RegAllocBasic and RegAllocGreedy. 
llvm-svn: 128935
 2011-04-05 21:40:37 +00:00
Johnny Chen e9c644d4a0 The r128085 checkin modified the operand ordering for MRC/MRC2 instructions. 
Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.

rdar://problem/9236873

llvm-svn: 128922
 2011-04-05 20:32:23 +00:00
Jakob Stoklund Olesen e20fec7732 Fix one more batch of X86 tests to be register allocation dependent. 
llvm-svn: 128919
 2011-04-05 20:20:30 +00:00
Jakob Stoklund Olesen 18fd84c79a When dead code elimination removes all but one use, try to fold the single def into the remaining use. 
Rematerialization can leave single-use loads behind that we might as well fold whenever possible.

llvm-svn: 128918
 2011-04-05 20:20:26 +00:00
Johnny Chen 151582492d ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error. 
llvm-svn: 128913
 2011-04-05 19:42:11 +00:00
Johnny Chen 56c15c64b0 LDRD now prints out two dst registers. 
llvm-svn: 128909
 2011-04-05 18:53:14 +00:00
Johnny Chen 293875ef55 Fix test-llvm failures. 
llvm-svn: 128906
 2011-04-05 18:41:40 +00:00