327188aa15
AMDGPU: Select branch on undef to uniform scc branch
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llvm-svn: 289877
2016-12-15 21:57:11 +00:00
115a61560e
AMDGPU: Add VI i16 support
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Patch By: Wei Ding
Differential Revision: https://reviews.llvm.org/D18049
llvm-svn: 286464
2016-11-10 16:02:37 +00:00
f530e8b3f0
AMDGPU: Remove unnecessary and on conditional branch
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The comment explaining why this was necessary is incorrect
in its description of v_cmp's behavior for inactive workitems.
llvm-svn: 286134
2016-11-07 19:09:33 +00:00
2d2d33f1dc
Revert "AMDGPU: Add VI i16 support"
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This reverts commit r285939 and r285948. These broke some conformance tests.
llvm-svn: 285995
2016-11-04 13:06:34 +00:00
2b3379cdff
AMDGPU: Add VI i16 support
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Patch By: Wei Ding
Differential Revision: https://reviews.llvm.org/D18049
llvm-svn: 285939
2016-11-03 17:13:50 +00:00
8d1052f55c
DAGCombiner: Reduce 64-bit BFE pattern to pattern on 32-bit component
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If the extracted bits are restricted to the upper half or lower half,
this can be truncated.
llvm-svn: 267024
2016-04-21 18:03:06 +00:00
59b8b77405
AMDGPU: Set HasExtractBitInsn
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This currently does not have the control over the bitwidth,
and there are missing optimizations to reduce the integer to
32-bit if it can be.
But in most situations we do want the sinking to occur.
llvm-svn: 262296
2016-03-01 04:58:17 +00:00
Matt Arsenault