Commit Graph

116775 Commits

Author SHA1 Message Date
Elena Demikhovsky 9ebd877a10 AVX-512: enabled tests for AVX512F set
llvm-svn: 236416
2015-05-04 11:09:41 +00:00
Elena Demikhovsky 2557a22be7 AVX-512: Added VPACK* instructions forms for KNL and SKX
and their intrinsics
by Asaf Badouh (asaf.badouh@intel.com)

llvm-svn: 236414
2015-05-04 09:14:02 +00:00
Yaron Keren f8e6517591 Replace windows_error calls with mapWindowsError.
After r210687, windows_error does nothing but call mapWindowsError.
Other Windows/*.inc files directly call mapWindowsError. This patch
updates Path.inc and Process.inc to do the same.

llvm-svn: 236409
2015-05-04 04:48:10 +00:00
Justin Bogner 65337d1f3a llvm-cov: Warn if object file is newer than profile
Looking at coverage with an out of date profile can be confusing.
Provide a little hint that something might be wrong.

llvm-svn: 236408
2015-05-04 04:09:38 +00:00
Jonathan Roelofs 949d55d87a Deprecate in-source autotools builds
This is a followup from:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20150323/268067.html

Upgrade instructions:
  $ mv llvm/include/llvm/Config/config.h ./config.h.BACKUP
  # copy the configure line from line 7 of llvm/config.log
  # (for example: `$ ./configure --no-create --no-recursion`)
  $ mkdir build
  $ cd build
  # run the configure line, but this time with '../llvm' at the beginning:
  $ ../llvm/configure --no-create --no-recursion

These warnings will soon be turned into hard errors after a week.  Speak up now
if this is going to be a problem for you.

llvm-svn: 236399
2015-05-04 02:04:54 +00:00
Craig Topper 23fdafe682 [TableGen] Replace 'static_cast' with 'cast'.
llvm-svn: 236398
2015-05-04 01:35:42 +00:00
Craig Topper a9642b4ec8 [TableGen] Formatting cleanup. Mostly removing trailing whitespace and unnecessary curly braces. NFC
llvm-svn: 236397
2015-05-04 01:35:39 +00:00
Elena Demikhovsky 1b60ed7069 Masked gather and scatter intrinsics - enabled codegen for KNL.
llvm-svn: 236394
2015-05-03 07:12:25 +00:00
Nico Weber 4b5b1ac997 Fix typo in comment.
llvm-svn: 236392
2015-05-02 21:34:39 +00:00
Simon Pilgrim d5e20306cc [SSE2] Minor tidyup of v16i8 SHL lowering. NFC.
Removed code that was replicating v8i16 'shift + mask' implementation that is done more nicely by making use of LowerScalarImmediateShift

llvm-svn: 236388
2015-05-02 14:42:43 +00:00
Simon Pilgrim 017ca19384 [DAGCombiner] Enabled vector float/double -> int constant folding
llvm-svn: 236387
2015-05-02 13:04:07 +00:00
Simon Pilgrim e170a4f5fa Line ending fix
llvm-svn: 236386
2015-05-02 11:50:47 +00:00
Simon Pilgrim 7d6df82dd1 [SSE] Added vector int (i32 and i64) -> float/double conversion tests
llvm-svn: 236385
2015-05-02 11:42:47 +00:00
Simon Pilgrim 6e3b7bad11 [SSE] Added vector float/double -> i32 and i64 conversion tests
llvm-svn: 236384
2015-05-02 11:18:47 +00:00
David Blaikie 72d03efa6d DebugInfo: Use low_pc relative debug_ranges under fission when the CU has a low_pc
Seems we were setting the base address on the wrong DwarfCompileUnit
object so it wasn't being used when generating the ranges.

llvm-svn: 236377
2015-05-02 02:31:49 +00:00
Eric Christopher a2d44dee73 Rework test to use FileCheck by making sure we have no xmm registers
with numbers.

llvm-svn: 236373
2015-05-02 01:06:17 +00:00
Jim Grosbach ae4c2649dc MC: Tidy up comments and clean up formatting a bit. NFC.
llvm-svn: 236368
2015-05-02 00:44:14 +00:00
Jim Grosbach bfe3a9c318 Fix spelling.
llvm-svn: 236367
2015-05-02 00:44:07 +00:00
Reid Kleckner 83d89fa546 Revert "[WinEH] Add an EH registration and state insertion pass for 32-bit x86"
This reverts commit r236359. Things are still broken despite testing. :(

llvm-svn: 236360
2015-05-01 22:50:14 +00:00
Reid Kleckner 51476acd77 Re-land "[WinEH] Add an EH registration and state insertion pass for 32-bit x86"
This reverts commit r236340.

llvm-svn: 236359
2015-05-01 22:40:25 +00:00
Colin LeMahieu bb0d7cbee1 [Hexagon] r236351 fix does not work on builder configurations yet.
llvm-svn: 236358
2015-05-01 22:39:20 +00:00
Quentin Colombet 0de2346859 [AArch64][FastISel] Variant of the logical instructions that use two input
registers cannot write on SP.

rdar://problem/20748715

llvm-svn: 236352
2015-05-01 21:34:57 +00:00
Colin LeMahieu 6efd273a61 [Hexagon] Removing variable unused in release.
llvm-svn: 236351
2015-05-01 21:30:22 +00:00
Colin LeMahieu b662565475 [Hexagon] Adding expression MC emission and removing XFAIL from test that hits this code path.
llvm-svn: 236348
2015-05-01 21:14:21 +00:00
Quentin Colombet 9df2fa261b [AArch64][FastISel] Fix the setting of kill flags for MUL -> UMULH sequences.
rdar://problem/20748715

llvm-svn: 236346
2015-05-01 20:57:11 +00:00
Zachary Turner 292e92d99d Fix compilation of PDBApiTest.
llvm-svn: 236345
2015-05-01 20:51:49 +00:00
Zachary Turner 6799af41fe Fix build.
llvm-svn: 236343
2015-05-01 20:33:10 +00:00
Zachary Turner e5cb269352 [llvm-pdbdump] Support dynamic load address and external symbols.
This patch adds the --load-address command line option to
llvm-pdbdump, which dumps all addresses assuming the module has
loaded at the specified address.

Additionally, this patch adds an option to llvm-pdbdump to support
dumping of public symbols (i.e. symbols with external linkage).

llvm-svn: 236342
2015-05-01 20:24:26 +00:00
Keno Fischer e6892c8149 Reapply [RuntimeDyldELF] Fold Placeholder into Addend
This reapplies r235060 and 235070, which were reverted because of test failures
in LLDB. The failure was caused because at  moment RuntimeDyld is processing
relocations for all sections, irrespective of whether we actually load them
into memory or not, but RuntimeDyld was not actually remembering where in memory
the unrelocated section is. This commit includes a fix for that issue by
remembering that pointer, though the longer term fix should be to stop processing
unneeded sections.

Original Summary:

This allows us to get rid of the original unrelocated object file after
we're done processing relocations (but before applying them).
MachO and COFF already do not require this (currently we have temporary hacks
to prevent ownership from being released, but those are brittle and should be
removed soon).

The placeholder mechanism allowed the relocation resolver to look at original
object file to obtain more information that are required to apply the
relocations. This is usually necessary in two cases:

- For relocations targetting sub-word memory locations, there may be pieces
  of the instruction at the target address which we should not override.
- Some relocations on some platforms allow an extra addend to be encoded in
  their immediate fields.

The problem is that in the second case the information cannot be recovered
after the relocations have been applied once because they will have been
overridden. In the first case we also need to be careful to not use any bits
that aren't fixed and may have been overriden by applying a first relocation.

In the past both have been fixed by just looking at original object file. This
patch attempts to recover the information from the first by looking at the
relocated object file, while the extra addend in the second case is read
upon relocation processing and addend to the regular addend.

I have tested this on X86. Other platforms represent my best understanding
of how those relocations should work, but I may have missed something because
I do not have access to those platforms.
We will keep the ugly workarounds in place for a couple of days, so this commit
can be reverted if it breaks the bots.

Differential Revision: http://reviews.llvm.org/D9028

llvm-svn: 236341
2015-05-01 20:21:45 +00:00
Reid Kleckner 2747d3d55a Revert "[WinEH] Add an EH registration and state insertion pass for 32-bit x86"
This reverts commit r236339, it breaks the win32 clang-cl self-host.

llvm-svn: 236340
2015-05-01 20:14:04 +00:00
Reid Kleckner 4856fc61b4 [WinEH] Add an EH registration and state insertion pass for 32-bit x86
This pass is responsible for constructing the EH registration object
that gets linked into fs:00, which is all it does in this change. In the
future, it will also insert stores to update the EH state number.

I considered keeping this functionality in WinEHPrepare, but it's pretty
separable and X86 specific. It has conceptually very little to do with
the task of WinEHPrepare, which is currently outlining.  WinEHPrepare is
also in theory useful on ARM, but this logic is pretty x86 specific.

Reviewers: andrew.w.kaylor, majnemer

Differential Revision: http://reviews.llvm.org/D9422

llvm-svn: 236339
2015-05-01 20:04:54 +00:00
Pete Cooper f68d5038e6 [ARM] Transfer the internal flag in thumb2 size reduction.
Converting from t2LDRs to tLDRr caused the shift argument to drop the internal flag.  This would then throw machine verifier errors.

Unfortunately i'm having trouble reducing a test case.  I'm going to keep trying, but so far its a scary combination of machine sinking, an 'and i1', loads feeding loads, and a bunch of code which shouldn't change IT block formation, but does.  Its not useful to commit a test in that state as we have no way of knowing if it even hits this code reliably in future.

rdar://problem/20752113

llvm-svn: 236333
2015-05-01 18:57:32 +00:00
Douglas Katzman e2e72382b9 Move unit test into anonymous namespace as per convention.
llvm-svn: 236332
2015-05-01 18:51:06 +00:00
Alex Lorenz 42e91fa312 YAML: Fix the output of sequences that contain flow sequences.
This patch fixes a bug where the YAML Output class emitted
a sequence of flow sequences without the '-' characters.
Before:
  
  seq:
    [ a, b ]
    [ c, d ]

After:

  seq:
    - [ a, b ]
    - [ c, d ]


Reviewers: Justin Bogner

Differential Revision: http://reviews.llvm.org/D9206

llvm-svn: 236329
2015-05-01 18:34:25 +00:00
Alex Lorenz 684379a00b Update YamlIO documentation for the ScalarTraits class.
This patch adds the missing context parameter to the
input and output methods in ScalarTraits.

Differential Revision: http://reviews.llvm.org/D9173

llvm-svn: 236328
2015-05-01 18:20:23 +00:00
Peter Collingbourne d27d3a151f ARM: Align functions containing Thumb-2 jump tables to 4 bytes.
Functions with jump tables need an alignment of 4 because they use the ADR
instruction, which aligns the PC to 4 bytes before adding an offset.

Differential Revision: http://reviews.llvm.org/D9424

llvm-svn: 236327
2015-05-01 18:05:59 +00:00
Diego Novillo a7b5c5b584 Fix infinite recursion in ScaledNumber::toInt.
Patch from dexonsmith. The call to toInt() was calling compareTo() which
in some cases would call back to toInt(), creating an infinite loop.

Fixed by simplifying the logic in compareTo() to avoid the co-recursion.

llvm-svn: 236326
2015-05-01 17:59:15 +00:00
James Y Knight 35e04e84fa [Sparc] Repair fixups in little endian mode.
Differential Revision: http://reviews.llvm.org/D9434

llvm-svn: 236324
2015-05-01 17:13:02 +00:00
Douglas Katzman 49e96132ce Fix omission from adding sparcel (original http://reviews.llvm.org/D9263)
"obviously" it needs to go in parseArch *and* getArchTypeForLLVMName.

Differential Revision: http://reviews.llvm.org/D9436

llvm-svn: 236322
2015-05-01 16:49:58 +00:00
Benjamin Kramer 5de990ebca Remove std::move on return of temporary.
No functionality change. Found by -Wpessimizing-move.

llvm-svn: 236318
2015-05-01 15:26:22 +00:00
Benjamin Kramer d5a0b345bb Remove std::move on return of temporary.
No functionality change. Found by -Wpessimizing-move.

llvm-svn: 236317
2015-05-01 15:25:29 +00:00
Benjamin Kramer 548e8a405c Remove std::move on return when it could prevent copy elision.
Found by -Wpessimizing-move, no functional change. The APFloat and
PassManager change doesn't affect codegen as returning a by-value
argument will always result in a move.

llvm-svn: 236316
2015-05-01 15:16:11 +00:00
Toma Tabacu 00e9867988 [mips] [IAS] Fix error messages for using LI with 64-bit immediates.
Summary:
LI should never accept immediates larger than 32 bits.
The additional Is32BitImm boolean also paves the way for unifying the functionality that LA and LI have in common.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9289

llvm-svn: 236313
2015-05-01 12:19:27 +00:00
Niels Ole Salscheider b0e3c348ab [CMake] Also search for prefixed versions of ld.gold
llvm-svn: 236312
2015-05-01 11:58:30 +00:00
Toma Tabacu a2861db834 [mips] [IAS] Slightly improve shift instruction generation in expandLoadImm.
Summary:
Generate one DSLL32 of 0 instead of two consecutive DSLL of 16.
In order to do this I had to change createLShiftOri's template argument from a bool to an unsigned.

This also gave me the opportunity to rewrite the mips64-expansions.s test, as it was testing the same cases multiple times and skipping over other cases.
It was also somewhat unreadable, as the CHECK lines were grouped in a huge block of text at the beginning of the file.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8974

llvm-svn: 236311
2015-05-01 10:26:47 +00:00
Simon Pilgrim 9fb06bca67 [SelectionDAG] Unary vector constant folding integer legality fixes
This patch fixes issues with vector constant folding not correctly handling scalar input operands if they require implicit truncation - this was tested with llvm-stress as recommended by Patrik H Hagglund.

The patch ensures that integer input scalars from a build vector are correctly truncated before folding, and that constant integer scalar results are promoted to a legal type before inclusion in the new folded build vector.

I have added another crash test case and also a test for UINT_TO_FP / SINT_TO_FP using an non-truncated scalar input, which was failing before this patch.

Differential Revision: http://reviews.llvm.org/D9282

llvm-svn: 236308
2015-05-01 08:20:04 +00:00
Tom Stellard aa798340c3 R600/SI: Add VCC as an implict def of SI_KILL
When SI_KILL has a register operand, its lowered form writes to vcc.

llvm-svn: 236307
2015-05-01 03:44:09 +00:00
Tom Stellard 0b7feb1cb7 R600/SI: Fix verifier errors from the SIAnnotateControlFlow pass
This pass was generating 'Instruction does not dominate all uses!'
errors for programs which had loops with a condition variable that
depended on the result of a phi instruction from outside of the loop.

The pass was inserting new phi nodes outside of the loop which used values
defined inside the loop.

http://bugs.freedesktop.org/show_bug.cgi?id=90056

llvm-svn: 236306
2015-05-01 03:44:08 +00:00
Quentin Colombet 65b5b01d56 [ARM][TEST] Strengthen test against smarter reg alloc.
Follow-up of r236247.

rdar://problem/20770899

llvm-svn: 236296
2015-05-01 00:45:55 +00:00
Pete Cooper 2127b00cd5 [ARM] optimizeSelect should clear kill flags.
If we move an instruction from one block down to a MOVC and predicate it,
then the original instruction could be moved in to a loop.  In this case,
its invalid for any kill flags to remain on there.

Fails with -verfy-machineinstrs.

rdar://problem/20752113

llvm-svn: 236290
2015-04-30 23:57:47 +00:00
Justin Bogner ba1900cefd InstrProf: Instrumenter support for setting profile output from command line
This change is the second of 3 patches to add support for specifying
the profile output from the command line via -fprofile-instr-generate=<path>,
where the specified output path/file will be overridden by the
LLVM_PROFILE_FILE environment variable.

This patch adds the necessary support to the llvm instrumenter, specifically
a new member of GCOVOptions for clang to save the specified filename, and
support for calling the new compiler-rt interface from __llvm_profile_init.

Patch by Teresa Johnson. Thanks!

llvm-svn: 236288
2015-04-30 23:49:23 +00:00
Matt Arsenault 59d2ca1cba Fix typo
llvm-svn: 236283
2015-04-30 23:20:56 +00:00
Pete Cooper 451755d370 Commute the internal flag on MachineOperands.
When commuting a thumb instruction in the size reduction pass, thumb
instructions are represented as a bundle and so some operands may be marked
as internal.  The internal flag has to move with the operand when commuting.

This test is sensitive to register allocation so can't specifically check that
this error was happening, but so long as it continues to pass with -verify then
hopefully its still ok.

rdar://problem/20752113

llvm-svn: 236282
2015-04-30 23:14:14 +00:00
Davide Italiano cd2514dca6 [Object] Teach Object and llvm-objdump about ".hidden"
Differential Revision:	http://reviews.llvm.org/D9416
Reviewed by:	rafael

llvm-svn: 236279
2015-04-30 23:08:53 +00:00
Richard Trieu 6ae37961a8 Fix -Wpessimizing-move warnings by removing std::move calls.
llvm-svn: 236278
2015-04-30 23:07:00 +00:00
Rafael Espindola 327fd4a255 Remove unnecessary break.
llvm-svn: 236275
2015-04-30 22:41:12 +00:00
Quentin Colombet 329fa890ba [AArch64] Fix bad register class constraint in fast-isel for TST instruction.
rdar://problem/20748715

llvm-svn: 236273
2015-04-30 22:27:20 +00:00
Pete Cooper 5111881cfc Don't always apply kill flag in thumb2 ABS pseudo expansion.
The expansion for t2ABS was always setting the kill flag on the rsb instruction.
It should instead only be set on rsb if it was set on the original ABS instruction.

rdar://problem/20752113

llvm-svn: 236272
2015-04-30 22:15:59 +00:00
Reid Kleckner 60d5232be2 [X86] Use 4 byte preferred aggregate alignment on Win32
This helps reduce the frequency of stack realignment prologues in 32-bit
X86 Windows code. Before this change and the corresponding clang change,
we would take the max of the type preferred alignment and the explicit
alignment on the alloca.

If you don't override aggregate alignment in datalayout, you get a
default of 8. This dates back to 2007 / r34356, and changing it seems
prohibitively difficult at this point.

llvm-svn: 236270
2015-04-30 22:11:59 +00:00
Matthias Braun e48484c64f InstCombineSimplifyDemanded: Remove nsw/nuw flags when optimizing demanded bits
When optimizing demanded bits of the operands of an Add we have to
remove the nsw/nuw flags as we have no guarantee anymore that we don't
wrap.  This is legal here because the top bit is not demanded.  In fact
this operaion was already performed but missed in the case of an Add
with a constant on the right side.  To fix this this patch refactors the
code to unify the code paths in SimplifyDemandedUseBits() handling of
Add/Sub:

- The transformation of Add->Or is removed from the simplify demand
  code because the equivalent transformation exists in
  InstCombiner::visitAdd()
- KnownOnes/KnownZero are not adjusted for Add x, C anymore as
  computeKnownBits() already performs these computations.
- The simplification of the operands is unified. In this new version
  constant on the right side of a Sub are shrunk now as I could not find
  a reason why not to do so.
- The special case for clearing nsw/nuw in ShrinkDemandedConstant() is
  not necessary anymore as the caller does that already.

Differential Revision: http://reviews.llvm.org/D9415

llvm-svn: 236269
2015-04-30 22:05:30 +00:00
Matthias Braun ec6833420f InstCombine: Move Sub->Xor rule from SimplifyDemanded to InstCombine
The rule that turns a sub to xor if the LHS is 2^n-1 and the remaining bits
are known zero, does not use the demanded bits at all: Move it to the
normal InstCombine code path.

Differential Revision: http://reviews.llvm.org/D9417

llvm-svn: 236268
2015-04-30 22:04:26 +00:00
Rafael Espindola 868b3f47d2 Simplify the creation of compressed debug sections.
This is actually fairly simple in the current code layout: Check if we should
compress just before writing out and everything else just works.

This removes the last case in which the object writer was creating a
fragment.

llvm-svn: 236267
2015-04-30 21:51:58 +00:00
Andrea Di Biagio 737a361006 Fix comment in test. NFC.
llvm-svn: 236262
2015-04-30 21:22:28 +00:00
Rafael Espindola 74ef480f8f Replace unreachable code with llvm_unreachable.
llvm-svn: 236261
2015-04-30 21:20:06 +00:00
Rafael Espindola b186391e2d Don't create a MCSectionData when we don't have to.
llvm-svn: 236260
2015-04-30 21:10:06 +00:00
Andrea Di Biagio c84b5bdd69 Fix for PR23103. Correctly propagate the 'IsUndef' flag to the register operands of a commuted instruction.
Revision 220239 exposed a latent bug in method
'TargetInstrInfo::commuteInstruction'. When commuting the operands of a machine
instruction, method 'commuteInstruction' didn't correctly propagate the
'IsUndef' flag to the register operands of the new (commuted) instruction.

Before this patch, the following instruction:
  %vreg4<def> = VADDSDrr  %vreg14, %vreg5<undef>; FR64:%vreg4,%vreg14,%vreg5

was wrongly converted by method 'commuteInstruction' into:
  %vreg4<def> = VADDSDrr  %vreg5, %vreg14<undef>; FR64:%vreg4,%vreg5,%vreg14

The correct instruction should have been:
  %vreg4<def> = VADDSDrr  %vreg5<undef>, %vreg14; FR64:%vreg4,%vreg5,%vreg14

This patch fixes the problem in method 'TargetInstrInfo::commuteInstruction'.
When swapping the operands of a machine instruction, we now make sure that
'IsUndef' flags are correctly set.
Added test case 'pr23103.ll'.

Differential Revision: http://reviews.llvm.org/D9406

llvm-svn: 236258
2015-04-30 21:03:29 +00:00
Rafael Espindola a001a32c31 Avoid an extra loop over the sections.
Add string to the section header string table as we add sections.

llvm-svn: 236257
2015-04-30 20:57:14 +00:00
Rafael Espindola 03d7abbbe5 Make the section table a member of ELFObjectWriter.
This avoids passing it around and lets us build a small helper to add
a section to the table.

llvm-svn: 236255
2015-04-30 20:53:27 +00:00
Rafael Espindola 657117f82c Nothing inherits from this, drop the protected:
llvm-svn: 236253
2015-04-30 20:37:36 +00:00
Kevin Enderby 8972e48bc8 For llvm-objdump, with the -archive-headers and -macho options, use the -non-verbose
option to print the archive headers using raw numeric values.  Also add the -archive-member-offsets
for use with these to also trigger printing of the offset of the archive member from the start
of the archive.

llvm-svn: 236252
2015-04-30 20:30:42 +00:00
Douglas Katzman 07920d8457 Exhaustively test all triples in TripleTest.
Iteration over all permutations didn't really work,
due to evolution of the underlying enums.

Differential Revision: http://reviews.llvm.org/D9057

llvm-svn: 236251
2015-04-30 20:08:44 +00:00
Matt Arsenault d42e017ee4 Mips: Remove dead declaration
llvm-svn: 236250
2015-04-30 19:35:43 +00:00
Matt Arsenault ee5c2ab734 MachineVerifier: Don't crash if MachineOperand has no parent
If you somehow added a MachineOperand to an instruction
that did not have the parent set, the verifier would
crash since it attempts to use the operand's parent.

llvm-svn: 236249
2015-04-30 19:35:41 +00:00
Pete Cooper 4d8d2ec3eb Don't rewrite jumps to empty BBs to landing pads.
In the test case here, the 'unreachable' BB was removed by BranchFolding because its empty.

It then rewrote the jump from 'entry' to jump to its fallthrough, which was a landing pad.

This results in 'entry' jumping to 2 different landing pads, which fails the machine verifier.

rdar://problem/20750162

llvm-svn: 236248
2015-04-30 18:58:23 +00:00
Quentin Colombet 0a905042cd [ARM] Do not generate invalid encoding for stack adjust, even if this is just
temporary.

Because of that:
1. The machine verifier was complaining on such code.
2. The generate code worked just because the thumb reduction size pass fixed the
opcode.

rdar://problem/20749824

llvm-svn: 236247
2015-04-30 18:52:49 +00:00
Tim Northover 03b99f66d7 AArch64: add BFC alias for the BFI/BFM instructions.
Unlike 32-bit ARM, AArch64 can use wzr/xzr to implement this without the need
for a separate instruction.

rdar://18679590

llvm-svn: 236245
2015-04-30 18:28:58 +00:00
Reid Kleckner 582786b6cc Add a note about permitting default member initializers
Use them in WinEHPrepare so that we can spot any toolchain bugs that
come up.

llvm-svn: 236244
2015-04-30 18:17:12 +00:00
Jan Vesely 808fff585b Reinstate revisions r234755, r234759, r234760
changes:
  Don't apply on hexagon and NVPTX since they no longer claim to support UADDO/USUBO
  Add location to getConstant
  Drop comment about the ops being turned into expand

llvm-svn: 236240
2015-04-30 17:15:56 +00:00
Daniel Berlin da23c0fde0 Move equality function for AliasAnalysis::Location from DenseMapInfo to Location struct so it can be used in other types of maps
llvm-svn: 236237
2015-04-30 16:15:07 +00:00
Rafael Espindola bda1980917 Write sections mostly in one pass.
During ELF writing, there is no need to further relax the sections, so we
should not be creating fragments. This patch avoids doing so in all cases
but debug section compression (that is next).

Also, the ELF format is fairly simple to write. We can do a single pass over
the sections to write them out and compute the section header table.

llvm-svn: 236235
2015-04-30 14:21:49 +00:00
Aaron Ballman 9cab732161 Silencing an "enumeral and non-enumeral type in conditional expression" warning; NFC.
llvm-svn: 236234
2015-04-30 14:03:12 +00:00
Rafael Espindola fc337022c7 Don't check for offsets in tests where it is not relevant.
llvm-svn: 236233
2015-04-30 13:57:06 +00:00
Diego Novillo 95c93fc6d2 Fix private constructor for ScaledNumber.
Summary:
The private constructor for ScaledNumber was using uint64_t instead of
DigitsT. This was preventing instantiations of ScaledNumber with
anything other than uint64_t types.

In implementing the tests, I ran into another issue. Operators >>= and
<<= did not have variants for accepting other ScaledNumber as the shift
argument. This is expected by the SCALED_NUMBER_BOP.

It makes no sense to allow shifting a ScaledNumber by another
ScaledNumber, so the patch includes two new templates for shifting
ScaledNumbers.

Reviewers: dexonsmith

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9350

llvm-svn: 236232
2015-04-30 13:22:48 +00:00
Rafael Espindola e740409d52 Check the entire content of the comdat group.
llvm-svn: 236230
2015-04-30 13:08:09 +00:00
Diego Novillo e1133e367b Fix typo in comment. NFC.
llvm-svn: 236227
2015-04-30 12:27:51 +00:00
Daniel Sanders 4d532b5617 [mips] Sorted instructions in mips64r6 disassembly tests. NFC.
llvm-svn: 236223
2015-04-30 10:52:42 +00:00
Daniel Sanders 811f21493c [mips][mips64r6] Sorted instructions in test. NFC.
llvm-svn: 236221
2015-04-30 10:23:48 +00:00
Daniel Sanders 59f89aa8ed [mips][msa] Rename main check prefix to 'ALL' in basic operations tests. NFC
Summary:
The majority of the checks are subtarget independent. The few that aren't
will be corrected shortly.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9340

llvm-svn: 236220
2015-04-30 09:57:37 +00:00
Daniel Sanders fa159165be [mips][msa] Use CHECK-LABEL where missing, and remove checks matching the .size directive. NFC.
Summary: 

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9339

llvm-svn: 236219
2015-04-30 09:56:30 +00:00
Daniel Sanders 90b059d555 [mips] Add missing signext attributes to MSA basic operations tests. NFC.
Summary:
This doesn't make much difference to MIPS32, but it will simplify a
MIPS64r6 bugfix which will follow shortly by removing unnecessary
sign-extension of parameters.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9338

llvm-svn: 236216
2015-04-30 09:24:09 +00:00
Pawel Bylica 0c2ab37be6 Add convenient overloads for CreateInsertElement and CreateExtractElement methods in IRBuilder
Summary:
This pathc add convenient overloads for CreateInsertElement and CreateExtractElement methods in IRBuilder
where vector index can be uint64_t instead of Value*.

Test Plan: Unit test included.

Reviewers: majnemer

Reviewed By: majnemer

Subscribers: majnemer, llvm-commits

Differential Revision: http://reviews.llvm.org/D9347

llvm-svn: 236214
2015-04-30 09:01:22 +00:00
Daniel Jasper 232778a7a0 Silence unused warning in non-assert builds.
llvm-svn: 236213
2015-04-30 09:01:21 +00:00
Daniel Jasper 0366cd23ac Inline local variable to silence unused warning.
llvm-svn: 236212
2015-04-30 08:51:13 +00:00
Elena Demikhovsky e1eda8a9e6 Masked gather and scatter - added DAGCombine visitors
and AVX-512 instruction selection patterns.
All other patches, including tests will follow.

http://reviews.llvm.org/D7665

llvm-svn: 236211
2015-04-30 08:38:48 +00:00
Simon Pilgrim ecf5875bd5 [SSE] Fix for MUL v16i8 on pre-SSE41 targets (PR23369).
Sign extension of i8 to i16 was placing the unpacked bytes in the lower byte instead of the upper byte.

llvm-svn: 236209
2015-04-30 08:23:16 +00:00
Craig Topper 85c07007ea [TableGen] Cleanup formatting by moving operators from beginning of line to end of previous line. NFC
llvm-svn: 236206
2015-04-30 05:54:22 +00:00
Craig Topper 9ed595e41d [TableGen] Used range-based for loop. NFC.
llvm-svn: 236205
2015-04-30 05:54:20 +00:00
Craig Topper 9ef76499b2 [TableGen] Merge a variable assignment and a return to drop curly braces. Fold an assignment into an if. Use auto on the result of a couple dyn_casts. NFC
llvm-svn: 236204
2015-04-30 05:12:52 +00:00
Sanjoy Das 08e95b4703 [InstCombine] Add new rule for MIN(MAX(~A, ~B), ~C) et. al.
Summary:
Optimizing these well are especially interesting for IRCE since it
"clamps" values by generating this sort of pattern through SCEV
expressions.

Depends on D9352.

Reviewers: majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9353

llvm-svn: 236203
2015-04-30 04:56:04 +00:00
Sanjoy Das a8c178f280 [InstCombine] Add a new formula for SMIN.
Summary:
After this change `MatchSelectPattern` recognizes the following form
of SMIN:

  Y >s C ? ~Y : ~C == ~Y <s ~C ? ~Y : ~C = SMIN(~Y, ~C)

Reviewers: majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9352

llvm-svn: 236202
2015-04-30 04:56:00 +00:00
Filipe Cabecinhas f8a16a952d Don't overflow GCTable
Summary: Bug found with AFL fuzz.

Reviewers: rafael, dexonsmith

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9361

llvm-svn: 236200
2015-04-30 04:09:41 +00:00
Owen Anderson d8a029c81b Semantically revert r236031, which is not a good idea for in-order targets.
At the least it should be guarded by some kind of target hook.
It also introduced catastrophic compile time and code quality
regressions on some out of tree targets (test case still being
reduced/sanitized).

Sanjay agreed with reverting this patch until these issues can be
resolved.

llvm-svn: 236199
2015-04-30 04:06:32 +00:00
Hans Wennborg 680a60f0d0 XFAIL test/CodeGen/Generic/MachineBranchProb.ll on Hexagon (PR23377)
llvm-svn: 236196
2015-04-30 01:59:04 +00:00
Filipe Cabecinhas 9a19e56306 Make sure Op->getType() is a PointerType before we cast<> it.
Bug found with AFL fuzz.

llvm-svn: 236193
2015-04-30 01:13:31 +00:00
Hans Wennborg 4b828d35fd Switch lowering: use profile info to build weight-balanced binary search trees
This will cause hot nodes to appear closer to the root.

The literature says building the tree like this makes it a near-optimal (in
terms of search time given key frequencies) binary search tree. In LLVM's case,
we can do up to 3 comparisons in each leaf node, so it might be better to opt
for lower tree height in some cases; that's something to look into in the
future.

Differential Revision: http://reviews.llvm.org/D9318

llvm-svn: 236192
2015-04-30 00:57:37 +00:00
Filipe Cabecinhas bad0779f63 Make sure we don't resize(0) when we get a fwdref with Idx == UINT_MAX
Make it an error instead.

Bug found with AFL fuzz.

llvm-svn: 236190
2015-04-30 00:52:42 +00:00
Rafael Espindola 34948e5e22 Store relocations in a map from MCSectionELF.
Saves finding the MCSectionData just to do a map lookup.

llvm-svn: 236189
2015-04-30 00:45:46 +00:00
Rafael Espindola b8cbb2678f Write relocations directly to the output stream. NFC.
llvm-svn: 236187
2015-04-30 00:30:40 +00:00
Ahmed Bougacha ace0593b42 Flip r236172 testcase RUN option ordering for BSD sed(1). NFC.
llvm-svn: 236186
2015-04-30 00:07:34 +00:00
Pete Cooper 46361a1ea1 Change x86 CMOVE_F to read it source, not write it.
This was breaking sqlite with the machine verifier because operand 0 was a def according to tablegen, but didn't have the 'isDef' flag set.

Looking at the ISA, its clear that this operand is a source as writing to st(0) is implicit.  So move the operand to the correct place in the td file.

rdar://problem/20751584

llvm-svn: 236183
2015-04-29 23:51:33 +00:00
Jonathan Roelofs 10b3acf215 Fix doxygen comment typo. NFC
llvm-svn: 236180
2015-04-29 23:33:32 +00:00
David Blaikie bf0a42ac09 [opaque pointer type] Store the value type of an alloca
llvm-svn: 236175
2015-04-29 23:00:35 +00:00
Reid Kleckner bcda1cd45a [WinEH] Start EH preparation for 32-bit x86, it uses no arguments
32-bit x86 MSVC-style exceptions are functionaly similar to 64-bit, but
they take no arguments. Instead, they implicitly use the value of EBP
passed in by the caller as a pointer to the parent's frame. In LLVM, we
can represent this as llvm.frameaddress(1), and feed that into all of
our calls to llvm.framerecover.

The next steps are:
- Add an alloca to the fs:00 linked list of handlers
- Add something like llvm.sjlj.lsda or generalize it to store in the
  alloca
- Move state number calculation to WinEHPrepare, arrange for
  FunctionLoweringInfo to call it
- Use the state numbers to insert explicit loads and stores in the IR

llvm-svn: 236172
2015-04-29 22:49:54 +00:00
Sanjay Patel 04b0e92766 generalize binop reassociation; NFC
Move the fold introduced in r236031:
http://reviews.llvm.org/rL236031

to its own helper function, so we can use it for other binops.

This is a preliminary step before partially solving:
https://llvm.org/bugs/show_bug.cgi?id=21768
https://llvm.org/bugs/show_bug.cgi?id=23116

llvm-svn: 236171
2015-04-29 22:30:02 +00:00
Pat Gavlin 022c5acad8 Run StatepointLowering.{cpp,h} through clang-format.
llvm-svn: 236166
2015-04-29 21:52:45 +00:00
Chris Bieneman 3e3ef2f28c [NFC] Updating FileCheck to reduce the std::vector interface used via cl::list.
llvm-svn: 236164
2015-04-29 21:45:24 +00:00
Chris Bieneman 664294cf37 [NFC] Converting to range-based for.
llvm-svn: 236163
2015-04-29 21:45:22 +00:00
David Blaikie f64246be72 [opaque pointer type] Pass GlobalAlias the actual pointer type rather than decomposing it into pointee type + address space
Many of the callers already have the pointer type anyway, and for the
couple of callers that don't it's pretty easy to call PointerType::get
on the pointee type and address space.

This avoids LLParser from using PointerType::getElementType when parsing
GlobalAliases from IR.

llvm-svn: 236160
2015-04-29 21:22:39 +00:00
Rafael Espindola 59f0e3182d Inline FragmentWriter into the only user.
llvm-svn: 236158
2015-04-29 21:13:30 +00:00
Rafael Espindola 91fd2778b0 Write the symbol table directly to the output file.
There is no need to first accumulate it in fragments.

llvm-svn: 236157
2015-04-29 21:09:32 +00:00
Sanjay Patel caf5180ff7 tidy up; NFC
llvm-svn: 236156
2015-04-29 21:01:41 +00:00
Rafael Espindola 8c7829b82f Use pwrite to write the number of sections.
This avoids having to compute the number upfront, which will be used in the
next patch.

llvm-svn: 236153
2015-04-29 20:39:37 +00:00
Sanjay Patel ee6678119d too much space again; NFC
llvm-svn: 236150
2015-04-29 20:38:02 +00:00
Rafael Espindola 88abc39d70 Write the string table directly to the output file.
There is no need to accumulate it in fragments first.

llvm-svn: 236148
2015-04-29 20:34:31 +00:00
Sanjay Patel 435efaadff too much space; NFC
llvm-svn: 236147
2015-04-29 20:32:57 +00:00
Douglas Katzman 9160e78ac8 [Sparc] Really add sparcel architecture support.
Mostly copy-and-paste from Sparc v8 architecture.

Differential Revision: http://reviews.llvm.org/D8741

llvm-svn: 236146
2015-04-29 20:30:57 +00:00
Rafael Espindola 88d1f632cf Write the section header string table directly to the output stream.
Instead of accumulating the content in a fragment first, just write it
to the output stream.

Also put it first in the section table, so that we never have to worry
about its index being >= SHN_LORESERVE.

llvm-svn: 236145
2015-04-29 20:25:24 +00:00
Jonathan Roelofs cf1ba1d8c0 Clean up docs references to './configure' in preparation for deprecating in-source builds
http://reviews.llvm.org/D8787

llvm-svn: 236144
2015-04-29 20:06:41 +00:00
Manman Ren 0e20822887 [AArch64] Refactor out codes that depend on specific CS save sequence.
No functionality change.

llvm-svn: 236143
2015-04-29 20:03:38 +00:00
Rafael Espindola ae7e4995ca Avoid a few const_cast.
llvm-svn: 236141
2015-04-29 19:20:10 +00:00
Tim Northover 5211715360 ARM: mark branch-like instructions with correct flags.
There's probably no way to test BXJ, but if the compiler ever did emit it
during CodeGen it would have to be a block terminator so "isBranch" is
appropriate.

BLX is more tricky. Clearly a call, but it affects surprisingly little.

rdar://18719544

llvm-svn: 236140
2015-04-29 19:16:38 +00:00
Douglas Katzman e0ff282d18 New architecture name - 'sparcel' for Sparc little-endian.
Differential Revision: http://reviews.llvm.org/D9263

llvm-svn: 236139
2015-04-29 19:15:08 +00:00
Douglas Katzman 9cb88b73c6 Make Sparc assembler accept parenthesized constant expressions.
Differential Revision: http://reviews.llvm.org/D9087

llvm-svn: 236137
2015-04-29 18:48:29 +00:00
Zoran Jovanovic 387ce30685 [mips][microMIPSr6] Implement MUL, MUH, MULU and MUHU instructions
Differential Revision: http://reviews.llvm.org/D8894

llvm-svn: 236131
2015-04-29 17:23:22 +00:00
Andrew Kaylor a33f159056 [WinEH] Fix minor bug in begincatch block splitting
llvm-svn: 236129
2015-04-29 17:21:26 +00:00
Reid Kleckner 97b7e26d13 Disable failing TestDevNull test on Windows
llvm-svn: 236126
2015-04-29 16:54:11 +00:00
Adrian Prantl ba6ec4b70b Temporarily relax a check in the debug info verifier.
The clang frontend helps out GDB by emitting the members of local anonymous
unions as artificial local variables with shared storage. When SROA splits
the storage for artificial local variables that are smaller than the entire
union, the overhang piece will be outside of the allotted space for the
variable and this check fails.

rdar://problem/20730771

llvm-svn: 236124
2015-04-29 16:52:17 +00:00
Reid Kleckner c695471365 [X86] Avoid mangling frameescape labels
x86 Windows uses the '_' prefix for all global symbols, and this was
mistakenly being applied to frameescape labels, which are not externally
visible global symbols. They use the private global prefix 'L'.

The *right* way to fix this is probably to stop masquerading this label
as an ExternalSymbol and create a new SDNode type. These labels are not
"external", and we know they will be resolved by assembly time. Having a
custom SDNode type would allow us to do better X86 address mode
matching, so it's probably worth doing eventually.

llvm-svn: 236123
2015-04-29 16:46:01 +00:00
Duncan P. N. Exon Smith a9308c49ef IR: Give 'DI' prefix to debug info metadata
Finish off PR23080 by renaming the debug info IR constructs from `MD*`
to `DI*`.  The last of the `DIDescriptor` classes were deleted in
r235356, and the last of the related typedefs removed in r235413, so
this has all baked for about a week.

Note: If you have out-of-tree code (like a frontend), I recommend that
you get everything compiling and tests passing with the *previous*
commit before updating to this one.  It'll be easier to keep track of
what code is using the `DIDescriptor` hierarchy and what you've already
updated, and I think you're extremely unlikely to insert bugs.  YMMV of
course.

Back to *this* commit: I did this using the rename-md-di-nodes.sh
upgrade script I've attached to PR23080 (both code and testcases) and
filtered through clang-format-diff.py.  I edited the tests for
test/Assembler/invalid-generic-debug-node-*.ll by hand since the columns
were off-by-three.  It should work on your out-of-tree testcases (and
code, if you've followed the advice in the previous paragraph).

Some of the tests are in badly named files now (e.g.,
test/Assembler/invalid-mdcompositetype-missing-tag.ll should be
'dicompositetype'); I'll come back and move the files in a follow-up
commit.

llvm-svn: 236120
2015-04-29 16:38:44 +00:00
Jan Vesely 7539548738 CodeGen: Default overflow operations to expand so we don't have to assume targets are lying
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: ab
Differential Revision: http://reviews.llvm.org/D9265

llvm-svn: 236119
2015-04-29 16:30:46 +00:00
Zoran Jovanovic cca29e8f6e [mips][microMIPSr6] Implement SUB and SUBU instructions
Differential Revision: http://reviews.llvm.org/D8764

llvm-svn: 236118
2015-04-29 16:22:46 +00:00
Zoran Jovanovic 5f34d44354 [mips][microMIPSr6] Implement ADD, ADDU and ADDIU instructions
Differential Revision: http://reviews.llvm.org/D8704

llvm-svn: 236111
2015-04-29 15:11:07 +00:00
James Y Knight c09bdfa4cb Sparc: Prefer reg+reg address encoding when only one register used.
Reg+%g0 is preferred to Reg+imm0 by the manual, and is what GCC produces.

Futhermore, reg+imm is invalid for the (not yet supported) "alternate
address space" instructions.

Differential Revision: http://reviews.llvm.org/D8753

llvm-svn: 236107
2015-04-29 14:54:44 +00:00
Rafael Espindola c54a0d0bf4 Relax assert to avoid spurious failures with /dev/null.
llvm-svn: 236106
2015-04-29 14:53:25 +00:00
Vasileios Kalintiris 1249e74648 Mips fast-isel - handle functions which return i8 or i6 .
Summary: Allow Mips fast-isel to handle functions which return i8/i16 signed/unsigned.

Test Plan:
Make check tests are forthcoming.
Already passes test-suite at O0/O2 for Mips 32 r1/r2

Reviewers: dsanders, rkotler

Subscribers: llvm-commits, rfuhler

Differential Revision: http://reviews.llvm.org/D6765

llvm-svn: 236103
2015-04-29 14:17:14 +00:00
Rafael Espindola cad91323dc Don't constrain the section order in tests that don't depend on it.
llvm-svn: 236102
2015-04-29 13:55:07 +00:00
Daniel Sanders 301f937765 [mips] Correct 128-bit shifts on 64-bit targets.
Summary:
The existing code was correct for 32-bit GPR's but not 64-bit GPR's. It now
accounts for both cases.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits, mohit.bhakkad, sagar

Differential Revision: http://reviews.llvm.org/D9337

llvm-svn: 236099
2015-04-29 12:28:58 +00:00
Toma Tabacu 79588100d7 [mips] [IAS] Inline assemble-time shifting out of createLShiftOri. NFC.
Summary:
Do the assemble-time shifts from createLShiftOri at the source, which groups all the shifting together, closer to the main logic path, and
store the results in concisely-named variables to improve code clarity.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8973

llvm-svn: 236096
2015-04-29 10:19:56 +00:00
Elena Demikhovsky a9f20495a2 fixed 80-chars; NFC
llvm-svn: 236093
2015-04-29 08:49:57 +00:00
Elena Demikhovsky ac969012ef Fixed masked gather/scatter switch-case
llvm-svn: 236092
2015-04-29 08:38:53 +00:00
Craig Topper 119998dbf1 [TableGen] Use range-based for loops. NFC.
llvm-svn: 236089
2015-04-29 07:13:14 +00:00
Craig Topper 39ba33b8f0 [TableGen] Fold a couple dyn_casts into the ifs that check their results. NFC
llvm-svn: 236088
2015-04-29 07:13:12 +00:00
Craig Topper ed5a950808 [TableGen] Replace some dyn_casts followed by an assert with just a regular cast which asserts internally. NFC
llvm-svn: 236087
2015-04-29 07:13:05 +00:00
Elena Demikhovsky 744fe0de33 fixed comments, blanks, nullptr; NFC
llvm-svn: 236086
2015-04-29 06:49:50 +00:00
Craig Topper eb4d7c6b70 [TableGen] Use range-based for loops. NFC
llvm-svn: 236083
2015-04-29 04:43:36 +00:00
Hans Wennborg ccc8c2477a Drop Dragonegg from the release export script
Follow-up to r236077.

llvm-svn: 236081
2015-04-29 02:36:43 +00:00
Filipe Cabecinhas 6fe8aabd45 Use an "early return" idiom for the error case. NFC
llvm-svn: 236080
2015-04-29 02:36:08 +00:00
Filipe Cabecinhas d8a1bcd0ad Check that we have a valid PointerType element type before calling get()
Same as r236073 but for PointerType.

Bug found with AFL fuzz.

llvm-svn: 236079
2015-04-29 02:27:28 +00:00
Filipe Cabecinhas 52d42c725a Use the ArrayType member function for array element types.
ArrayType and StructType accept the same types, so no test.

llvm-svn: 236078
2015-04-29 02:27:21 +00:00
Hans Wennborg 99ebb31283 Drop Dragonegg support from the release script
It doesn't have a maintainer and none of the release testers test it,
so I don't think it should be part of the release.

http://reviews.llvm.org/D9331

llvm-svn: 236077
2015-04-29 02:14:26 +00:00
Filipe Cabecinhas 1351cba720 Turn an assert into report_fatal_error since it's reachable based on user input
Bug found with AFL fuzz.

llvm-svn: 236076
2015-04-29 01:58:31 +00:00
Lang Hames f3a8362bf2 [Orc] It's not valid to pass a null resolver to addModuleSet. Use a no-op
resolver with a diagnostic instread.

llvm-svn: 236074
2015-04-29 01:33:35 +00:00
Filipe Cabecinhas f15fb032ef Make sure that isValidElementType(Type) before calling {Array,Struct}Type::get(Type)
Bug found with AFL fuzz.

llvm-svn: 236073
2015-04-29 01:27:01 +00:00
Matthias Braun 5295793bca RegisterCoalescer: hide terminal rule option by default
llvm-svn: 236062
2015-04-28 23:55:11 +00:00
Hans Wennborg bb66f202eb test-release.sh: Drop some unused command-line options.
These haven't done anything since before r142165.

llvm-svn: 236061
2015-04-28 23:37:41 +00:00
Rafael Espindola 89feff3b76 Map directly from signature symbol to group index. NFC.
llvm-svn: 236058
2015-04-28 22:59:58 +00:00
Eric Christopher 0ba41a6841 Reuse a lookup in an assert.
llvm-svn: 236054
2015-04-28 22:38:35 +00:00
Rafael Espindola cf6d5a9f94 Remove redundant temporary std::vector.
New sections are added to the end of the list, so the RelSections array was
redundant.

llvm-svn: 236053
2015-04-28 22:26:19 +00:00
Tim Northover e18d662201 ARM: fix peephole optimisation of TST
We were trying to look through COPY instructions, but only to the next
instruction in a BB and incorrectly anyway. The cases where that would actually
be a good idea are rare enough (and not even tested!) that it's not worth
trying to get right.

rdar://20721342

llvm-svn: 236050
2015-04-28 22:03:55 +00:00
Rafael Espindola 41920d0382 Avoid one more walk over all sections. NFC.
Set the group section index as they are created.

llvm-svn: 236049
2015-04-28 22:03:22 +00:00
Andrew Kaylor 91307434f4 Style updates
llvm-svn: 236048
2015-04-28 22:01:51 +00:00
Rafael Espindola fac3fbc5ff Use a range loop. NFC.
llvm-svn: 236047
2015-04-28 21:58:05 +00:00
Andrew Kaylor 046f7b42f2 [WinEH] Split blocks at calls to llvm.eh.begincatch
Differential Revision: http://reviews.llvm.org/D9311

llvm-svn: 236046
2015-04-28 21:54:14 +00:00
Rafael Espindola 8a90d87d76 Avoid an extra walk over the sections just to assign sections to groups.
Assign the sections in the same pass we compute the index.

llvm-svn: 236045
2015-04-28 21:52:33 +00:00
James Y Knight e8da8096ec Sparc: Add alternate aliases for conditional branch instructions.
llvm-svn: 236042
2015-04-28 21:27:31 +00:00
Reid Kleckner 2e49c605ad [SEH] Add an LLVM intrinsic for _exception_info
Eventually, we will lower this out during IR preparation.

llvm-svn: 236036
2015-04-28 21:20:42 +00:00
Rafael Espindola 55a3afb418 Remove the GroupMapTy DenseMap. NFC.
Instead use the Group symbol of MCSectionELF.

llvm-svn: 236033
2015-04-28 21:07:28 +00:00
Sanjay Patel 2fbc4e5c49 transform fadd chains to increase parallelism
This is a compromise: with this simple patch, we should always handle a chain of exactly 3
operations optimally, but we're not generating the optimal balanced binary tree for a longer
sequence.

In general, this transform will reduce the dependency chain for a sequence of instructions
using N operands from a worst case N-1 dependent operations to N/2 dependent operations. 
The optimal balanced binary tree would reduce the chain to log2(N).

The trade-off for not dealing with longer sequences is: (1) we have less complexity in the
compiler, (2) we avoid unknown compile-time blowup calculating a balanced tree, and (3) we
don't need to worry about the increased register pressure required to parallelize longer
sequences. It also seems unlikely that we would ever encounter really long strings of
dependent ops like that in the wild, but I'm not sure how to verify that speculation.
FWIW, I see no perf difference for test-suite running on btver2 (x86-64) with -ffast-math
and this patch.

We can extend this patch to cover other associative operations such as fmul, fmax, fmin, 
integer add, integer mul.

This is a partial fix for:
https://llvm.org/bugs/show_bug.cgi?id=17305

and if extended:
https://llvm.org/bugs/show_bug.cgi?id=21768
https://llvm.org/bugs/show_bug.cgi?id=23116

The issue also came up in:
http://reviews.llvm.org/D8941

Differential Revision: http://reviews.llvm.org/D9232

llvm-svn: 236031
2015-04-28 21:03:22 +00:00
Alexei Starovoitov 659ece9ddb [bpf] fix build
Patch by Brenden Blanco.

llvm-svn: 236030
2015-04-28 20:38:56 +00:00
Rafael Espindola ad3cfaaa20 Use range loops. NFC.
llvm-svn: 236028
2015-04-28 20:23:35 +00:00
Filipe Cabecinhas b435d0f439 Relax an assert when there's a type mismatch in forward references
Summary:
We don't seem to need to assert here, since this function's callers expect
to get a nullptr on error. This way we don't assert on user input.

Bug found with AFL fuzz.

Reviewers: rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9308

llvm-svn: 236027
2015-04-28 20:18:47 +00:00
Rafael Espindola e3ff9305cd Avoid adding to SectionIndexMap sections that we never lookup. NFC.
llvm-svn: 236026
2015-04-28 20:09:13 +00:00
Daniel Berlin ec1de3fb19 Make getModRefInfo(Instruction *) not crash on certain types of instructions
llvm-svn: 236023
2015-04-28 19:19:14 +00:00
Rafael Espindola 163f672cd5 Use a range loop. NFC.
llvm-svn: 236015
2015-04-28 19:07:16 +00:00
Sanjay Patel f75ee4dc07 [x86] remove RCPPS and RSQRTPS intrinsic instruction definitions
We don't need codegen-only intrinsic instructions for the vector forms of these instructions.

This makes the reciprocal estimate instruction lowering identical to how we handle normal
square roots: (V)SQRTPS / (V)SQRTPD.

No existing regression tests fail with this patch.

Differential Revision: http://reviews.llvm.org/D9301

llvm-svn: 236013
2015-04-28 18:48:45 +00:00
Eric Christopher 35a8a62125 Add a fixme to resetTargetOptions to explain why it needs to go
away.

llvm-svn: 236009
2015-04-28 18:09:05 +00:00
Eric Christopher f4bf3779d8 Fix a [-Werror,-Winconsistent-missing-override] problem in the
NVPTX overrides.

llvm-svn: 236007
2015-04-28 18:06:27 +00:00
Tom Stellard 96301d2455 R600: Fix up for AsmPrinter's OutStreamer being a unique_ptr
Fixes a crash with basically any OpenGL application using the radeonsi
driver.

Patch by: Michel Dänzer

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90176
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 236004
2015-04-28 17:37:03 +00:00
Tom Stellard 0a0fa03d5a R600/SI: Add a lower case alias for subtarget feature: +DumpCode
llc converts all feature strings to lower case, while the LLVM C API
does not, so we need a lower case alias in order to test this with llc.

llvm-svn: 236003
2015-04-28 17:37:00 +00:00
Justin Holewinski 3d2a976197 [NVPTX] Handle addrspacecast constant expressions in aggregate initializers
We need to track if an AddrSpaceCast expression was seen when
generating an MCExpr for a ConstantExpr.  This change introduces a
custom lowerConstant method to the NVPTX asm printer that will create
NVPTXGenericMCSymbolRefExpr nodes at the appropriate places to encode
the information that a given symbol needs to be casted to a generic
address.

llvm-svn: 236000
2015-04-28 17:18:30 +00:00
David Blaikie bdb4910202 [opaque pointer type] Encode the allocated type of an alloca rather than its pointer result type.
llvm-svn: 235998
2015-04-28 16:51:01 +00:00
Sanjay Patel ba55804ea3 move IR-level optimization flags into their own struct
This is a preliminary step to using the IR-level floating-point fast-math-flags in the SDAG (D8900).

In this patch, we introduce the optimization flags as their own struct. As noted in the TODO comment, 
we should eventually share this data between the IR passes and the backend.

We also switch the existing nsw / nuw / exact bit functionality of the BinaryWithFlagsSDNode class to
use the new struct.

The tradeoff is that instead of using the free but limited space of SDNode's SubclassData, we add a
data member to the subclass. This means we don't have to repeat all of the get/set methods per flag,
but we're potentially adding size to all nodes of this subclassi type.

In practice on 64-bit systems (measured on Linux and MacOS X), there is no size difference between an
SDNode and BinaryWithFlagsSDNode after this change: they're both 80 bytes. This means that we had at
least one free byte to play with due to struct alignment.

Differential Revision: http://reviews.llvm.org/D9325

llvm-svn: 235997
2015-04-28 16:39:12 +00:00
Rafael Espindola a820169711 Use a std::vector to record the offsets of the sections. NFC.
llvm-svn: 235995
2015-04-28 15:26:21 +00:00
Rafael Espindola b64175076f Avoid an extra loop for computing the section size. NFC.
llvm-svn: 235994
2015-04-28 15:04:09 +00:00
Elena Demikhovsky 1f7b3644d3 Fixed crash of variable shift inst on AVX2
https://llvm.org/bugs/show_bug.cgi?id=22955

llvm-svn: 235993
2015-04-28 14:46:35 +00:00
Toma Tabacu 7dea2e3982 [mips] [IAS] Do not generate redundant ORi in createLShiftOri.
Summary: If the immediate is 0, the ORi is pointless.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8969

llvm-svn: 235990
2015-04-28 14:06:35 +00:00
Sergey Dmitrouk 842a51bad8 Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"
[DebugInfo] Add debug locations to constant SD nodes

This adds debug location to constant nodes of Selection DAG and updates
all places that create constants to pass debug locations
(see PR13269).

Can't guarantee that all locations are correct, but in a lot of cases choice
is obvious, so most of them should be. At least all tests pass.

Tests for these changes do not cover everything, instead just check it for
SDNodes, ARM and AArch64 where it's easy to get incorrect locations on
constants.

This is not complete fix as FastISel contains workaround for wrong debug
locations, which drops locations from instructions on processing constants,
but there isn't currently a way to use debug locations from constants there
as llvm::Constant doesn't cache it (yet). Although this is a bit different
issue, not directly related to these changes.

Differential Revision: http://reviews.llvm.org/D9084

llvm-svn: 235989
2015-04-28 14:05:47 +00:00
Rafael Espindola effdc7e981 Use CIE version 4 for dwarf4.
According to http://www.dwarfstd.org/doc/DWARF4.pdf appendix F the CIE
version for dwarf 4 is 4.

llvm-svn: 235988
2015-04-28 13:55:31 +00:00
Daniel Jasper 48e93f7181 Revert "[DebugInfo] Add debug locations to constant SD nodes"
This breaks a test:
http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/23870

llvm-svn: 235987
2015-04-28 13:38:35 +00:00
Toma Tabacu 6114565269 [mips] [IAS] Rename the createShiftOr function to createLShiftOri. NFC.
Summary: The new name is more accurate with regard to the functionality.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8968

llvm-svn: 235984
2015-04-28 13:16:06 +00:00